JPS62160731A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve insulating characteristics, by performing thermal oxidation under the state a CVD oxide film is present, and forming a thermal oxide film having a uniform thickness on the surface of a silicon layer having irregularities. CONSTITUTION:An insulating film 2 is formed on a silicon substrate 1. A CVD oxide film 3 is deposited, and a groove 4 is formed. Thereafter, an oxide film 3 is removed, and an oxide film 5 by a CVD method is deposited. Thermal oxidation is performed, and a thermal oxide film 6 is formed on the surface of the silicon substrate 1 beneath the CVD oxide film 5. At a corner A at the recessed part, oxidation speed is decreased owing to the concentration of stress at the thermal oxidation. As a result, the interface between the formed thermal oxide film 6 and the silicon substrate 1 becomes round. At a corner B at the protruded part, stress concentration is similarly formed. At this part, the amount of oxygen, which is diffused in the CVD oxide film 5 and supplied to the silicon substrate 1, is more than that in the flat part. Therefore, the effect of the decrease in oxidation speed can be compensated. Thus, the thermal oxide film 6 becomes thick, and the round part is effectively formed. Therefore, the thickness of the corner part of a thermal oxide film 7 as a capacitor insulating film, which is finally formed, does not become thin.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a thermal oxide film with excellent insulation properties on the surface of a silicon layer having unevenness.

[Technical background of the invention and its problems]

In recent years, there has been a remarkable increase in the integration of dynamic RAMs (dRAMs) that use memory cells with a one-transistor/one-capacitor configuration. In this dRAM, a structure in which a trench is dug in the surface of the silicon substrate in the capacitor region to compensate for the decrease in capacitor capacitance due to higher integration, and the sidewalls of the trench are utilized to increase the capacitor area is considered promising. In this case, the usual method for forming grooves in microscopic regions of a silicon substrate is
An anisotropic dry etching process is used and the grooves are formed with substantially vertical sidewalls. However, a groove like this was formed. When a thermal oxide film serving as a capacitor insulating film is formed on the surface of a silicon substrate having irregularities, a phenomenon is observed in which the thickness of the thermal oxide film becomes thinner at the corners of the recesses and projections than at the flat parts. The reason for this is that the oxidation rate at the corners of the concave or convex portions is lower than that at the flat portions due to the concentration of stress that occurs during thermal oxidation. The concentration of stress is more significant as the radius of curvature of the unevenness is smaller, and therefore, the thermal oxide film is significantly thinner at corners where the radius of curvature is smaller.

Due to the demands for miniaturization of elements and securing capacitor capacity,
The capacitor insulating film is formed as thin as possible, but for the reasons mentioned above, the capacitor insulating film becomes extremely thin at some corners of the trench type capacitor. On the other hand, when an electric field is applied to the insulating film of a grooved capacitor, the electric field tends to concentrate at the corners of the concave or convex portions. For this reason, if the oxide film in a part of this corner is extremely thin, the so-called F
A large tunneling current due to the Owler-N ordheim mechanism flows, and the insulation properties are significantly worse than that of a planar capacitor. This greatly degrades the data retention characteristics of dRAM.

[Purpose of the invention]

In view of the above points, the present invention aims to improve the insulation properties of a thermal oxide film formed on the surface of a silicon layer having unevenness, thereby providing a method for manufacturing a semiconductor device that makes it possible to improve the properties of devices such as dRAM. The purpose is to

[Summary of the invention]

In the present invention, a first oxide film is deposited by chemical vapor deposition (CVD) on the surface of a silicon layer on which unevenness is formed, and thermal oxidation is performed while covered with this first oxide film. After forming a second oxide film on the surface of the silicon layer under the first oxide film, the first and second oxide films are removed by etching, and a third oxide film is formed on the exposed silicon layer surface by thermal oxidation.
oxide film is formed.

〔Effect of the invention〕

According to the present invention, by performing thermal oxidation in the presence of a CVD oxide film, it is possible to effectively round corners with a small radius of curvature of the irregularities on the surface of the silicon layer formed by anisotropic dry etching. can. As a result, the thickness of the thermal oxide film formed subsequently is suppressed from decreasing at the corners.

Therefore, according to the present invention, it is possible to form a thermally oxidized film with a uniform thickness and excellent insulating properties on the surface of a silicon layer having unevenness, and at the same time, it is possible to alleviate electric field concentration at a part of the corner. It is possible to improve the reliability of a highly integrated dRAM having a sunken capacitor.

[Embodiments of the invention]

The present invention will be explained in detail below.

Figures 1(a) to (9) show dR with grooved capacitors.
FIG. 3 is a cross-sectional view showing the manufacturing process of an example applied to AM.

As shown in Figure 1(a), for example, the specific resistance is 5 to 50Ω.
After preparing a CRS p-type (100) silicon substrate 1 and forming a field insulating film 2, a CVD oxide film 3 with a thickness of about 0.8 μm is deposited on the entire surface. form a window. Next, Figure 1(b)
As shown in FIG. 3, reactive ion etching (RIE) is performed on the CVDI compound 11 to form a groove 4 having a depth of about 2 μm and having vertical walls. Thereafter, the oxide lI3 is removed, and an oxide film (first oxide film) 5 is deposited again by CVD as shown in FIG. 1(C). This CVD oxide film 5 preferably has a thickness of 200 Å or more. Then, thermal oxidation is performed in the state where this CVD oxide M5 is deposited, and thermal oxidation Ml (second oxide film) 6 is formed on the surface of the silicon substrate 1 under the CVD oxide film 5, as shown in FIG. 1(d). Form.

The thermal oxide film 6 preferably has a thickness of 100 Å or more.

FIG. 2 (a>, (b) shows the silicon substrate 1 formed by the above steps.
This is an enlarged view of how roundness is formed at the corners A and B of the uneven portion. At the concave corner A, the oxidation rate decreases due to stress concentration during thermal oxidation, and as a result, the interface between the formed thermal oxide film 6 and the silicon substrate 1 becomes rounded as shown in FIG. 2(a). On the other hand, stress concentration similarly occurs at the convex corner B, but since the amount of oxygen diffused through the CVDl1I film 5 and supplied to the silicon substrate in this part is larger than that in the flat part, the effect of lowering the oxidation rate is compensated for. Ru.

Therefore, at this corner B, the thermal oxide film 6 becomes thicker, as shown in FIG. 2(b), and is effectively rounded. When the CvDrli film 5 is set to a thickness of 200 Å or more and thermal oxidation is performed so that about 100 or more thermally oxidized m6 are formed on the flat part, corner A is formed.

Both B are rounded with a radius of curvature of 50 Å or more.

Thereafter, as shown in FIG. 1(e), the CVD oxide film 5 and the thermal oxide film 6 are removed by etching. Then, as shown in FIG. 1(f), an n-type layer 9 is formed on the exposed surface of the silicon substrate 1, and thermal oxidation is performed again to form a capacitor insulating film. (Third oxide film) 7 is formed, and then a first layer polycrystalline silicon film is deposited and patterned to form a capacitor electrode 8. Thermal oxide film 7 has a thickness of 50 Å or more5
It is formed with a thickness of 00 Å or less. Next, Figure 1 (
As shown in Q), thermally oxidized jlIO, which will become a gate insulating film, is formed at a position adjacent to the capacitor region, and the gate electrode 1 is formed by depositing and patterning a second layer polycrystalline silicon film.
A switching MOS transistor is formed by forming n+ type layers 12 and 13 which become a source and a drain by, for example, As ion implantation. After this, although not shown, a CVD III film is deposited on the entire surface, contact holes are opened, and λ wiring is formed to complete the dRAM.

According to this embodiment, the corners of the capacitor groove formed by RIE can be effectively rounded, and thinning of the thermal oxide film, which becomes the capacitor insulating film, at a part of the corner can be prevented. Further, by rounding a portion of the corner, electric field concentration can be alleviated. Therefore, according to this embodiment, a highly reliable and highly integrated JRAM can be obtained.

The present invention is not limited to the above embodiments.

For example, although the trench-type dRAM has been described above, the present invention is applicable not only to dRAM but also to any device that requires a step of forming a thermal oxide film on a silicon surface having unevenness.

[Brief explanation of drawings]

FIGS. 1(a) to (Q) are cross-sectional views showing the manufacturing process of an embodiment in which the present invention is applied to dRAMl, and FIGS. 2(a) to (Q) are
b) is an enlarged sectional view of corners A and B in FIG. 1(d), respectively. 1... Silicon substrate, 2... Field insulating film, 3
...CVD oxide film, 4...groove, 5...CVDll
1-oxide film (first oxide layer), 6... thermal oxide film (second oxide film), 7... thermal oxide film (third oxide film, capacitor insulating film), 8... capacitor Electrode, 9... n-type layer, 10... thermal oxide film (gate insulating film), 11...
Gate electrode, 12.13...n+ type layer. Applicant's agent Patent attorney Takehiko Suzue Figure 1 ＾ −
−ζ phrase, O hehe ^^ υ in νν

Claims (5)

[Claims] (1) A step of depositing a first oxide film on the surface of the silicon layer having irregularities by chemical vapor deposition; It is characterized by comprising a step of forming a second oxide film, and a step of forming a third oxide film by thermal oxidation on the surface of the silicon layer exposed by etching away the first and second oxide films. A method for manufacturing a semiconductor device. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the unevenness on the surface of the silicon layer is formed by an anisotropic dry etching method. (3) The recess on the surface of the silicon layer is a dynamic RAM.
a groove formed in the capacitor region of the cell;
Claim 1, wherein the oxide film is a capacitor insulating film.
A method for manufacturing a semiconductor device according to section 1. (4) Manufacturing a semiconductor device according to claim 1, wherein the first oxide film is formed to have a thickness of 200 Å or more, and the second oxide film is formed to have a thickness of 100 Å or more. Method. (5) The method of manufacturing a semiconductor device according to claim 1, wherein the third oxide film is formed to have a thickness of 50 Å or more and 500 Å or less.