JPS62219659A - Mos type semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain capacitance, storage capacitance thereof is remarkably larger than conventional devices, though an area is equal to a conventional superposition type capacitor-cell by using the three layer film, etc. of tantalum pentoxide, silicon dioxide and silicon nitride as an insulating film for storage capacitance. CONSTITUTION:The three layer film of Ta2O5 13, SiO2 14 and Si3N4 12 or the two layer film of Ta2O5 and Si3N4 is used or the combination of the two layer film of SiO2 and Si3N4 and either one of said multilayer films is employed as an insulating film for storage capacity. The Si3N4 film 12 is deposited on the whole surface of polycrystalline silicon 8 processed to an electrode shape, the Ta2O5 film 13 is deposited on the film 12, the Si3N4 film 12 is oxidized directly by oxygen passing in the Ta2O5 film 13 through oxidation treatment under the state, and the SiO2 film 14 is formed on the interface, thus shaping the three-layer insulating film structure of Ta2O5/SiO2/Si3N4. The two-layer insulating film structure of SiO2/Si3N4 can be formed at a position where the Ta2O5 film 13 is difficult to be coated because the film 13 is made approximately perpendicular to a substrate as the processed end of polycrystalline silicon 8 at that time.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a MOS type semiconductor memory device, and particularly to a MOS type semiconductor memory device that can obtain a sufficient storage capacity for operation even in minute elements. It is.

[Conventional technology]

MO5 type semiconductor memory devices, especially dRAM (dynamic random access memory), have achieved a fourfold improvement in integration density in three years, and the mainstream has already shifted from 64K to 256, and mass production of IM is just around the corner. It is in. This high degree of integration has been achieved by miniaturizing element dimensions, which is called the so-called scaling law.

However, in recent years, due to the decrease in storage capacity due to miniaturization, S
Adverse effects such as a decrease in the /N ratio and signal inversion due to the incidence of alpha rays have become apparent.

For this reason, memory cells with various structures have been proposed for the purpose of increasing storage capacity. One example is a trench capacitor, which uses the sidewalls of a trench dug perpendicular to the substrate. Since the capacitance of this trench capacitor is determined by the depth of the trench, a large capacitance can be obtained in a very small area.

However, this method has problems such as leakage current between adjacent grooves.

For the trench capacitor described above, attempts have been made to increase the effective capacitor area by stacking the capacitor part on a thick oxide film for word lines and element isolation (for example, IE , International, Electron, Device, Meeting, Technical Digest, IEEE Int, Electro
n DevjcesMeeting, Tech.

Dig, p348-351. Dec (1978)
Koyanagi in.

Sunami, Hashimoto and Ashik
“Novel high density” by awa etc.
y, 5tacked CapacitorMOSRA
(described in M).

FIG. 2 is a cross-sectional view of a dRAM having a conventional stacked capacitor as described above.

The structure will be explained below.

In Figure 2, a MOS transistor (switching transistor) consisting of a drain 5 connected to a bit line, a gate electrode 4 connected to a word line, and a source 6 serving as one electrode of a capacitor is connected to a thick oxide film for isolation between elements. It is formed in an area surrounded by membrane 2.

Further, polycrystalline silicon 8 is formed so as to be in contact with the source 6 and partially on top of the gate electrode 4 and the element isolation oxide film 2, and an insulating film 9 is formed on the surface of this polycrystalline silicon 8. . Therefore, compared to a planar capacitor in which an insulating film is formed only on the substrate surface portion of the source 6, the area can be increased.

In FIG. 2, 1 is a semiconductor substrate, 3 is a gate oxide film, 7 is an oxide film for interlayer isolation, 10 is the other electrode of the capacitor at the power supply potential, 11 is an interlayer isolation film, 15 is a word line, and 16 is an interlayer isolation film. indicates a bit line, and 17 indicates a power supply potential.

[Problem that the invention seeks to solve]

In the conventional stacked capacitor cell as described above,
As an insulating film for a capacitor, a silicon dioxide film (S
iOt) and deposited silicon nitride film (S13N4
) or a double-layer film thereof. Therefore, compared to conventional planar capacitors, the increase in capacitance is only due to the increase in area, and when the cell area is made even smaller, it becomes impossible to secure sufficient storage capacity. Ta.

An object of the present invention is to provide a MOS type semiconductor memory device which is equivalent in area to a conventional stacked capacitor cell but has a much larger storage capacity than the conventional stacked capacitor cell; The object of the present invention is to provide a MOS type semiconductor memory device that has a smaller area than a capacitor cell but has the same storage capacity as a conventional device.

[Means for solving problems]

The above object can be solved by using an insulating material having a larger dielectric constant than silicon dioxide or silicon nitride as the insulating film of the capacitor. For example, tantalum pentoxide ('razos) has a relative dielectric constant of 20 to 25, and compared to Sj, O, if the capacitor area is the same, it can be expected that the capacitance will increase by about 5 times, and in order to achieve the same capacitance, In this case, the area of the capacitor only needs to be 115.

However, various problems arise when trying to apply Ta2o to conventional stacked capacitors. For example, as shown in Figure 2 above, in a stacked capacitor cell, polycrystalline silicon is used as one of the capacitor electrodes, so the unevenness of the polycrystalline silicon surface causes electric field concentration, which reduces the breakdown voltage and long-term This is a factor that reduces the reliability of the information. In particular, when depositing a Ta2O film by a physical vapor deposition method such as a sputtering method, the unevenness of the underlying layer has a large effect.

As one means to solve this problem, extended, abstract, of, electrochemical,
Society, Spring, Meeting, p190-
191, Abstract No. 125° (1984)
(Extended Abstract of El
electrochemical Society, Spr.
N15hioka at ing Meeting).

“Dielect” by Kimura, Mukai, etc.
ricCharacter-istic of a
very thin Ta2O, MIS capaci
As discussed in the paper entitled ``tor'',
It is conceivable to use a method of adding oxidation treatment to the TaZOs/Si two-layer structure and growing a SiO□ film at the interface.

In this method, oxygen diffuses through the Ta, O, and films and reacts with Si at the interface to form an oxide film. Moreover, since oxygen diffuses through the particularly thin part of the Ta2O film,
It becomes possible to repair defects such as pinholes.

However, even if this method is used, electric field concentration points reflecting the unevenness of polycrystalline silicon remain at the interface between Sio and Si.

Therefore, in the present invention, as shown in FIG. 1, a Si, N4 film 12 is deposited on the entire surface of polycrystalline silicon 8 processed into an electrode shape, and a Ta, O, film 13 is deposited on this.
In this state, oxidation treatment is performed to remove Ta and O.

The Si, N4 film 12 was directly oxidized by the oxygen passing through the film 13, and a Si, 114 was formed at the interface. By this, T a, Os / S i Oz / S
A three-layer insulating film structure of IA N4 was formed.

Note that in areas where it is difficult for Ta, O, and the film 13 to adhere because they are almost perpendicular to the substrate, such as the processed edges of polycrystalline silicon, a two-layer insulating film of SiO2/SiaN* is used. A structure is created.

[Effect]

1/- When depositing the Si, N4 film 12 on the surface of the polycrystalline silicon 8, generally known low pressure CVD (Chemical
Vapor Deposition) method is used.

This method uses SiH4 and NH3 in an atmosphere below atmospheric pressure.
By introducing gas and thermally decomposing it, Si
This is a method of forming a 3N4 film.

Since this method uses low pressure, it is superior to physical vapor deposition methods in terms of coverage and the like. Therefore, when deposited on a substrate with unevenness, the unevenness is alleviated, and electric field concentration when voltage is applied is suppressed. Such an effect cannot be expected when polycrystalline silicon is directly oxidized.

In addition, the step coverage of the Si3N4 film formed by low-pressure CVD is very good, so it looks like the processed edge.
It is also possible to deposit the film almost uniformly on the side walls perpendicular to the substrate.

Next, on top of the above 5L3N and film 12, Ta20=film 1
3 to form a two-layer film. At this time, the coverage of the processed edge is affected. Although this two-layer film structure has sufficient characteristics as a capantor insulating film, it
A single layer film of N4 does not necessarily have sufficient breakdown voltage etc. due to Si, N, and latent defects such as pinholes existing in the film.

Therefore, by further adding oxidation treatment to the above structure, Si,
If an oxide film 14 is formed on the surface of the N film, pinholes etc. will be closed and the withstand voltage will be improved.

Even in the double layer film of Ta2O, and Si, N4, Ta,0
The oxygen diffused into the film oxidizes only the very surface of the underlying Si and N, which has a great effect on reducing pinholes in the Si and N.

Thus, T a, Os / S i Oz /
Three-layer insulation film structure of S is N 4 and S 102 /
By coexisting the two-layer insulating film structure with the S la N 4 film, a charge storage capacitor with large capacity and excellent long-term reliability can be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. Third
The figure is a process diagram for implementing the present invention, and (a) to (f) in FIG. 3 show cross-sectional views in each process.

In FIG. 3, (a) is a cross-sectional view of a MoS transistor manufactured by a conventional known method.

The parts indicated by the numbers are the same as those shown in FIG.

Polycrystalline silicon 8, which will become one electrode of the capacitor, is deposited thereon as shown in FIG. 3B, and impurities are introduced by phosphorus diffusion, ion implantation, etc. to make it the same conductivity type as the source 6. Thereafter, using a known photolithography method or dry etching method, only necessary portions are left and the rest are removed. The film thickness is, for example, 250 nm.

A 513N4 film 12 is deposited thereon to a thickness of about 15 nm, as shown in FIG. 3C, using a known low pressure CVD method.

Since the low-pressure CVD method has good step coverage, it is possible to deposit the same film thickness even on parts perpendicular to the substrate, such as the processed edges.

On top of this, Ta, O, and a film 13 are deposited as shown in (d). The Ta, Os film can be formed by various methods, but reactive sputtering is suitable from the viewpoint of stoichiometric composition and film density.

In this example, a reactive sputtering method was used in which a 99.99% tantalum plate was used as a target and sputtering was performed in a mixed gas of argon and oxygen. The film thickness is 20 nm or less.

Note that 1. physical vapor deposition methods such as reactive sputtering have poor step coverage;
,O, The film may not stick.

Next, when oxidation treatment is applied to the state shown in (d),
At the exposed portions of the Si, N4 film 12, the Si, N4 film is oxidized as it is, and an Sio2 film 14 of several nm thick is formed on the surface. Even in the portion covered by the Ta, O, film 13, oxygen easily diffuses through the Ta, Os film, so the oxygen reacts with the Si, N, and film to form a Sun film (e).

In this example, a high-pressure oxidation method at 900° C. and 7 atmospheres was used.

In this way, Ta, Os/5
Three-layer insulation film of io2/Si3N4 and S io2/S
A two-layer insulating film of 13 N 4 is formed. In this embodiment, a structure in which a three-layer insulating film and a two-layer insulating film coexist has been described. However, if the coverage of the Ta2O film is good, a three-layer insulating film is formed over the entire surface of the capacitor.

Finally, as shown in (f), the other electrode 10 of the capacitor
Deposit the necessary parts and remove the others.

At the same time, the insulating film on the contact hole connected to the wiring is also removed. In this way, the capacitor section is completed.

Next, FIG. 4 is a layout diagram of a MOS semiconductor memory device of the present invention.

In FIG. 4, 2 is a thick insulating film for isolation between elements, 15
is a word line, and 8 is one electrode of a capacitor connected to the drain of a MOS transistor.

Reference numeral 10 designates the other electrode of the capacitor, which covers the entire surface except for a contact hole 11 area to which a bit line is connected.

Note that the bit lines are omitted in FIG. 4 to avoid complication.

Further, in this embodiment, a folded bit line configuration is used to reduce noise in circuit operation, but an open bit line configuration is also possible.

Next, FIG. 5 is a sectional view of another embodiment of the present invention.

In the embodiment shown in FIG. 1, in order to simplify the explanation, the simplest structure of the switching MOS transistor was explained as an example.

That is, in the above structure, the impurity concentration in the source/drain regions is approximately constant in the lateral direction on the substrate.

When the effective channel length of the gate is 2#l1 or more, even a simple source/drain structure as described above poses no problem in terms of operation or reliability. However, as the gate length becomes shorter, electric field concentration at the drain end becomes more pronounced, and characteristic fluctuations due to injection of hot carriers become a major problem.

One method proposed to solve the above problem is the LDD (LightlyDop) shown in Figure 5.
ed Drain) structure.

This structure is designed to alleviate electric field concentration by forming a low concentration impurity layer at the source/drain ends. In FIG. 5, 5' indicates the drain of the LDD structure, and 6' indicates the source of the LDD structure.

As shown in FIG. 5, the above-described LDD structure transistor can also be used in the semiconductor memory device of the present invention.

In the LDD structure, it is necessary to suppress changes in the LDD profile due to heat treatment, so a process that involves high-temperature heat treatment after forming the LDD is not preferred.

On the other hand, in the present invention, there is no heat treatment process that affects the profile.For example, polycrystalline silicon 8
CVD at about 700°C is used to form the film 12.
method has been used, and Ta, O.

Since the film 13 is formed by sputtering, it can be deposited at room temperature. Furthermore, the oxidation process after the Ta, O, and film formation is also 10
A high-pressure oxidation method at temperatures below 00°C is used.

As described above, the present invention can be applied even when an LDD structure transistor, which requires strict control of the source/drain impurity concentration profile, is used as a switching transistor.

〔Effect of the invention〕

According to the present invention, not only can the area be significantly reduced compared to conventional capacitors to obtain the same capacity, but it also has excellent breakdown voltage and long-term reliability.
It becomes possible to fabricate minute memory cells, which has an excellent effect on increasing the integration of MOS type semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an embodiment of a MOS semiconductor memory device having stacked capacitor cells according to the present invention;
The figure shows a MOS with conventional stacked capacitor cells.
FIG. 2 is a cross-sectional view of a type semiconductor memory device. FIG. 3 is a process diagram for manufacturing a MOS type semiconductor memory device according to the present invention, FIG. 4 is an example of the layout of a MOS type semiconductor memory device according to the present invention, and FIG. 5 is a diagram showing another embodiment of the present invention. FIG. 3 is an example cross-sectional view. Explanation of symbols> 1... Semiconductor substrate 2... Oxide film for element isolation 3... Gate oxide film 4... Gate electrode 5.
...Drain 5'...Drain 6 of LDD structure...Source 6'...Source 7 of LDD structure...Interlayer isolation film 8...Polycrystalline silicon 9
...Capacitor oxide film 10...Other electrode of the capacitor 11...Interlayer isolation film 12...Si, N4 film 13...Ta, O, film 14...Sio2
Film 15...word line 16...bit line 1
7...Power supply potential

Claims (1)

[Claims] 1. A MOS transistor formed from a drain region connected to a bit line, a gate electrode connected to a word line, and a source region serving as one electrode of a storage capacitor;
A conductor layer in contact with the source region and having the same conductivity type as the source region is used as one electrode, a conductor layer connected to the power supply voltage is used as the other electrode, A storage capacitor formed from an insulating film sandwiched between
In a MOS type semiconductor memory device configured by
As the insulating film of the storage capacitor, a three-layer film of tantalum pentoxide, silicon dioxide, and silicon nitride, a two-layer film of tantalum pentoxide and silicon nitride, or a two-layer film of silicon dioxide, silicon nitride, and the above-mentioned A MOS type semiconductor memory device characterized by using a combination with either one of multilayer films. 2. The MOS semiconductor according to claim 1, wherein a film formed by directly oxidizing the silicon nitride surface is used as silicon dioxide in the two-layer film of silicon dioxide and silicon nitride. Storage device. 3. As silicon dioxide in the three-layer film of tantalum pentoxide, silicon dioxide, and silicon nitride, a film formed as a result of direct oxidation of the silicon nitride surface by oxidizing species diffused into the tantalum pentoxide film. A MOS type semiconductor memory device according to claim 1, wherein the MOS type semiconductor memory device is used.