JPH0196949A - Semiconductor device - Google Patents

Abstract

PURPOSE:To open a contact hole on a substantially flat surface, and to improve the reliability of conduction by forming a storage capacity and a base intermediate layer of another layers, and forming the intermediate layer not only on a valley region formed between word lines but in a shape extended to the above of the capacity in which its base becomes relatively flat. CONSTITUTION:Thick oxide film regions 1, 2 for electrically isolating between elements are formed on first conductivity type semiconductor substrates 1, 1, and word electrodes 1, 3 are formed. Then, a second conductivity type diffused layer is formed in the substrate. Then, a storage capacities 1, 5 are formed, but not formed in bit line contacts. After capacitor insulating films 1, 6 and plate electrodes 1, 7 are formed, intermediate layers 1, 9 are formed. The intermediate layers are extended to the above of one storage capacity. Further, BPSG or the like having high fluidity are employed as interlayer insulating films 1, 10, and the contact of the bit line can be opened on a substantially flat surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which contact from a wiring layer to a fine source/drain region can be easily and reliably established.

[Conventional technology]

In recent years, with the miniaturization of semiconductor devices, DRAM (DRAM)
dynamic Random Access Memo
In integrated circuits with high integration density such as RY), when electrically connecting one diffusion layer and a bit line, an intermediate layer is provided between the two to prevent contact holes from opening directly into the substrate. There is. This method was developed in Japanese Patent Application Laid-Open No. 60-2313.
Discussed in 57.

FIG. 2 shows this structure. First, I will outline the process for realizing Honseizo.

A thick oxide film (2, 2) for isolating each element and a gate electrode (2, 1) are formed on the semiconductor substrate (2, 1) of the first conductivity type.
, 3) and 24th electrode type diffusion layers (2, 4) are formed. In FIG. 2, the gate electrode structure has a well-known LDD (L
A single drain structure is used, but a single drain structure is also used.

After exposing the diffusion layer (2, 4) between the word lines, the polycrystalline silicon (2, 5) (2, 8) is coated by a known CVD process.
(Chemical Vapor Depositio
n) deposited by method. Of this polycrystalline silicon, (2
, 5) has an insulating film (2) for charge storage capacitor on its surface.
, 6), plate electrodes (2, 7) are formed to form a capacitor. One polycrystalline silicon (2, 8) serves as a base for opening a contact hole for a bit line (2, 10). By providing the intermediate layer as a base for the contact holes in this manner, it is no longer necessary to directly open contact holes in the diffusion layer between the word lines, and it is possible to greatly reduce the distance between the word lines.

This has the advantage that the memory cell area can be reduced.

Furthermore, since the storage capacitor portion and the silicon for the intermediate layer of the contact can be formed in the same layer, there is also a feature that the number of manufacturing steps for the memory cell is reduced.

Note that in FIG. 2, (2, 9) is an interlayer insulating film.

[Problem that the invention seeks to solve]

However, in the structure shown in Fig. 2, the plate electrodes (2,
In order to prevent the layer 7) from coming into contact with the intermediate layer polycrystalline silicon (2, 8), a large margin must be designed in advance. For this reason, the storage capacitor section (2, 5
) is limited, and as the memory cells are reduced, the storage capacity decreases significantly. In addition, interlayer insulating film (2, 9)
B P S G (Borophosph)
Even if it is reflowed using a material such as AQ or silicide, the contact hole must be opened in the valley formed between the word lines, and a material with poor sidewall coverage such as AQ or silicide is used as the bit line. In this case, there was a problem in ensuring the reliability of the bit line contact.

An object of the present invention is to provide a semiconductor device that fundamentally solves the above objects.

[Means for solving problems]

The disadvantage of the structure shown in FIG. 2 is that the storage capacitor section (2, 5) and the underlying intermediate layer (2, 8) are the same layer.

For this reason, the plate electrodes (2, 7) and the underlying intermediate layer (2
, 8) must be provided with a margin for mask alignment.

This drawback is caused by the storage capacitance section (2, 5) and the underlying intermediate layer (2, 5).
8) are formed in separate layers, and the intermediate layer is shaped so that it extends not only into the valley area between the word lines, but also over the storage capacitor part, where the underlying layer is relatively flat. Solvable.

[Effect]

FIG. 1 shows the structure of the present invention. First, a thick oxide film region (1, 2) is formed on the surface (1, 1) of a semiconductor substrate of a first conductivity type to electrically isolate each element, thereby forming a word electrode (1, 3). Next, a second conductivity type diffusion layer is formed in the semiconductor substrate, but the structure up to this point is the same as the conventional structure shown in FIG. Next, the storage capacitor section (1, 5) is formed, but at this time, it is made so that it cannot be formed in part of the bit line contact i. Then, after forming the capacitor insulating film (1, 6) and the plate electrode (1, 7), the intermediate layer (1, 7) is formed.
9). As shown in Figure 1, this middle layer is
Make it extend to the top of one &i TA capacitor section. Furthermore, highly fluid nPSG etc. are used as an interlayer film (
1, 10), the bit line contact becomes
It becomes possible to open the opening on a flat surface.

As described above, by using the structure of the present invention, the reliability of contact conduction is significantly improved. Furthermore, since there is no need for alignment allowance between the plate electrodes (1, 7) and the bit line contact area, a secondary effect is that the storage capacitance can be increased compared to the conventional structure when comparing the same cell area. be.

[Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 3(,) to (g). First, as shown in FIG. 3(A), an oxide film (3, 2) for electrically separating each element is formed on the surface of a first conductivity type semiconductor substrate (3, 1) to a thickness of about 550 nm. It is grown using a known thermal oxidation method. After growing a gate oxide film (3, 3) with a thickness of about 20 nm, a gate electrode (3, 3) is grown.
, 4) is made of a material such as polycrystalline silicon containing impurities or a two-layer film of polycrystalline silicon and silicide, and patterned. By ion-implanting impurities such as arsenic while using this gate electrode as a mask, the first
A second conductivity type diffusion layer (3, 5
) to form. In FIG. 3(a), the known ■, D D
(Lightly Doped Drain) structure is used as an example, but there is no difference in a so-called single drain structure.

Next, as shown in FIG. 3(b), an oxide film (3
, 6) are deposited, and only the portion where the storage capacitance portion contacts the diffusion layer in the substrate is opened using a known photolithography method and dry etching method.

Note that this oxide film is formed using CVD (Chemical
It is deposited using a vapor deposition method.

Next, as shown in FIG. 3(c), a conductor layer (3, 7) is formed, which becomes one electrode of the storage capacitor and contacts the diffusion layer in the substrate.
form. This conductor layer is generally made of polycrystalline silicon formed by CVD. In order to make this polycrystalline silicon the same conductivity type as the diffusion layer in the substrate, phosphorus ions are implanted or phosphorus is diffused from the surface.The phosphorus that diffuses within the polycrystalline silicon has no effect on the characteristics of the transistor. As long as the impurity does not have any adverse effect, either of the above methods may be used to introduce the impurity. In addition, Section 3.2
The oxide film remaining in areas other than the openings in the figure serves as a base for patterning the 9 g stacked amount using a dry etching method, and prevents the substrate from being scraped.

After patterning is completed, capacitor insulating film (3, 8
) to form. The film thickness is 10 nm or less in terms of a 5iOz film. This capacitor insulating film can be made by directly oxidizing polycrystalline silicon, or by adding 5 ia on top of it.
A structure in which a Na film is deposited is desirable from the viewpoint of reliability. Furthermore, a high dielectric constant insulating film such as a Taxes film can also be used.

Next, as shown in FIG. 3(d), the plate electrodes (3, 9)
Polycrystalline silicon containing impurities is deposited, and only the portion where the bit line makes electrical contact with the substrate is opened. At this time, in order to utilize the structure of the present invention most effectively, the following steps were used. First, the plate electrodes (3, 9) are not processed in a single layer, but as shown in Figure 3.4, an oxide film (3, 10) is formed on them.
is deposited and the two layers are processed simultaneously. This oxide film (3,
10) is formed using the CVD method.

Next, an oxide film is deposited again on the entire surface of the shape shown in FIG.
), the oxide film remains to cover the sidewalls of the plate electrodes, and the plate electrodes are insulated (FIG. 3(e)).

At this time, the diffusion layer region sandwiched between the word lines is exposed.

If such a method is not used, after processing the plate electrode,
Part of the effect of the present invention is that a mask is required to cover the oxide film again and expose the diffusion layer of the substrate, and there is no need for a margin for alignment between the plate electrodes (3, 9) and the contact holes. I can't take advantage of it.

Next, as shown in FIG. 3(f), an intermediate layer (3, 1
2) into form 1. As is clear from Figure 3(f),
Since deep valleys are formed between word lines, polycrystalline silicon is used in this embodiment to cover these valleys with good coverage.

As a method for introducing impurities into polycrystalline silicon, ion implantation or diffusion may be used as long as it does not affect transistor characteristics.

However, the resistance is too high to use this polycrystalline silicon as it is as a wiring layer.

Therefore, as shown in Fig. 3(g), an interlayer film (3, 1
3) and bit lines (3, 14) and intermediate 1 (3
, 12), and
Thereafter, wiring to become the bit lines (3, 14) is formed, and AQ, silicide, or the like having low resistance is used as the wiring. At this time, by using an interlayer film such as BPSG that exhibits high fluidity under high temperatures, the deep valley created by the intermediate layer (3, 12) and the word line is almost completely filled with this interlayer film, and the bit line (3, 14) can be formed on a substantially flat surface.

FIG. 4 shows a plan layout of a memory cell using the structure of the present invention. (4, 1) is a pattern surrounding the active region of the transistor, and a thick oxide film for isolation between elements is formed around this pattern. (4,2) is a word line. The ltM capacitance part of (4, 4) is (4,
3) is in contact with the substrate through the opening. Plate electrodes (4, 5) are provided to cover this storage capacitor section, and only a portion thereof is open. Through this opening, the intermediate layer (4,
, 6) are in contact with the substrate, contact holes (4, 7) are opened thereon, and bit lines (4, 8) are connected to the intermediate layer. In this way, the intermediate layer is formed on one storage capacitor section or word line.

As described above, in this embodiment, in order to most effectively explain the structure of the present invention, a so-called stacked capacitive cell is used.
A RAM cell was used. However, it goes without saying that the present invention is not limited to DRAM cells and can also be applied to ordinary transistor structures. Unlike the structure, the contact hole can be opened on a substantially flat surface, so even if a material with poor sidewall coverage is used as the wiring, the reliability of the groove path is significantly improved.

Furthermore, by applying the present invention to DRAM, there is no need for alignment margin between the plate electrode and the contact hole.
In some cases, it is said to be effective in increasing f&d.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a stacked capacitance type D RΔM cell to which the present invention is applied, FIG. 2 is a cross-sectional view of a conventional structure, and FIGS.
g) is a process diagram showing an embodiment of the present invention, and FIG. 4 is a plan layout diagram of a stacked capacitance type DRAM cell to which the present invention is applied. 1.1... First conductivity type semiconductor substrate, ]1.2... Oxide film for isolation between elements, 1.3... Word line, 1.4...
・Second conductivity type diffusion layer, 1.5...Storage capacitor section, 1.6
... Capacitor insulating film, 1.7... Plate electrode,
1.8... Interlayer insulating film, 1.9... Intermediate layer, l 1
0...Interlayer insulating film, 1.11...Bit line, 2.1
...First conductivity type semiconductor substrate, 2.2... Oxide film for element isolation, 2.3... Word line, 2.4... Second conductivity type diffusion layer, 2.5...・Storage capacitor part, 2.6... Capacitor insulating film, 2.7... Plate electrode, 2.8.
... intermediate layer, 2.9 ... interlayer film, 2.10 ... bit line, 3.1 ... first conductivity type semiconductor substrate, 3.2 ...
- Inter-element isolation oxide film, 3.3... Gate oxide film, 3.
4... Word line, 3.5... Second conductivity type diffusion layer, 3
．． 6... Base oxide film, 3.7... Storage capacitance section, 3.
8...Capacitor insulating film. 3.9... Plate electrode, 3.10... Interlayer film, 3
．． 11...Side wall oxide film, 3.12...Intermediate layer, 3.
13... Interlayer film, 3.14... Bit line, 4.1.
... Transistor active area, 4.2... Word line, 4.3... Opening to substrate, 4.4... Storage capacitor, 4.5... Plate electrode opening, 4.6 ...Intermediate layer, 4.7...Contact hole, 4.8...Bit line.

Claims (1)

[Claims] 1. A source and drain region of a second conductivity type formed in a semiconductor substrate of a first conductivity type, and a current flowing between the source and drain formed in the semiconductor substrate of the first conductivity type. In a semiconductor device controlled by a gate electrode through a film, and in which electrical connection to at least one of the wiring layer and the source/drain is made through an intermediate layer of a second conductivity type. . A semiconductor device, wherein a contact to the intermediate layer is opened at a position partially or completely away from the source and drain regions in a plan view of the semiconductor device.