JP2002033381A - Formation method of element isolation insulating film and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an element isolation insulating film that forms the shoulder part of a silicon substrate into a round shape, and at the same time, can thin the thickness of the inner-wall oxide film of a trench. SOLUTION: With a silicon nitride film 3 as an etching mask, a silicon substrate 1 is etched from the upper surface by a specific depth (for example, 300 nm) through anisotropic dry etching method with a high etching rate in the depth direction of the silicon substrate 1, thus forming a trench 5 in the upper surface of the silicon substrate 1. Then, in a known plasma-oxidizing device, a silicon oxide film 6 with a film thickness of approximately 15 nm is formed on the inner wall of the trench 5 by the plasma oxidation method, using an oxidizing gas with high concentration, such as an oxygen gas.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation insulating film for isolating adjacent semiconductor elements.

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memory)
In semiconductor devices such as ry), it is required to improve the isolation performance of the element isolation insulating film and to reduce the isolation width. 10 to 17 are sectional views showing a conventional method for manufacturing a semiconductor device in the order of steps. First, CVD (Chemic
al Vapor Deposition) method, etc.
A silicon oxide film 102 and a silicon nitride film 103 are formed in this order on the upper surface of FIG. Next, a photoresist 104 having a pattern in which the upper part of the region where the element isolation insulating film 108 is to be formed is opened is formed on the silicon nitride film 103 by photolithography (FIG. 11).

Then, using a photoresist 104 as an etching mask, the silicon nitride film 103 and the silicon oxide film 102 are etched in this order by an anisotropic dry etching method having a high etching rate in the depth direction of the silicon substrate 101. Then, the upper surface of the silicon substrate 101 is exposed. After that, the photoresist 104 is removed (FIG. 12). Next, using the silicon nitride film 103 as an etching mask, the silicon substrate 101 is etched from the upper surface thereof to a predetermined depth by an anisotropic dry etching method having a high etching rate in the depth direction of the silicon substrate 101. Thus, a trench 105 is formed in the upper surface of the silicon substrate 101 (FIG. 13).

Next, a silicon oxide film 106 is formed by thermally oxidizing the inner wall of the trench 105 (FIG. 1).
4). Thereby, the damage caused in the silicon substrate 101 by the anisotropic dry etching for forming the trench 105 can be taken into the silicon oxide film 106. Next, HDP (High Density Plasm
a) A silicon oxide film 107 is formed on the entire surface by -CVD so as to fill the trench 105 (FIG. 1).
5).

Next, CMP (Chemical Mechanical Poli)
The silicon oxide film 107 is removed by a shing) method. This CMP process stops when the upper surface of the silicon nitride film 103 is exposed. Next, the silicon nitride film 103
And the underlying silicon oxide film 102 are removed by wet etching. Next, a portion of the silicon oxide film 107 located above the upper surface of the silicon substrate 101 is removed by wet etching using hydrofluoric acid.
A predetermined thickness is removed from the upper surface (FIG. 16). Figure 1
In the example shown in FIG. 6, the upper surface of the silicon oxide film 107 after the wet etching is slightly higher than the upper surface of the silicon substrate 101. Through the above steps, the element isolation insulating film 108 including the silicon oxide films 106 and 107 can be formed.

Next, a gate oxide film 109 is formed on the upper surface of the silicon substrate 101 in an element formation region defined by the element isolation insulating film 108 by a thermal oxidation method. Next, a gate electrode 110 is formed by forming a polysilicon film on the entire surface by a CVD method or the like and patterning the polysilicon film by a photoengraving method (FIG. 17). As shown in FIG. 17, the end of the gate electrode 110 is located on the element isolation insulating film 108. After that, the device is completed through processes such as a source / drain region forming process and a wiring process.

Here, the thickness of the silicon oxide film 106 will be described. Referring to FIG. 17, when a voltage is applied to gate electrode 110 and an electric field is concentrated on shoulder portion 200 of silicon substrate 101 below the end of gate electrode 110, dielectric breakdown of gate oxide film 109 occurs near the shoulder. Therefore, the characteristics of the gate oxide film 109 are deteriorated as a whole. In order to suppress this, the shoulder 200 of the silicon substrate 101 needs to be rounded in order to alleviate the electric field concentration. When the silicon oxide film 106 is formed by the thermal oxidation method as in the above-described conventional method of manufacturing a semiconductor device, the shoulder 20 of the silicon substrate 101 is formed.
In order to make 0 a round shape, the thickness of the silicon oxide film 106 needs to be 20 nm or more.

[0008]

As described above, in the conventional method of manufacturing a semiconductor device, since the silicon oxide film 106 is formed by thermally oxidizing the inner wall of the trench 105, the thickness of the silicon oxide film 106 is reduced. As 20
A film thickness of at least nm is required. On the other hand, in order to improve the driving capability of the transistor and increase the integration of the chip,
The isolation width itself of the element isolation insulating film cannot be increased.
For example, in a 256 MDRAM, the separation width is required to be suppressed to about 0.1 μm.

Therefore, when the silicon oxide film 107 is buried in the trench 105 in the HDP-CVD process after the formation of the silicon oxide film 106, the opening width of the trench 105 is reduced due to the formation of the thick silicon oxide film 106. Since the size is reduced, there is a problem that the embedding defect easily occurs. FIG. 18 is a cross-sectional view showing a situation in which such embedding failure has occurred. As shown in FIG. 18, a burying defect 111 occurs at the center of the silicon oxide film 107.

The present invention has been made in order to solve such a problem. In order to alleviate the electric field concentration, the thickness of the oxide film on the inner wall of the trench is reduced while the shoulder portion of the silicon substrate is rounded. To obtain a method for forming an element isolation insulating film capable of suppressing the occurrence of embedding defects by reducing the thickness,
And a method for manufacturing a semiconductor device including the method.

[0011]

Means for Solving the Problems Claim 1 of the present invention
(A) a step of preparing a substrate, (b) a step of selectively forming a recess in a main surface of the substrate, and (c) a recess by plasma oxidation. Forming an oxide film on the inner wall of the substrate, and (d) embedding an insulating film in the concave portion where the oxide film is formed.

According to a second aspect of the present invention, a method for forming an element isolation insulating film according to the first aspect is the method for forming an element isolation insulating film according to the first aspect.
gh Density Plasma) -deposition of an insulating film in a CVD chamber, and step (c) is performed in an HDP-CVD chamber.

According to a third aspect of the present invention, there is provided a method for forming an element isolation insulating film according to the first or second aspect, wherein the step (c) comprises the steps of: The oxidation is performed using a source gas containing an inert gas.

According to a fourth aspect of the present invention, there is provided a method for forming an element isolation insulating film according to the third aspect, wherein the inert gas is Ne, A
The gas is one of r, Kr, and Xe.

According to a fifth aspect of the present invention, there is provided a method for forming an element isolation insulating film according to the third or fourth aspect, wherein the step (c) comprises the step of: Is characterized in that a bias voltage having a polarity opposite to that of the inert gas ions is applied.

According to a sixth aspect of the present invention, a method of manufacturing a semiconductor device includes the method of forming an element isolation insulating film according to any one of the first to fifth aspects.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 1 to 7 are sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. First, a silicon oxide film 2 is formed on the entire upper surface of a silicon substrate 1 by a thermal oxidation method. Next, a silicon nitride film 3 is formed on the entire surface of the silicon oxide film 2 by the CVD method (FIG. 1). The silicon oxide film 2 is formed for the purpose of reducing stress caused by forming the silicon nitride film 3 directly on the silicon substrate 1. Next, a photoresist 4 having a pattern in which an upper portion of a region where the element isolation insulating film 8 is to be formed is opened is formed on the silicon nitride film 3 by photolithography (FIG. 2).

Next, using the photoresist 4 as an etching mask, the silicon nitride film 3 and the silicon oxide film 2 are etched in this order by an anisotropic dry etching method having a high etching rate in the depth direction of the silicon substrate 1. Then, the upper surface of the silicon substrate 1 is exposed. Thereafter, the photoresist 4 is removed (FIG. 3). Next, using the silicon nitride film 3 as an etching mask, the silicon substrate 1 is separated from the upper surface by a predetermined depth (for example, 300 nm) by an anisotropic dry etching method having a high etching rate in the depth direction of the silicon substrate 1 Etch. Thus, a trench 5 is formed in the upper surface of the silicon substrate 1 (FIG. 4).

Next, in a well-known plasma oxidizing apparatus, a film thickness of 1 is formed on the inner wall of the trench 5 by a plasma oxidizing method using a high-concentration oxidizing gas (for example, oxygen gas).
A silicon oxide film 6 of about 5 nm is formed (FIG. 5). Thereby, the damage caused in the silicon substrate 1 by the anisotropic dry etching for forming the trench 5 can be taken into the silicon oxide film 6.

Here, in the oxygen plasma, in addition to negative oxygen ions, highly reactive, chemically active oxygen radicals (O *) are present. Oxygen radicals are electrically neutral, but take away electrons from the silicon substrate 1 on the surface of the silicon substrate 1 (strictly speaking, the surface of an oxide film formed on the silicon substrate). As a result, the oxygen radical becomes negative. Charges.
The silicon substrate 1 is positively charged to generate an electric field. The electric field is concentrated at the shoulder 10 of the silicon substrate 1 defined by the side surface of the trench 5 and the upper surface of the silicon substrate 1, so that oxygen radicals are attracted to the electric field and the shoulder 10 of the silicon substrate 10. Concentrate on a lot.
Therefore, oxidation is promoted more at the shoulder 10 of the silicon substrate 1 than at other portions, and the shoulder 10 of the silicon substrate 1 has a rounded shape.

Next, a silicon oxide film 7 is formed on the entire surface by HDP-CVD so as to fill the trench 5 (FIG. 6). Next, the silicon oxide film 7 is removed by the CMP method. This CMP process stops when the upper surface of the silicon nitride film 3 is exposed. Next, the silicon nitride film 3 and the underlying silicon oxide film 2 are removed by wet etching. Next, by a wet etching method using hydrofluoric acid, a portion of the silicon oxide film 7 located above the upper surface of the silicon substrate 1 is removed by a predetermined thickness from the upper surface (FIG. 7). In the example shown in FIG. 7, the upper surface of the silicon oxide film 7 after the wet etching is slightly higher than the upper surface of the silicon substrate 1. Through the above steps, the element isolation insulating film 8 composed of the silicon oxide films 6 and 7 can be formed.

Thereafter, as in the conventional method of manufacturing a semiconductor device, a gate oxide film is formed on the upper surface of the silicon substrate 1 in the element formation region defined by the element isolation insulating film 8, and then the CVD method and the photoengraving method are performed. A gate electrode is formed on the gate oxide film by the method described above. Then, the device is completed through processes such as a source / drain region forming process and a wiring process.

As described above, according to the method of manufacturing a semiconductor device according to the first embodiment, after forming trench 5 in the upper surface of silicon substrate 1, the inner wall of trench 5 is formed by a plasma oxidation method using oxygen plasma. Then, a silicon oxide film 6 is formed. In the case where the silicon oxide film 106 is formed by a thermal oxidation method as in a conventional method of manufacturing a semiconductor device,
In order to form the shoulder 120 of the silicon substrate 101 into a round shape, the silicon oxide film 1 having a thickness of 20 nm or more is required.
06 had to be formed.

On the other hand, in the method of manufacturing the semiconductor device according to the first embodiment, as described above, the silicon oxide film 6 is formed with a thickness of about 15 nm, thereby forming the shoulder 10 of the silicon substrate 1. Can have a rounded shape. As a result, H after the silicon oxide film 6 is formed
When the silicon oxide film 7 is buried in the trench 5 in the DP-CVD process, the reduction in the opening width of the trench 5 due to the formation of the silicon oxide film 6 can be reduced, so that the occurrence of burying failure can be suppressed. Become.

The plasma oxidation step (FIG. 6) for forming the silicon oxide film 6 and the CVD step (FIG. 7) for forming the silicon oxide film 7 both use high-concentration oxygen plasma. Done. Therefore, the plasma oxidation process for forming the silicon oxide film 6 is performed in the HDP-C
It may be performed in a VD chamber. As a result, it is possible to continuously execute both of the above steps without the process of transporting the wafer between different manufacturing apparatuses,
Manufacturing efficiency can be improved.

Embodiment 2 FIG. FIG. 8 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention. The method of manufacturing a semiconductor device according to the second embodiment is based on the method of manufacturing a semiconductor device according to the first embodiment, and includes a step of forming a silicon oxide film 6 by plasma oxidation shown in FIG. Is obtained by adding Ar gas having the same concentration as that of the oxidizing gas to the raw material gas to be supplied. The plasma generation efficiency is improved by adding a gas having a large mass such as Ar,
The density of the oxygen plasma increases. As a result, the density of oxygen radicals around the silicon substrate 1 to be processed also increases. Other steps of the method of manufacturing the semiconductor device according to the second embodiment are the same as those of the method of manufacturing the semiconductor device according to the first embodiment.

As described above, according to the method of manufacturing a semiconductor device according to the second embodiment, in the step of forming silicon oxide film 6 by plasma oxidation, Ar gas is added to the source gas. Thereby, the density of oxygen radicals in the periphery of silicon substrate 1 is increased and the amount of oxygen radicals concentrated on shoulder 10 of silicon substrate 1 is increased as compared with the first embodiment. As a result, the shoulder 1 of the silicon substrate 1
Since the thickness of the silicon oxide film 6 can be further reduced while maintaining the rounded shape at 0, it is possible to further suppress the occurrence of embedding defects in the subsequent step of forming the silicon oxide film 7. .

In the above description, Ar gas is contained in the source gas.
Although an example in which a gas is added has been described, an inert gas such as He, Ne, Kr, or Xe may be used instead of Ar. However, Ne, Ar, which are heavier than oxygen atoms
By using Kr and Xe, oxygen can be efficiently activated.

Embodiment 3 FIG. 9 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to the third embodiment of the present invention. The method for manufacturing a semiconductor device according to the third embodiment is based on the method for manufacturing a semiconductor device according to the second embodiment, and includes a step of forming a silicon oxide film 6 by plasma oxidation shown in FIG. Are applied with a predetermined substrate bias voltage. Silicon substrate 1
, A substrate bias voltage having a polarity opposite to that of the ions of the inert gas is applied from a power supply 9 connected to the silicon substrate 1. In FIG. 9, since Ar is used as an inert gas, negative argon ions (A
A positive substrate bias voltage having a polarity opposite to that of r ⁻ ) is applied.
Other steps in the method for manufacturing a semiconductor device according to the third embodiment are the same as those in the method for manufacturing a semiconductor device according to the second embodiment.

As described above, according to the method of manufacturing the semiconductor device according to the third embodiment, a predetermined substrate bias voltage is applied to the silicon substrate 1 in the step of forming the silicon oxide film 6. As the inner wall oxidation of the trench 5 progresses, a silicon oxide film 6 grows on the side surface of the trench 5 toward the inside of the trench 5, and the opening width of the trench 5 decreases. However, according to the method of manufacturing a semiconductor device according to the third embodiment, while growing silicon oxide film 6,
Negative argon ions drawn vertically into the silicon substrate 1 by a positive substrate bias voltage cause the trench 5
The silicon oxide film 6 grown on the side surface can be sputtered. That is, the growth of the silicon oxide film 6 on the side surface of the trench 5 can be suppressed by sputtering with argon ions. As a result, the thickness of the silicon oxide film 6 on the side surface of the trench 5 is smaller than in the first and second embodiments, so that the subsequent silicon oxide film 7
In the formation process, the occurrence of defective embedding can be further suppressed.

[0031]

According to the first aspect of the present invention, in the step (c), the oxide film on the inner wall of the concave portion is formed by plasma oxidation. Therefore, the thickness of the oxide film necessary for forming the shoulder portion of the substrate into a rounded shape by the action of oxygen radicals in the plasma can be set to be smaller than that in the case where the oxide film is formed by thermal oxidation. As a result, the reduction in the opening width of the concave portion due to the formation of the oxide film can be reduced, so that in the step (d), the occurrence of defective filling of the insulating film can be suppressed.

According to the second aspect of the present invention, the steps (c) and (d) are performed in the same HDP-CV.
The processing can be continuously performed in the D chamber, and the processing efficiency can be improved.

According to the third aspect of the present invention, the plasma generation efficiency is improved and the density of oxygen radicals is also increased, so that the shoulder of the substrate is formed into a rounded shape. The required thickness of the oxide film can be set smaller. As a result, it is possible to further suppress the occurrence of defective embedding.

According to the fourth aspect of the present invention, since Ne, Ar, Kr, and Xe atoms are heavier than oxygen atoms, these gases are used as inert gases. Thereby, oxygen can be efficiently activated.

According to the fifth aspect of the present invention, the ions of the inert gas are vertically drawn into the substrate by the bias voltage applied to the substrate, and are sputtered by the ions to form the side surfaces of the recess. Can suppress the growth of the oxide film. As a result, the thickness of the oxide film on the side surface of the concave portion is reduced, so that it is possible to further suppress the occurrence of the embedding failure in the step (d).

According to the sixth aspect of the present invention, it is possible to obtain a semiconductor device having an element isolation insulating film having high isolation performance without increasing the isolation width.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps;

FIG. 2 is a sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps;

FIG. 4 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps;

FIG. 5 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps;

FIG. 7 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps;

FIG. 8 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a sectional view showing one step of a method of manufacturing a semiconductor device according to Embodiment 3 of the present invention.

FIG. 10 is a sectional view showing a conventional method for manufacturing a semiconductor device in the order of steps.

FIG. 11 is a sectional view showing a conventional method for manufacturing a semiconductor device in the order of steps.

FIG. 12 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps.

FIG. 13 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps.

FIG. 14 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps.

FIG. 15 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps.

FIG. 16 is a sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps.

FIG. 17 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps.

FIG. 18 is a cross-sectional view illustrating a situation where a filling failure has occurred in a trench.

[Explanation of symbols]

1 silicon substrate, 5 trenches, 6,7 silicon oxide film, 8 element isolation insulating film, 9 power supply.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noboru Morimoto 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5F032 AA14 AA36 AA44 AA77 BA01 CA17 DA04 DA23 DA24 DA25 DA53 5F058 BA02 BC02 BD01 BD04 BF07 BF73 BJ01 BJ06

Claims (6)

[Claims] (A) a step of preparing a substrate; (b) a step of selectively forming a recess in a main surface of the substrate; and (c) an oxide film on an inner wall of the recess by plasma oxidation. And (d) embedding an insulating film in the concave portion in which the oxide film is formed. 2. The method according to claim 1, wherein the step (d) is performed with HDP (High Density).
2. The device isolation according to claim 1, further comprising a step of depositing the insulating film in a ty-plasma-CVD chamber, wherein the step (c) is performed in the HDP-CVD chamber. A method for forming an insulating film. 3. The element isolation insulating film according to claim 1, wherein in the step (c), the plasma oxidation is performed using a source gas containing an inert gas. Method. 4. The inert gas includes Ne, Ar, Kr,
4. The method for forming an element isolation insulating film according to claim 3, wherein the gas is any one of Xe. 5. The device isolation according to claim 3, wherein in the step (c), a bias voltage having a polarity opposite to that of the ions of the inert gas is applied to the substrate. A method for forming an insulating film. 6. A method for manufacturing a semiconductor device, comprising the method for forming an element isolation insulating film according to claim 1.