JPS6223128A - Method for forming element isolating region - Google Patents

Abstract

PURPOSE:To accomplish embedding and realize enhanced integration without causing the top of the filler in an element-isolating groove to sink or to contain a cavity by a method wherein single-crystal silicon is grown by the selective epitaxial method and is embedded in the element-isolating groove. CONSTITUTION:On the exposed portion in a groove 15 in a single-crystal silicon substrate 11, that is, only on the single-crystal silicon on a bottom 17, single- crystal silicon is grown by the selective epitaxial method. The groove 15 is embedded with single-crystal silicon 18 which reaches near the surface of the single-crystal silicon substrate 11. Thermal oxidation is accomplished with an Si3N4 film 13 serving as an oxidation-resistant mask for the formation of an SiO2 film 19 as a second insulating film on top of the embedded single-crystal silicon 18. After this, the Si3N4 film 13 and SiO2 film 12 are removed for the completion of an element isolating region 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for forming an element isolation region in a semiconductor device.

[Background technology]

In a semiconductor device, an element isolation region is formed to insulate and isolate elements. The following methods are currently being considered as methods for forming the element isolation regions. That is, Fig. 3 t
As shown in FIG. 1, grooves 2 for element isolation are formed in the silicon substrate 1, and then oxidation 11 is performed by oxidation. 1 (S + Ox film) 3 is formed, and polycrystalline silicon (or S IO2) 4 is deposited by CVD on the entire surface of the silicon substrate 1 on which the groove 2 is formed.
(Chemical Vapor D=posit
ion) method to fill the trench groove 2, and then nip back to flatten the surface of the silicon substrate 1 and deposit polycrystalline silicon (or SiO,
) 4 is embedded into an element isolation region 5.

However, if such pressure is applied, it is difficult to etch back with good uniformity and controllability, and the upper part of the buried polycrystalline silicon (or SiOx) 4 is removed as shown in FIG. I feel depressed.

Therefore, if a wiring formed in a later step crosses this depressed groove portion, it may cause disconnection or short circuit.

Further, as shown in FIG. 5, since trenches with different widths exist as the element isolation trenches 2 formed in the silicon substrate 1, it is not possible to fill a wide trench.

Further, depending on the shape of the groove 2 (for example, barrel shape), there is a problem that a cavity 6 is formed in the buried portion as shown in FIG.

The temperature for the drench aisle method is given in the I-D KenM 1982 Technical Digest (I
EDM 82 TECHNICAL DIGES
T) Described in P237.

[Purpose of the invention]

An object of the present invention is to prevent the buried upper part of the element isolation trench from falling into the trench and without creating a cavity.
Moreover, a plurality of grooves with different groove widths can be simultaneously embedded in single crystal silicon or polycrystalline silicon at ℃.
An object of the present invention is to provide a method for forming an element isolation region as described in item 5, which forms an element isolation region that enables high integration.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a groove for element isolation is formed in a single-crystal silicon substrate, an oxide film (SiOx film) is formed on the sidewalls of the groove, and single-crystal silicon is selectively epitaxially deposited on the exposed single-crystal silicon at the bottom of the groove. or by depositing polycrystalline silicon by selective CVD method, the single crystal silicon or polycrystalline silicon is buried inside the groove up to the vicinity of the surface of the single crystal silicon substrate, and the buried single crystal silicon or The present invention provides a method for forming an element isolation region in which an oxide film (S + Ox film) is formed by thermally oxidizing the upper part of polycrystalline silicon. Grow silicon by selective epitaxial method, or selectively grow polycrystalline silicon by CVD
Since the buried upper part of the element isolation trench does not fall into the trench and does not create a cavity, a plurality of trenches with different trench widths can be simultaneously deposited using the monocrystalline silicon or It can be filled with polycrystalline silicon, thereby forming an element isolation region that enables high integration.

[Example 1] Figure 1 fat~(fl shows a first example of the method for forming an element isolation region according to the present invention, and in particular, the figure teltfl shows an example of MO8 formed by the element isolation region formed by the method of the present invention. This is to explain the separation between elements.The present invention will be explained below using FIG.

First, as shown in the same figure [al] (P-type single crystal silicon substrate 1
A 5iOz film 12 is formed by oxidation on 1, and then a silicon nitride (S 1sN4) K 13 and a 5in2 film 14 as a mask member are sequentially formed.
in2rIA14 + 5lsNa membrane 14, S
1lN4 film 13 and S + Ox lli@12
On the other hand, the exposed single-crystal silicon substrate 11 is covered with a 5-inch film 14 after patterning the trenches for element isolation.
Using as a mask, etching is performed by anisotropic etching to form a groove 15 of, for example, 0.3 to 7 μm.
The inside is oxidized to form a Sin film 16 as a first insulating film. Next, a p layer 43 as a channel stopper is formed in the Si substrate at the bottom of the groove by ion implantation. In addition,
Si, N<base layer of film 13 K Si O! A film 12 is formed to relieve stress due to film pressure.

Next, as shown in the same figure [bl], S was etched by anisotropic etching.
The r02 film 16 is etched to expose the single crystal silicon substrate 11 on the bottom surface 17 of the groove 15.

Next, as shown in FIG. Single-crystal silicon 18 is buried to the vicinity of the surface of single-crystal silicon substrate 11, and Si, N+ film 13
Thermal oxidation is performed using the oxidation-resistant mask as
, to form a film 19. Note that before the formation of the Sin film 19, a p+ layer 44 as a channel stopper may be formed on the surface of the single crystal silicon 18 by an ion implantation trap.

Thereafter, as shown in tdl in the figure, the Si3N4 film 13, SiQ, and film 12 are removed. As a result, element isolation regions 20 are formed.

Next, as shown in tel of the figure, a gate oxide film 21 is formed,
Thereafter, a gate electrode (here, for example, a polycrystalline silicon gate electrode) 22 is formed, and further an N 2 diffusion layer 23 as a source and drain region is formed. Furthermore, as shown in FIG. 1fl, a 5-inch film 24 was formed as an interlayer insulating film,
After this, a contact hole of 25° is formed, and A2 pattern 1fiA2
form 6. In this manner, the '1:N channel MOS transistors 27 and 28 are insulated and separated by the element isolation region 20.

In FIG. 1cl, single crystal silicon is grown on the exposed single crystal silicon at the bottom of the groove 15 by a selective epitaxial method, and the inside of the C groove 15 is filled with single crystal silicon 18. Polycrystalline silicon 18' may be selectively deposited only on the exposed single-crystal silicon by the CVD method, and the inside of groove 15 may be filled with polycrystalline silicon 18' up to the vicinity of the surface of single-crystal silicon substrate 11 in the same manner as described above. In this case as well, the buried polycrystalline silicon 18'
By thermally oxidizing the upper part of the S
In! A film 19' is then formed.

As can be seen from the above, when forming the element isolation region 20, there is a method of burying the element isolation trench 15 in FIG. 1b.
As shown in llcl, the single crystal silicon substrate 1 in the groove 15
Only the upper part of the single crystal silicon on the exposed bottom surface 17 of the groove 15 is grown using the selective epitaxial method. crystalline silicon 18
(or polycrystalline silicon 18), the buried single crystal silicon 18 (or polycrystalline silicon 18)
8) The trench groove 15 is buried in the single crystal silicon 18 (or polycrystalline silicon 18') up to the vicinity of the surface of the single crystal silicon substrate 11 without the upper part of the trench 15 falling into the groove 15 and without creating a cavity as in the conventional case. The groove width can vary depending on the location, such as the groove width for separating memory cells in MOS memory is small, but the groove width for device isolation in peripheral circuits is wide. ) can also be simultaneously incorporated into the single crystal silicon 18 (or polycrystalline silicon 18').

Groove 15' in a single crystal silicon substrate like this? : form,
A film 16 of Sin is formed on the walls of this groove 15, and then the inside of the groove 15 is covered with single crystal silicon 18 (or polycrystalline silicon 18).
8) The element isolation region 20 obtained by burying the LS
High integration of I becomes possible.

Note that the element isolation region 20 (particularly the monocrystalline silicon 13 and polycrystalline silicon 18' portions) has the same potential as the silicon substrate 11. In this case, the same impurities as the silicon substrate 11 are added to the single crystal silicon 18. It is preferable to put it in a high concentration in the polycrystalline silicon 18 portion. In this manner, the MO8 elements can be separated by .degree. C. by the element isolation region 20 having the same potential as the silicon substrate 11.

Furthermore, even if there are variations in the depth of the six grooves 15, since the selective epitaxial method or the selective CVD method is used to fill the grooves 15 as described above, the six grooves 15 can be filled without problems. .

In addition, after removing the Si3N4 film 13 in 1dl of FIG. 1, a Si film is deposited on the entire surface, and a photoresist is further applied and flattened. By sexual etching (ot-
The same selection ratio as ixw variable El Cotote, S+Ot[12] can be obtained. ) By etching the photoresist and the Sin film, the surface of the silicon substrate 11 can be further planarized.

[Example 2] Figures 1al to tfl show a second example of the method for forming an element isolation region according to the present invention. As shown in FIG. 1dl, the MO8 elements are insulated and separated from each other.

Hereinafter, the present invention will be explained using FIG. 2.

First, as shown in FIG. 1al, an oxide film (Sin, film) 32 is formed on the entire surface of a p-type silicon substrate 31. A silicon nitride (sisN4) film 33 and a phosphosilicate glass (PSG) film 34 are formed in this order. 5iO1
The film 32 is used as a base for the Si, N4 film 33 for stress relaxation. These PSG films 34. Sara KS
i$N4 membrane 33. The Sing film 32 is patterned with a trench groove for element isolation, and the exposed silicon substrate 31 is etched by anisotropic etching using the PSG film 34, Si, N, film 33, and Sin film 32 as a mask. A trench groove 35 is formed, and then the groove 35 is
An oxide film (S+O
tgi) 36Y is formed. Next, a p'' layer 45 as a channel stopper layer is formed into the Si substrate at the bottom of the groove by ion implantation.
form. Although the PSG film 34 is used, an insulating film (including an oxide film) doped with impurities such as a boron silicate glass (BSG) film may also be used.

Next, as shown in FIG. tbl, a polycrystalline silicon film 37 is formed to a thickness of 0.1 to 0.2 μm over the entire surface by CVD, and annealed at a temperature of 900 to 1000° C. By this annealing process, the crystalline silicon film 37 on the PSG film 3 and 4 is
tPl is doped only in the third and fourth PSG films.

Next, as shown in FIG. 1cl, the polycrystalline silicon film 37 is thermally oxidized to form an oxide film (Si0m film) 38.

In this case, since the crystalline silicon on the PSG film 3 and 4 is doped with phosphorus, the oxidation rate is fast and all of it is oxidized, but the polycrystalline silicon 37 in the trench 35 is not doped with phosphorus and is not Only the surface is oxidized.

Next, by anisotropically etching the SiO film 38, polycrystalline silicon is exposed on the bottom surface 39 of the groove 35, as shown in FIG. Selectively polycrystalline silicon 4
0 is deposited to fill the inside of the trench 35 with this polycrystalline silicon 40.
It is buried up to the vicinity of the surface of the silicon substrate 31.

Next, as shown in FIG. 1et (PSG film 34?: removed, S
Using the i3N4 film 33 as an oxidation-resistant mask, thermal oxidation is performed to form a Sing film 41 film type 1' as a fourth insulating film on top of the polycrystalline silicon 40 buried in the trench 35. As a result, an element isolation region 42 is formed. Ru.

Next, as shown in Figure 1, Si, N4 film and SiO
The x film 32 is removed. The element isolation region 42 formed in this manner provides insulation isolation between the MO3 elements as shown in FIG.

When forming the element isolation region 42 formed as described above, a method of burying the element isolation groove 35 is shown in FIG.
As shown in dl, 40 ft of polycrystalline silicon was deposited on the exposed polycrystalline silicon at the bottom of the groove 35 by the selective CVD method, and the inside of the groove 35 was filled with polycrystalline silicon 40'' CC. The same effects as in Example 1 are achieved.

〔effect〕

(1) When filling the trench for element isolation, single crystal silicon was grown by selective epitaxial method or polycrystalline silicon was deposited by selective CVD method to fill the trench. A plurality of grooves having different groove widths can be filled with the single crystal silicon or polycrystalline silicon at the same time without causing the internal pressure of the buried upper part of the groove to drop and without creating a cavity.

+21 111 can form an element isolation region that enables high integration.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the first embodiment (FIG. 1), as the second insulating film and Si
The Ox film 19 (19') is used, but any insulating film may be used. Further, in the first embodiment, CS is used as a mask member.
Although the i 2 O film 14 is used, a PSG film or other oxide film may also be used.

Further, in the second embodiment (FIG. 2), the third insulating film and the fourth insulating film are a Si0g film 36 and a Sin0g film 36, respectively.
Although 1 is used for 41 g films, in short, any insulating film may be used.

I have explained the element isolation process of NMOS IC above.
As shown in FIG. 7, it can also be applied to well separation of 0MO8IC.

[Application field]

In the above explanation, we will explain the invention made by the present inventor in the field of application such as MO3LSI.
When applied to the isolation technology of OS devices, the
Although described above, the present invention is not limited thereto, and can be applied, for example, to element isolation technology for bipolar devices such as bipolar LSIs, and further to insulation isolation technology for semiconductor devices in general. Furthermore, a part of the present invention can also be applied to embedding when creating a trench capacitor in a dynamic RAM.

[Brief explanation of the drawing]

FIG. 1 (al to lfl, respectively, are cross-sectional views of main parts showing the first embodiment of the method for forming an element isolation region according to the present invention, and FIG. Main part process sectional views 1 and 3 showing the second embodiment [a
1 and lbl are cross-sectional views of the ☆ process showing an example of a conventional method for forming an element isolation region, FIGS. 4 to 6 are explanatory diagrams for explaining problems in the conventional method, and FIG. FIG. 7 is a cross-sectional view showing a well separation process of CMO8IC, which is another example of the present invention. 11...p-type single crystal silicon substrate, 12.14°16
, 19, 19'...Sin, film, 13...S
i s N, film, 15... element isolation trench, 1
7... Bottom surface of groove, 18... Single crystal silicon, 18.
...Polycrystalline silicon, 20...Element isolation region, 31.
...Silicon substrate, 32.36, 38.41...Si
n, film, 33...Si3N4#tL 34...PS
Gl [, 35... element isolation trench, 37.40
...Polycrystalline silicon, 39...Bottom of groove, 42...
- Element isolation region, 43, 44. 45... Channel stopper layer, 46... Single crystal silicon, 47... 3I0
1 film, 48... Single crystal silicon, 49... Well isolation region, 50... N type well, 51... P well,
52... Gate electrode, 53... N diffusion layer, 54...
...P diffusion layer, 55...sio, s6...contact hole, 57...Ai wiring. Agent: Patent Attorney Katsuo Ogawa; 1st
Figure 1 Figure 2 Figure 2 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. A step of forming a trench for element isolation in a single crystal silicon substrate, a step of forming a silicon dioxide film on the side wall of the trench, and a step of forming a silicon dioxide film on the exposed bottom of the trench. growing single-crystal silicon by a selective epitaxial method to bury the single-crystal silicon inside the groove up to the vicinity of the surface of the single-crystal silicon substrate, and forming a second insulating film on top of the buried single-crystal silicon; 1. A method for forming an element isolation region, comprising: 2. The method of forming an element isolation region according to claim 1, wherein a silicon dioxide film formed by oxidation is used as the first insulating film. 3. The element isolation region according to claim 1 or 2, wherein the second insulating film is a silicon dioxide film obtained by thermally oxidizing the upper part of the buried single crystal silicon. Formation method. 4. The step of forming the element isolation groove includes sequentially forming a silicon nitride film and a mask member on a single crystal silicon substrate, and then patterning the groove portion on the mask member and the silicon nitride film. ,
4. The method of forming an element isolation region according to claim 3, wherein the trench is formed by etching the exposed single crystal silicon substrate. 5. Forming a trench for element isolation in a single crystal silicon substrate, forming a silicon dioxide film on the side walls of the trench, and selective CVD of polycrystalline silicon on the exposed single crystal silicon at the bottom of the trench. burying the polycrystalline silicon in the trench up to the vicinity of the surface of the single-crystal silicon substrate by depositing the polycrystalline silicon by a method, and forming a second insulating film on top of the buried polycrystalline silicon. Characteristic method for forming element isolation regions. 6. The method of forming an element isolation region according to claim 5, wherein a silicon dioxide film formed by oxidation is used as the first insulating film. 7. The element isolation region according to claim 5 or 6, wherein the second insulating film is a silicon dioxide film obtained by thermally oxidizing the upper part of the buried polycrystalline silicon. Formation method. 8. The step of forming the element isolation groove includes sequentially forming a silicon nitride film and a mask member on a single crystal silicon substrate, and then patterning the groove portion on the mask member and the silicon nitride film. ,
8. The method of forming an element isolation region according to claim 5, wherein the trench is formed by etching the exposed single crystal silicon substrate. 9. Forming a trench for element isolation in a silicon substrate, forming at least a third insulating film on the entire inner wall of the trench, and forming a polycrystalline silicon film so that polycrystalline silicon is exposed only at the bottom of the trench. a step of depositing polycrystalline silicon on the exposed polycrystalline silicon at the bottom of the trench by a selective CVD method to bury the polycrystalline silicon inside the trench up to the vicinity of the surface of the silicon substrate; 1. A method for forming an element isolation region, comprising the step of forming a fourth insulating film on top of crystalline silicon. 10. The method of forming an element isolation region according to claim 9, wherein a silicon dioxide film formed by oxidation is used as the third insulating film. 11. The method of forming an element isolation region according to claim 10, wherein a silicon dioxide film obtained by thermally oxidizing the upper part of the buried polycrystalline silicon is used as the fourth insulating film. 12 After forming a silicon nitride film and an impurity-doped insulating film on a silicon substrate, a groove for element isolation is formed, and then a polycrystalline silicon film is formed on the entire surface by CVD method, and then an annealing treatment is performed. Furthermore, by thermal oxidation, the polycrystalline silicon film in the trench is made into an oxide film, leaving a part of the thickness, and the entire polycrystalline silicon film in the trench is made into an oxide film. Next, the oxide film is etched by anisotropic etching to expose the polycrystalline silicon only at the bottom of the groove, and polycrystalline silicon is deposited on the polycrystalline silicon by selective CVD to form the polycrystalline silicon inside the groove. burying silicon to the vicinity of the surface of the silicon substrate, then removing the insulating film, thermally oxidizing the upper part of the buried polycrystalline silicon to form a silicon dioxide film, and then removing the silicon nitride film. A method for forming an element isolation region according to claim 9.