JPS60136330A - Manufacture of complementary metal insulator semiconductor device - Google Patents

Abstract

PURPOSE:To enable a narrower and deep isolation region of an insulator to be formed easily, by selectively forming a recess having sheer side walls, providing the insulator selectively on the side walls and thereafter growing single crystal semiconductor within the recess. CONSTITUTION:A recess 4 when formed by an anisotropic etching process has approximately vertical side walls 4a. A silicon wafer with such a recess is provided with an insulator layer 5 of SiO2 covering all over the surface including the sheer side walls 4a. The surface is then processed by reactive ion etching so that the insulator 5 is selectively left only on the side walls 4a while the silicon is exposed only on the bottom of the recess 4. Single crystal silicon is grown within the recess 4 and doped with B so as to form a P type well 7. In N type regions inside and outside the well 7, MOSFET's 12 and 13 with P channels are completed, respectively. The well 7 is surrounded by narrow and deep isolation region 14 consisting of the insulator 5.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a CM OS (Complement, a
ry MetalOxide Sem1conduct
The present invention relates to manufacturing technology for complementary metal-insulator semiconductor devices, typically LSI, and particularly to technology effective in achieving high integration and preventing latch-up.

[Background Art] In a complementary metal-insulator semiconductor device, a well of a second conductivity type, which is an opposite conductivity type, is formed on one surface of a semiconductor substrate of a first conductivity type, and a metal of a first conductivity type is formed inside and outside the well. An insulator semiconductor element and a second conductivity type metal-insulator semiconductor element are respectively formed. For this reason, it is necessary to electrically isolate the inside and outside of the well, and conventionally, LOGO3 (
Local 0x-idaeion of 5ilic
on) method was used.

However, in order to prevent latch-up, the isolation region using the LOCO8 method has a sufficient width (for example,
7 to 8 μm), which poses a problem in achieving high integration.

Therefore, a technique has been proposed in which an isolation region is formed by a deep groove called a trench and an insulator filling the inside thereof. This is a method in which a groove with a width of about 1 μm and a depth of about 5 μm is formed, and then the groove is filled with silicon dioxide, etc., and the LO
In place of the horizontally elongated separation region with a sufficient distance in the plane in the COS method, a vertically elongated separation region with a sufficient distance in the depth direction of the semiconductor substrate is used (see Nikkei Electronics, 1982). June 21 issue, No. 14
(See pages 6-151).

However, according to the inventor's study, this proposed method has the following:
The following problems were found.

(1) The width of the isolation region is determined by photolithography technology, and its lower limit is, for example, about 0.8 μrn.

(2) It is extremely difficult to form narrow and deep trenches, and it is also difficult to fill such trenches with an insulator.

(3) Since impurities are introduced into the well after the trench structure is formed, the well cannot be formed using self-alignment, and an extra mask is required.

Particularly in this case, mask alignment is extremely difficult because the groove width is narrow.

[Object of the Invention] An object of the present invention is to provide a technique that can easily form a vertically elongated insulating material front region having a narrower width.

Another object of the present invention is to
The object of the present invention is to provide a technology that allows wells to be formed using Selfa Line.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying four drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, a concave portion with steep side walls is selectively formed in a portion of one surface of a semiconductor substrate where a well is to be formed;
CVD (Chemical Vapor Dep-
An insulator for forming an insulator isolation region is selectively formed on the side wall portion by a combination of the osit, 1on) method and anisotropic etching, or a combination of selective oxidation and anisotropic etching, and then an insulator is formed in the recess. Single crystal semiconductors are grown selectively. As a result, the width of the insulator isolation region is determined by the film thickness obtained by CVD or selective oxidation, so it can be formed extremely narrow, for example, on the order of 0.1 to 0.5 μm, without using photolithography.

Furthermore, the mask layer used as a mask for etching when forming the recesses can also be used as a mask for introducing impurities when forming wells by introducing impurities into the region of the single crystal semiconductor. Formation can be self-aligned.

[Example 1] Figures 1 to 6 are process diagrams showing an example in which the present invention is applied to a CMO8LSI.

(Refer to Figure 1) N-type silicon wafer 1 which is a semiconductor substrate of the first conductivity type.
A silicon dioxide (SiO2) film 2 is formed on the surface by thermal oxidation or CVD, and then patterned to form a mask layer 3 covering areas other than the areas where wells are to be formed. This mask layer 3 is used as a mask for silicon etching in the next step, and as a mask for selective epitaxial growth and ion implantation in subsequent steps. therefore,
The film should be set to an appropriate thickness so that it remains even after silicon is etched and the remaining material can function as a mask for ion implantation.

(See FIG. 2) Then, using the mask layer 3 as a mask for etching, the quadrature 4 is formed on the surface of the silicon wafer 1 by anisotropic etching, for example reactive ion etching. Since the etching process is anisotropic, the side walls 4a of the four parts 4 are steep and almost vertical. Since a single crystal semiconductor will later be selectively grown in the recess 4 and a P-type well will be formed there, the etching depth of the recess 4 will be approximately the same as or more than the depth of the well, for example, approximately 5 μm. shall be. The depth of this recess 4 defines the depth of the separation region.

(Refer to FIG. 3) After forming the recess 4, the entire surface of the silicon wafer 1 is subjected to CVD.
An insulator layer 5 made of 5i02 is formed by a method. The insulating layer 5 is required to completely cover the steep sidewall 4a. Therefore, for forming the insulating layer 5, it is preferable to use a CVD method under conditions with good coverage, such as high temperature and low pressure. Since the insulating material 5 covering the side wall 4a constitutes an electrically isolated region, the thickness of the insulating material (layer) 5 is, for example, about 0.1 to 0.5 μm to make it pinhole-free. It's good.

(See FIG. 4) Next, the surface of the silicon wafer 1 on which the insulator 5 has been deposited is subjected to an anisotropic reactive ion etching process to etch the side walls 4a.
The insulator 5 is selectively left only in the area. Since reactive ion etching has extremely high etching directionality, only the bottom of the recess 4 and the insulator 5 on the mask layer 3 are removed.

(See FIG. 5) When the reactive ion etching process is completed, the surface of the silicon wafer 1 is in a state where only the bottom 4b of the recess 4 has silicon exposed. Therefore, by selective epitaxial growth,
Silicon 6, which is a single crystal semiconductor, can be grown only within the four parts 4.

As the reaction gas, a mixed gas of dichlorosilane, hydrogen chloride, and hydrogen is used. In this case, by simultaneously doping boron, which is a P-type impurity of the second conductivity type, into the silicon 6, the P-type well 7 can be formed at the same time as the selective epitaxial growth is completed. The P-type well 7 can also be formed by selective epitaxial growth of silicon 6, followed by ion implantation and subsequent thermal diffusion. In either case, the mask layer 3 functions as a mask for boron introduction, so
It does not require a separate mask. Note that the thickness of the single crystal silicon 6 to be selectively epitaxially grown is set so that its surface coincides with the surface of the silicon wafer 1.

(See FIG. 6) After removing the mask layer 3 by wet etching with a hydrofluoric acid solution, a gate oxide film 8, a gate 9 made of polysilicon, etc., and a P+ type or N+ type source, drain 1
0. s, 10d; 11s, 11d Furthermore, an insulating protective film and aluminum wiring (not shown) are formed. As a result, N-channel MO3 is placed inside the P-type well 7.
The FET 12 is also connected to the N-type region outside the well 7.
Each channel MO3FET 13 is completed.

The peripheral part of the well 7 is made of an insulator 5 with a width of 0, i-
Since there is a vertically long isolation region 14 of about 0.5 μm and 5 μm deep, this structure is advantageous in preventing latch-up caused by parasitic vertical and lateral bipolar transistors.

[Example 2] In Example 1, one separation region 14 was coated with the coating 5 by the CV and D method.
However, the isolation region 14 can also be formed by 5i02 using denser thermal oxidation. In this case, the mask layer 3 is formed of an oxidation-resistant material such as silicon nitride (Si3N4), and after the recess 4 is formed,
Using the mask layer 3 as a mask for selective oxidation, a 5i02 oxide film is formed on the inner surface of the recess 4 including the side wall 4a, and then the oxide film is anisotropically etched. The subsequent steps are the same as in Example 1.

In this case, the mask layer 3 made of Si3N4 is placed in the recess 4.
It is necessary to leave it on the silicon wafer 1 even after the formation of the silicon wafer 1 and to function as a mask for the subsequent anisotropic etching and ion implantation. Furthermore, in this second embodiment, if the Si3N4 film 3 is directly deposited on the silicon substrate 1 and then subjected to heat treatment (oxidation), crystal defects are likely to occur in the silicon substrate 1 due to stress. Therefore, it is desirable to insert a thin 5i02 film between the Si3N4 film 3 and the silicon substrate 1 for stress relief.

[Example 3] In Example 1 and Example 2, a so-called single-well method was described in which only a P-type well was formed. A so-called double-well system may be adopted in which an N-well is also formed on the P-channel MO8FET side. FIG. 7 to FIG. 16 are process diagrams showing an embodiment of this double-well system.

(Refer to FIG. 7) N-type silicon wafer 1 which is a semiconductor substrate of the first conductivity type
Phosphorus ions 15 are introduced into the surface of the substrate by an ion implantation method to form an N-type implantation layer 16.

Here, it is desirable that the concentration of the silicon wafer 1 is lower than the concentration of the N well and the P well, and is indicated as N- in the examples.

(See FIG. 8) Next, a 5i02 film 2 is formed on the surface of the silicon wafer 1 by thermal oxidation or CVD. Note that the phosphorus ion implantation in FIG. 7 may be performed after the 5i02 film 2 is formed. The following steps shown in FIGS. 9 to 12 are the same as those in FIGS. 1 to 4 of Example 'l, and therefore their explanation will be omitted. Note that during silicon etching in FIG. 1-0, the phosphorus implantation layer 16 in the region where the P-type well is to be formed is
is removed by etching.

(Refer to FIG. 13) When the process shown in FIG. 12 is completed, the surface of the silicon wafer 1 is in a state where only the bottom 4b of the recess 4 is exposed. In this state, single crystal silicon 6 is grown in the recess 4. The type and concentration of impurities in the silicon 6 at this time may be the same as in the silicon wafer 1.

(Refer to FIG. 14) Next, using the 5iO7 film 3 as a mask, boron ions 17 are introduced into the silicon 6°, that is, the region to be a P-type well, by ion implantation to form a P-type implantation layer 18.

(Refer to FIG. 15) Next, the N-type implantation layer 16 and the P-type implantation layer 18 are stretched and diffused at a high temperature of about 1100-1200°C.
N-type well 19. A P-type well 7 is formed.

(Refer to FIG. 16) Next, as in the first embodiment, N-channel MO3FET12, P
A channel MOS FET13 is formed.

Incidentally, in the third embodiment, the stretching diffusion of the N-type well is carried out simultaneously with the stretching diffusion of the P-type well as shown in FIG. 1.5, but these may be carried out separately. In that case, the stretching diffusion of the N-type well may be performed at any point during the process up to FIG. 15, as long as it is after silicon etching is performed to form the recess 4 in FIG. 10.

[Effects] (1) Located in the periphery of the well. Since the width of the vertically long insulator isolation region can be defined by the film thickness by CVD or thermal oxidation, it can be formed extremely narrow, for example, on the order of 0.1 to 0.5 μm, without being constrained by photolithography technology. .

Therefore, the area occupied by the isolation region is reduced, and the device can be further integrated.

(2) Since the depth of the insulator isolation region is determined by the etching depth of the portion where the well is to be formed, a deep isolation region can be formed relatively easily compared to the conventional trench structure.

(3) The mask layer for etching the part where a well is to be formed can be used as a mask for impurity introduction when forming a well by introducing impurities into a single crystal semiconductor by selective growth. Formation can be self-aligned.

Although this invention has been specifically described above based on Examples, it goes without saying that this invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. For example, when forming the insulating layer 5 by the C, VD method, the inner surface of the recess including the side wall 4a is thermally oxidized and
After forming a thin and dense 5i02 film of about 0 to 50 nm, an insulator J'f' such as 5iOz is formed by the Cvr) method.
15 may be formed. By doing so, the dielectric strength can be improved compared to the case where only the insulating layer is formed by the CVD method. Further, the semiconductor substrate 1 is of P type.

Well 7 may be of N type. Furthermore, semiconductor substrate 1.
Alternatively, an epitaxial wafer having an epitaxial layer on a silicon wafer substrate can also be used.

Furthermore, in Examples 1 to 3, the impurity concentration distribution of the well formed by selective epitaxial growth can be controlled to an arbitrary distribution. This can be easily controlled by continuously changing the ratio of the impurity gas to the carrier gas and the main reaction gas for depositing silicon. Diborane B2H6 may be used as the impurity gas.

The impurity concentration distribution in the well is preferably as shown in FIG. 17. That is, the impurity concentration in the inside of the well is higher than that on the surface. This can prevent latch-up (thyristor phenomenon) caused by parasitic transistors. This impurity concentration distribution can be easily achieved as described above. Impurities of the opposite conductivity type to the well are introduced onto the surface of the well.

Although lowering the surface carrier concentration lowers the mobility, such a method is not necessary.

Although a method using ion implantation with high acceleration energy on the order of M eV is difficult, this method is not necessary.

[Field of Application] The present invention can be applied to complementary metal-insulator semiconductor devices such as CVD8, particularly highly integrated and high-performance devices, to obtain great effects.

[Brief explanation of drawings]

Figures 1 to 6 are cross-sectional views showing one embodiment of the present invention in order of process, Figures 7 to 16 are cross-sectional views showing other embodiments of this invention in order of process, and Figure 17 is a cross-sectional view showing an embodiment of the present invention in order of process. It is a figure showing distribution. DESCRIPTION OF SYMBOLS 1... Semiconductor base (silicon wafer), 3... Mask layer, 4... Recessed part, 4a... Side wall, 5... Insulator, 6... Single crystal semiconductor, 7... P Type well, 12.
... N channel MOSFET, 13... P channel MOSFET, 14... Insulator isolation region, 15... Phosphorus ion, 16... Phosphorus implantation layer, 1
7...Boron ion, 18...Boron implantation layer, 1
9...N type well. Figure 1 Figure 2 Figure 3 Figure 5/ Figure 6 Figure 7 + + + + + + “”

Claims (1)

[Claims] (1) A well of a second conductivity type, which is an opposite conductivity type, is provided on one surface of a semiconductor substrate of a first conductivity type, and a metal-insulator semiconductor element of a first conductivity type and a second conductivity type are disposed inside and outside the well. A complementary metal-insulator semiconductor having nine conductive-type metal-insulator semiconductor elements and having a vertically long insulator isolation region around the well that is as deep as or deeper than the well. 1. A method for manufacturing a complementary metal-insulator semiconductor device, the method comprising at least each primary step in manufacturing the device. (A) A mask layer is formed to cover the area other than the area where the well is to be formed on one surface of the semiconductor substrate of the first conductivity type, and the mask layer is used as a mask for etching to form a cut in the area where the well is to be formed. A process of forming four parts having +1!l walls. (B) A process of selectively forming an insulator for forming the insulator isolation region on the side walls of these four parts. (C) After the (B) process, a recess is formed. (1)) A step of introducing impurities into a region of the single crystal semiconductor to form a well at the same time as step (C) or after step (C). 2. As a means for selectively forming an insulator in the step (B), after the step (A), #! is applied to the entire surface of the semiconductor substrate. ! After depositing the edges, # deposited! ! Claim 1 using a method of anisotropically etching the textile layer
A method for manufacturing a complementary metal-insulator semiconductor device as described in 1. 3. The mask layer in the step (A) is formed of an oxidation-resistant material, and as a means for selectively forming an insulator in the step (B), after the step (A), the mask layer is used as a mask for selective oxidation. Claim 1 uses a method in which an oxide film is formed on the inner surface of the recess including the side wall, and then the oxide film is anisotropically etched to leave the oxide film as an insulator only on the side wall portion. A method for manufacturing a complementary metal-insulator semiconductor device as described in 1. 4. The method for manufacturing a complementary metal-insulator semiconductor device according to claim 1, wherein the mask layer is used as a mask for introducing impurities in the step (D). 5. A step of introducing an impurity having the same conductivity type as the first conductivity type into the vicinity of the surface of the semiconductor substrate of the first conductivity type before the step (A), and a step of introducing this impurity after the end of the step (A). 2. The method for manufacturing a complementary metal-insulator semiconductor device according to claim 1, further comprising the step of stretching and diffusing at any point before the end of the step (D) to form a well of the first conductivity type.