JPS60241230A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a parasitic capacity and to prevent a conductor between an emitter and a collector by guiding an impurity to the wall of the inside of a groove for a separating region formed on the main surface of a semiconductor, and forming a semiconductor layer, thereby hardly forming an inverting layer. CONSTITUTION:An N<+> type buried layer 2 is formed on a semiconductor substrate 1, and an N<-> type epitaxial layer is then formed. An oxide film 21 and a nitride film 22 are formed thereon. Then, a U-shaped groove 4 is formed to pass the layer 2. Then, N type impurity is diffused in the inner wall of the groove 4 to form an N type diffusion layer 23. Then, a channel stopper layer 24 is formed. Thereafter, an insulating film 5 is formed in the groove 4. Subsequently, polysilicon 6 is deposited in the groove 4, and flattened by dry etching. With such a construction, even if the potential of the polysilicon varies, an inverting layer is hardly formed due to the layer 23.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor technology and particularly to a technique that is particularly effective when applied to semiconductor integrated circuit devices. Concerning effective techniques.

[Background Art] Conventionally, as a method for separating elements in semiconductor integrated circuits,
A junction isolation method using a diffusion layer and an oxide film isolation method using a selective oxide film called LOGO8 on the surface of a substrate are being carried out. However, in these isolation methods, the width of the element isolation region is made relatively large, and as elements become smaller, the ratio occupied by the element isolation region increases.
This becomes an obstacle to increasing the density of I (large-scale integrated circuits). Therefore, the present applicant cut away the part that would become the element isolation region to form a U-shaped groove, formed an oxide film inside this groove, and then filled the inside of the groove with a material such as polysilicon (polycrystalline silicon). He proposed an isolation technique called the U-groove isolation method, in which device isolation regions are created by filling them with dielectric material (Japanese Patent Application No. 57-16).
No. 8355).

The above-mentioned prior invention has an N-type buried layer 2 on a P-type semiconductor substrate 1.
After forming the N- type epitaxial layer 3, a groove 4 is formed so as to penetrate through the N+-type buried layer 2 by directional etching. Thereafter, an insulating film 5 such as an oxide film (Si02 film) is formed on the substrate surface and inside the groove 4 by thermal oxidation. Then, after filling the trench 4 by depositing a thick layer of polysilicon using the CVD method, an N-type collector pull-up region 7, a P-type base region 8, and an N-type emitter region 9 are formed in the element region using a known technique. After that, an aluminum electrode 13 is connected through a contact hole 12 opened in the protective film 11 (see FIG. 1).

However, in a bipolar integrated circuit to which the above-mentioned U-groove isolation method is applied, the polysilicon filled in the groove 4 is kept floating in potential. In addition, there are parasitic capacitances C between the polysilicon layer and the substrate 1 and between the polysilicon layer and the epitaxial layer 3, respectively.
1 and 02 exist. Therefore, if the lowest potential of the circuit (for example -5V) is applied to the substrate 1 and the collector is biased to ground, the potential of the polysilicon in the U-groove will be the capacitance ratio C1/(C1 + 02 ) is set to a potential (negative potential) that divides the substrate potential (-5V). Further, negative charges may be accumulated in the polysilicon during the process, causing the potential to drop.

When the potential of the polysilicon in the U-trench is lowered in this way, an inversion layer is formed in the collector region in contact with the U-trench isolation region 10 as shown by the broken line A in FIG. The mold base region 8 has a shape extending along the U-groove isolation region 10.

Therefore, the junction capacitance between the base and the collector increases, and the operating speed of the transistor decreases.

Furthermore, when horizontal PNP transistors separated by U-groove isolation regions 10 are formed on the semiconductor substrate 1 as shown in FIG. 2, negative charges are accumulated in the polysilicon in the U-groove isolation regions 1o. Then, an inversion layer is formed as shown by the broken line B on both sides of the N-type base region 8' in contact with the U-groove isolation region 10, and the P-type collector region 7' and emitter region 9' are free from parasitic M.
It becomes conductive due to the O3 effect.

Moreover, in order to reduce crystal defects associated with U-groove formation,
It is better that the insulating film 5 is thinner, and in order to reduce the junction capacitance between the base and collector (between the base region 8 and the epitaxial layer 3), and to reduce the capacitance between the base and collector,
The lower the concentration of the epitaxial layer 3, the better. However,
There is a disadvantage that the thinner the insulating film 5 is, or the lower the concentration of the epitaxial layer 3, the easier it is to form an inversion layer.

[Object of the Invention] An object of the present invention is to reduce the parasitic capacitance between the base and collector of a vertical transistor formed on the main surface of a semiconductor substrate in a semiconductor integrated circuit device to which a trench isolation method is applied, and to An object of the present invention is to provide a technique for preventing conduction between the emitter and collector of a transistor.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, after a trench is dug in the area where the isolation region is to be formed, impurities are introduced into the inner wall of the trench to form a semiconductor layer along the sides of the isolation trench in advance. Even if the potential of the dielectric within the region changes, an inversion layer is formed around the isolation region. , which achieves the above object of preventing conduction between the emitter and collector of a lateral transistor.

[Embodiment 1] FIGS. 3 to 7 show an embodiment in which the present invention is applied to a bipolar integrated circuit in the order of manufacturing steps.

In this embodiment, first, an N+ type buried layer 2 is formed on a semiconductor substrate 1 using an oxide film or the like as a mask by a known bibolar integrated circuit process, and an N- type epitaxial layer 3 is formed on it in a vapor phase. After forming by a growth method, an oxide film 21 and a nitride film 22 are formed on the surface thereof. next,
Remove the oxide film and nitride film where the isolation region will be formed,
Using this as a mask, as shown in FIG. 3, a U-groove 4 is formed that penetrates the N+ type buried layer 2 and reaches the P type substrate 1.

Then, using the nitride film 22 as a mask, an N-type impurity such as arsenic is diffused along the inner wall of the U-groove 4 by thermal diffusion to a concentration of about 10''~]017 and a thickness of 0.2~0.
An N-type diffusion layer 23 of about 5 μm is formed. In this case, instead of forming the N-type diffusion layer 23 by thermal diffusion, a polysilicon layer doped with arsenic is formed by the CVD method (chemical vapor deposition method), as shown by the chain line P in FIG. After that, heat treatment may be performed to form the N-type diffusion layer 23 by diffusion of impurities from the polysilicon layer.

Thereafter, ions of boron or the like are implanted into the U-groove 4 and diffused to form a channel stopper layer 24, resulting in the state shown in FIG. 4. Then, after forming an insulating film 5 such as an oxide film inside the U-groove 4, a polysilicon layer is deposited inside the U-groove 4 by the CVD method and flattened by dry etching. It will be in the state shown in the figure.

After the state shown in FIG. 5, for example, after removing the oxide film 21 and nitride film 22 on the surface of the epitaxial layer 3, an oxide film 15 is formed on the surface of the epitaxial layer 3 and the surface of the polysilicon layer by thermal oxidation. , a nitride film 16 is formed thereon.

Then, a hole is made in the nitride film 16, and P-type impurity ions are implanted from above the oxide film 15 using the hole as a mask, thereby forming a P-type base region 8.

Next, a polysilicon layer is formed over the entire surface by CVD, and then an N-type impurity such as arsenic is doped into the polysilicon layer by ion implantation. Thereafter, polysilicon electrodes 23a and 23b are formed by removing the polysilicon by photoetching so that it remains only on the emitter region and the portion that will become the collector pull-up port. Then, using a photoresist as a mask, only the polysilicon electrode 23b is doped with an N-type impurity such as phosphorous, and then heat treatment is performed to raise the N-type collector by diffusion of the impurity from the polysilicon electrodes 23a and 2'3b. Region 7 and N type emitter region 9 are formed. In this case, since the diffusion rate of phosphorus is faster than that of arsenic, the collector pulling region 7 is formed deeper than the emitter region 9.

Thereafter, a contact hole is formed after a glabellar insulating film 11 such as a PSG film is deposited over the entire surface, aluminum is vapor deposited on the film, and unnecessary portions are removed by photo-etching to form aluminum electrodes 13a to 13. 1
3c is formed, resulting in the state shown in FIG.

Note that after the state shown in FIG. 7, the aluminum electrodes 13a to 12c
A final passivation film is formed on the entire surface to complete the structure.

According to the above embodiment, a thin N-type diffusion layer 23 is formed in the N-type epitaxial layer 3 as a collector in contact with the U-groove isolation region.
is formed. Therefore, even if the potential of the polysilicon in the U-groove isolation region becomes lower than the collector potential by applying the lowest voltage of the circuit, such as -5V to the substrate 1, the insulating film 5 and the epitaxial layer 3 An inversion layer is formed in between.

As a result, the depletion layer between the P-type base region 8 and the epitaxial layer 3 is prevented from extending downward along the U-trench isolation region and increasing the junction capacitance.

Furthermore, if the above embodiment is applied to a lateral transistor as shown in FIG. 2, it becomes difficult to form an inversion layer around the U-groove isolation region, thereby preventing conduction between the emitter and the collector. This improves the operating speed and reliability of the bipolar transistor.

In the case of the above embodiment, ion implantation for forming the channel stopper layer 24 is performed not in a direction perpendicular to the substrate but in a direction slightly inclined to prevent deep implantation. In that case, if the N-type diffusion layer 23 is formed along the inner wall of the U groove in the above embodiment, the U
Another advantage is that the N-type impurity of the N-type diffusion layer 23 can cancel out the P-type impurity for the channel stopper implanted into the side wall of the trench.

If the concentration of the N-type diffusion layer 23 in the above embodiment is too high, the depletion layer between it and the P-type base region 8 will become narrow, which may increase the junction capacitance or lower the withstand voltage between the base and collector. . Therefore.

The concentration of the N-type diffusion layer 23 is preferably set to about 1016 to 1017, which is about one digit higher than that of the epitaxial layer 3, which has a concentration of about io'' to xolG.

[Embodiment 2] A second embodiment of the present invention is shown in FIGS. 8 and 9.

This embodiment is the same as the previous embodiment up to the point where the U-groove 4 is formed in a portion that will become one isolation region and the state shown in FIG. 3 is achieved. In this embodiment, after forming the U-groove 4, the nitride film 22 and oxide film 2, which served as a mask on the surface of the substrate, are removed.
1 is removed, and then the N-type impurity is diffused over the entire surface by thermal diffusion.

Then, as shown in FIG. 8, the surface of the substrate 1 and the U-groove 4
An N-type diffusion layer 23 is formed on the inner wall. Also in this case,
After removing the insulating film on the surface of the substrate, a polysilicon layer doped with N-type impurities is deposited over the entire surface, and then heat treatment is performed to form an N-type diffusion layer 23 by diffusion from the polysilicon. It's okay.

After the state shown in FIG. 8, a channel stopper layer 24 is formed at the bottom of the U-groove 4 by ion implantation, and then thermal oxidation is performed to form an oxide film from the substrate surface to the inner wall of the U-groove 4.
is formed, resulting in the state shown in FIG. Thereafter, using the same method as in the first embodiment, the U-groove 4 is filled with polysilicon and flattened, an oxide film is formed on the surface and the lid is covered, and then the base, emitter and By forming the collector region and their respective electrodes, a bipolar transistor having substantially the same structure as that shown in FIG. 7 is formed.

Also in this embodiment, since the N-type diffusion layer 23 is formed around the U-groove isolation region, the parasitic capacitance between the base and collector of the vertical transistor is reduced as in the first embodiment. Further, the lateral transistor has the effect of preventing emitter-collector conduction.

Moreover, according to this embodiment, the bird's head that occurs due to the formation of an oxide film at the boundary portion of the surface of the U-groove isolation region in the first embodiment is eliminated, so that planarization is facilitated. Furthermore, since the oxide film 5 formed on the inner wall of the U-groove 4 can be made thinner, crystal defects generated around the U-groove during the formation of the oxide film can be reduced, and
It is also possible to increase the degree of integration by narrowing the width of the U-groove isolation region.

Therefore, in the structure in which the thin oxide film 5 is formed in the U-groove 4, as the oxide film becomes thinner, an inversion layer due to parasitic MoS is more likely to be formed around the U-groove isolation region. There is a great advantage in forming the N-type diffusion layer 23 on the wall surface of the U-groove in advance as in this embodiment.

In the above embodiment, an oxide film 21 and a nitride film 22 are formed on the main surface of the substrate, and this is used as a mask to form the U-groove 4. Alternatively, a U-groove may be formed using this oxide film as a mask.

Furthermore, in the above embodiment, no isolation region is provided between the base and the collector, but as in the structure shown in FIG.
A relatively shallow U-groove isolation region reaching the surface of the buried layer 2 may be formed.

Furthermore, in the embodiment, the collector pulling lower is formed after the base is formed, but the collector lifting lower may be formed before the base is formed. Collector lifting lower
It may be formed by ion implantation instead of diffusion from polysilicon.

[Effects] (1) After digging a groove in the part where the separation region is to be formed,
By introducing impurities into the inner wall surface of the trench, a semiconductor layer is formed in advance along the side surfaces of the trench, so even if the potential of the dielectric within one isolation region fluctuates, the semiconductor layer around the isolation region remains constant. Due to the effect that it becomes difficult to form an inversion layer,
The parasitic capacitance between the base and collector of vertical transistors formed on the main surface of the semiconductor substrate is reduced, which improves the operating speed of the transistor and eliminates concerns about wall channels, reducing layout constraints. This has the effect of enabling high integration.

(2) After digging a groove in the part where the separation area is to be formed,
By introducing impurities into the inner walls of the trench, a semiconductor layer is formed in advance along the sides of the trench, so even if the potential of the dielectric within the isolation region fluctuates, it will not reverse around the isolation region. The effect of making the layer less likely to be formed makes it possible to prevent conduction between the emitter and collector of the lateral transistor, which has the effect of improving the reliability of the transistor.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the material filled inside the isolation trench is not limited to polysilicon, but may be other conductive material. Further, the insulating film formed inside the trench is not limited to an oxide film, but may have a two-layer or three-layer structure of an oxide film and a nitride film. Further, the shape of the groove is not limited to the U-shape, but may be a 7-shape as long as it has a structure in which a groove is dug in the substrate and filled with a dielectric material.

[Field of Application] The present invention can be applied not only to isolation regions between bipolar transistors in bipolar integrated circuits, but also to MO3 integrated circuits to which the trench isolation method is applied.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a configuration example of a bipolar transistor and its inter-element isolation region in a semiconductor device of a prior application to which the U-groove isolation method is applied. 2 is a plan view showing a configuration example of a lateral transistor; FIGS. 3 to 7 are cross-sectional views showing the first embodiment in the order of manufacturing steps when the present invention is applied to a bipolar integrated circuit; FIG. 9 and 9 are cross-sectional views showing the second embodiment in the order of manufacturing steps. 1... Semiconductor substrate, 2... N+ type buried layer, 3...
...N-type epitaxial layer, 4...separation groove (
U groove), 5... Insulating film, 6... Conductor (polysilicon), 7... Collector pull-up region, 8...
Base region, 9...Emitter region, 10...U
Groove isolation region, 11... interlayer insulating film, 12a. 12b...contact hole, 13a-13c...
...Aluminum electrode, 15.21...Insulating film (oxide film)
, 16.22...insulating film (nitride film), 23...
Diffusion layer (N type diffusion layer) 24... Channel stopper layer (P type diffusion layer), 25a, 25b... Polysilicon electrode. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. Grooves are dug between active regions of elements formed on the main surface of a semiconductor substrate, an insulating film is formed inside the insulating film, and a dielectric material is filled inside the insulating film, and then a dielectric material is formed on the surface. A semiconductor device in which an isolation region is formed by forming an insulating film, characterized in that a semiconductor layer having a higher concentration than the surrounding low concentration region is formed around the insulating film in the groove. Semiconductor equipment. 2. The element is a vertical NPN bipolar transistor, characterized in that an N-type semiconductor layer with a higher concentration than the N-type collector region is formed in a portion surrounding the isolation region and in contact with the N-type collector region. A semiconductor device according to claim 1. 3. The element is a lateral bipolar transistor, and a semiconductor layer having a higher concentration than the base region is formed at a side of the base region in contact with the isolation region. The semiconductor device according to item 1.