JP2002118262A - Semiconductor device and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its fabricating method in which process control is facilitated and a full depletion transistor can be fabricated easily. SOLUTION: The method for fabricating a semiconductor device comprises steps for preparing an SOI substrate 1, forming a gate oxide film 6b on the surface of a single crystal Si layer 4, forming a dummy gate electrode on the dummy gate oxide film, implanting impurity ions into the single crystal Si layer using the dummy gate as a mask, forming source-drain diffusion layers 16 and 17 in the single crystal Si layer by annealing, depositing a silicon oxide film on the entire surface including the dummy gate, exposing the upper surface of the dummy gate by CMP, etching the dummy gate electrode and the dummy gate oxide film using the silicon oxide film as a mask and etching the single crystal Si layer down to a specified depth, forming a gate oxide film 6b on the single crystal Si layer, and then forming a gate electrode 7b on the gate oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an SOI structure and a method for manufacturing the same. In particular, it relates to a semiconductor device capable of easily manufacturing a fully depleted SOI device and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 13 shows a conventional SOI (Silicon On In
FIG. 3 is a cross-sectional view showing a fully depleted semiconductor device having a (sulator) structure. First, the SOI substrate 1 manufactured by the bonding method
Prepare 01. The SOI substrate 101 includes a support substrate 102 made of single crystal silicon, an insulating film 103 formed on the support substrate 102, and a single crystal Si layer 104 formed on the insulating film 103. I have.

That is, a first silicon substrate (support substrate 102) having a first insulating film formed on its surface is prepared, and a second silicon substrate (single-crystal Si) having a second insulating film formed on its surface is prepared.
Prepare layer 104). Next, the first insulating film and the second insulating film are bonded to each other to form an insulating film 103 including the first and second insulating films formed on the support substrate 102 and a second insulating film 103 formed on the insulating film 103. An SOI substrate 101 including two silicon substrates (single-crystal Si layer 104) is formed. Thereafter, the thickness of the second silicon substrate is reduced to about 10 nm by polishing the back surface of the second silicon substrate.
As a result, the S including the single-crystal Si layer 104 having a small thickness is
An OI substrate 101 is formed.

Next, a trench is formed in the single-crystal Si layer 104, and a silicon oxide film is buried in the trench. Thus, an element isolation film 105 made of a silicon oxide film is formed in an element isolation region on the insulating film 103. next,
P-type impurities are ion-implanted into the single crystal Si layer 104.

Thereafter, a gate oxide film 106 is formed on the surface of the single crystal Si layer 104 by a thermal oxidation method. Next, a polysilicon film is deposited on the entire surface including the gate oxide film 106, and the polysilicon film is patterned to form a gate electrode 107 on the gate oxide film.

Next, low concentration N-type impurity ions are implanted using the gate electrode 107 as a mask. Thereafter, a CVD (Chemical Vapor) is formed on the entire surface including the gate electrode 107.
By depositing a silicon oxide film by a Deposition method and etching the entire surface of the silicon oxide film, a sidewall 113 made of a silicon oxide film is formed on the side wall of the gate electrode 107.

Next, N-type impurity ions are implanted using the side wall 113 and the gate electrode 107 as a mask. Thereafter, the SOI substrate 101 is annealed to form a low-concentration N-type diffusion layer 115 and N-type diffusion layers 116 and 117 of source / drain regions in the single-crystal Si layer. Thus, the SOI structure fully depleted M
An OS transistor is formed. Fully depleted MOS transistors have various features such as being able to sufficiently suppress the short channel effect.

After that, the oxide film on the N-type diffusion layers 116 and 117 in the source / drain regions is removed, and the gate electrode 10 is removed.
7. A metal layer (not shown) is deposited on the entire surface including 7. Next, by subjecting the SOI substrate to a heat treatment, the single-crystal Si
By causing a silicide reaction between the layer and the gate electrode and the metal layer, a silicide layer (not shown) is formed on each of the N-type diffusion layers 116 and 117 and the gate electrode.

Next, an interlayer insulating film (not shown) is deposited on the entire surface including the gate electrode, and the interlayer insulating film is etched to form an N type diffusion layer 116,
A contact hole (not shown) located on each of the 117 is formed.

[0010]

In the above-mentioned conventional method for manufacturing a semiconductor device, the thickness of the single-crystal Si layer 104 is made extremely small in order to form a fully depleted MOS transistor. For this reason, if the silicide reaction on the diffusion layer in the source / drain region proceeds excessively, the single-crystal Si
All of the diffusion layers 116 and 117 in the layer 104 may be silicided. If the amount of over-etching in the etching for forming the contact hole is too large, the contact hole becomes
In some cases, the insulating film 103 may be penetrated through the layer 104. As described above, it is difficult to control the process of a fully depleted MOS transistor in which a single-crystal Si layer is formed thin. Therefore, it is difficult to manufacture a fully depleted SOI device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can easily manufacture a fully depleted transistor by easily controlling a process. It is in.

[0012]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises a supporting substrate,
A first step of preparing an SOI substrate having a first insulating film formed thereon and a single-crystal Si layer formed thereon, and a second step of forming a dummy gate insulating film on the surface of the single-crystal Si layer A third step of forming a dummy gate electrode on the dummy gate insulating film, a fourth step of implanting impurity ions into the single crystal Si layer using the dummy gate electrode as a mask, and annealing the single crystal Si layer Forming a diffusion layer of a source / drain region on a single-crystal Si layer, depositing a second insulating film on the entire surface including the dummy gate electrode, and polishing or etching back the second insulating film by CMP. A sixth step of exposing the upper surface of the dummy gate electrode, using the second insulating film as a mask, etching the dummy gate electrode and the dummy gate insulating film, and forming the single-crystal Si layer to a predetermined depth. A seventh step of in etching, an eighth step of forming a gate insulating film on the single crystal Si layer, and a ninth step of forming a gate electrode on the gate insulating film,
It is characterized by having.

According to the method of manufacturing a semiconductor device, even if the single crystal Si layer is formed relatively thick, the single crystal Si layer is etched to a predetermined depth in the seventh step using the second insulating film as a mask. By doing so, the thickness of the single crystal Si layer in the channel portion below the gate electrode can be reduced. Therefore, a fully depleted MOS transistor can be formed. In this transistor, a single crystal S
Since it is not necessary to reduce the thickness of the i-layer, process control is facilitated.

Further, in the method of manufacturing a semiconductor device according to the present invention, between the seventh step and the eighth step, the relative dielectric constant of the recessed portion formed in the single-crystal Si layer in the seventh step is higher than that of Si. It is possible to further include a step of forming a sidewall made of an insulating film having a low ratio.

A semiconductor device according to the present invention includes an SOI substrate having a support substrate, an insulating film formed thereon and a single crystal Si layer formed thereon, and a channel region formed in the single crystal Si layer. An upper concave portion, a sidewall formed on the inner side wall of the concave portion, made of an insulating film having a lower relative dielectric constant than Si, a gate insulating film formed on a bottom portion of the concave portion, and A gate electrode formed between the side walls; and a diffusion layer of a source / drain region formed on the single-crystal Si layer below the side wall of the gate electrode. And

According to the semiconductor device, the process control is easy, and a fully depleted transistor can be easily manufactured. In addition, the inner wall of the recess formed in the single crystal Si layer has S
Side walls made of an insulating film having a lower relative dielectric constant than i are formed, and a gate electrode is formed between the side walls and on the gate insulating film. Therefore, the capacitance between the gate electrode and the drain diffusion layer can be reduced.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 7 are sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

First, SO manufactured by the laminating method is used.
An I substrate 1 is prepared. The SOI substrate 1 includes a supporting substrate 2 made of single-crystal silicon, an insulating film 3 formed on the supporting substrate 2, and a single crystal S formed on the insulating film 3.
and an i-layer 4.

That is, a first silicon substrate (support substrate 2) having a first insulating film formed on its surface is prepared, and a second silicon substrate is formed on its surface.
A second silicon substrate (single-crystal Si layer 4) on which an insulating film has been formed is prepared. Next, the first insulating film and the second insulating film are bonded to each other to form an insulating film 3 made of the first and second insulating films formed on the support substrate 2 and a second insulating film formed on the insulating film 3. An SOI substrate 1 including two silicon substrates (single-crystal Si layer 4) is formed. Then, the thickness of the second silicon substrate is reduced to, for example, about 150 nm by polishing the back surface of the second silicon substrate.

Next, as shown in FIG.
A trench is formed on the entire surface including the inside of the trench.
A silicon oxide film is deposited by the VD method. Thereafter, the silicon oxide film existing on the single crystal Si layer 4 is removed by etch back or CMP (Chemical Mechanical Polishing) polishing. As a result, a silicon oxide film is buried in the trench, and an element isolation film 5 made of a silicon oxide film is formed in an element isolation region on the insulating film 3. next,
P-type impurities are ion-implanted into the single crystal Si layer 4.

Thereafter, a dummy gate oxide film 6a is formed on the surface of the single crystal Si layer 4 by a thermal oxidation method. Next, a polysilicon film is deposited on the entire surface including the dummy gate oxide film 6a by the CVD method, and the polysilicon film is patterned to form a dummy gate electrode 7a on the dummy gate oxide film.

Next, low concentration N-type impurity ions are implanted using the dummy gate electrode 7a as a mask. next,
A silicon oxide film is deposited on the entire surface including the dummy gate electrode 7a by the CVD method, and the entire surface of the silicon oxide film is etched to form a sidewall 13 made of the silicon oxide film on the side wall of the dummy gate electrode 7a. .

Thereafter, N-type impurity ions are implanted using the sidewall 13 and the dummy gate electrode 7a as a mask, and the single-crystal Si layer 4 is annealed. Thus, the low-concentration N-type diffusion layer 15 and the N-type diffusion layers 16 and 17 in the source / drain regions are formed in the single-crystal Si layer.

Next, the oxide film on the N-type diffusion layers 16 and 17 in the source / drain regions is removed, and the dummy gate electrode 7a is removed.
A metal layer (not shown) such as a Ti layer is deposited on the entire surface including the above. Next, heat treatment is performed on the SOI substrate to cause a silicide reaction between the single-crystal Si layer and the dummy gate electrode and the metal layer, thereby forming the N-type diffusion layers 16 and 1.
On each of the dummy gate electrode 7 and the dummy gate electrode 7a, a silicide layer (not shown) is formed.

Next, as shown in FIG. 2, a silicon oxide film 2 is formed on the entire surface including the dummy gate electrode 7a by CVD.
1 is thickly deposited, and the silicon oxide film 21 is polished by CMP or etched back to form a dummy gate electrode 7.
The upper surface of a is exposed.

Thereafter, as shown in FIG. 3, the dummy gate electrode 7a and the dummy gate oxide film 6a are removed by etching using the silicon oxide film 21 and the sidewalls 13 as a mask, and the single crystal Si layer 4 is etched to a predetermined depth. . Thereby, the thickness of the single-crystal Si layer 4 below the gate electrode 7b can be reduced to about 10 nm.

Next, as shown in FIG.
A gate oxide film 6b is formed on the surface of the substrate by a thermal oxidation method.

Thereafter, as shown in FIG. 5, a polysilicon film 22 doped with impurities is deposited on the entire surface including the silicon oxide film 21 by the CVD method. In this step, it is possible to deposit a polysilicon film which is not doped with an impurity. In this case, however, the polysilicon film is ion-implanted with impurity ions after the deposition or the polysilicon film is vapor-phase-diffused. It is preferable to introduce impurity ions into the silicon.

Next, as shown in FIG. 6, a gate electrode 7b made of a polysilicon film is formed between the side walls 13 and on the gate oxide film 6b by polishing or etching back the polysilicon film 22. Is done. Thus, a fully depleted MOS transistor having an SOI structure is formed. That is, single-crystal Si under the gate electrode
By etching the layer 4 to a predetermined depth, a single-crystal Si layer region under the gate electrode can be formed as shallow as about 10 nm, and as a result, the SOI structure of the fully depleted M
An OS transistor can be formed. In addition, fully depleted MO
The S transistor has various features such as being able to sufficiently suppress the short channel effect. Next, the gate electrode 7
An interlayer insulating film 23 made of a silicon oxide film or the like is deposited on the entire surface including b.

Next, as shown in FIG.
And by etching the silicon oxide film 21,
Contact holes 23a and 23b are formed on the N-type diffusion layers 16 and 17 in the source / drain regions, respectively. Thereafter, a wiring layer 25 is formed in the contact hole and on the interlayer insulating film.

According to the first embodiment, the single crystal S
Although the thickness of the i-layer 4 is relatively thick at about 150 nm, the single-crystal Si layer 4 is etched to a predetermined depth by using the silicon oxide film 21 and the sidewalls 13 as a mask in the process shown in FIG. Since the thickness of the single crystal Si layer in the channel portion below the gate electrode can be reduced, a fully depleted MOS transistor can be formed. In this transistor, it is not necessary to reduce the thickness of the single-crystal Si layer unlike a conventional semiconductor device, so that process control is facilitated. In other words, since the thickness of the single crystal Si layer is relatively large, even if the silicide reaction on the diffusion layer in the source / drain region progresses excessively, the portions of the diffusion layers 16 and 17 in the single crystal Si layer 4 will not change. Are not completely silicided. In addition, contact holes 23a, 23
Even if the amount of over-etching in the etching for forming 3b is too large, the contact hole is made of single-crystal Si.
It does not penetrate the layer 4 and reach the insulating film 3. Therefore, process control is easy, and a fully depleted transistor can be easily manufactured.

FIGS. 8 to 12 are sectional views showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

After performing the steps shown in FIGS. 1 to 3 in the first embodiment, as shown in FIG. 8, a silicon oxide film is deposited on the entire surface including the silicon oxide film 21 by the CVD method. By etching the entire surface of the silicon oxide film, the inner wall of the sidewall 13 and the low concentration diffusion layer 15 (that is, the inner wall of the concave portion formed in the single crystal Si layer 4)
Is formed with a sidewall 33 made of a silicon oxide film.

Next, as shown in FIG.
A gate oxide film 6b is formed on the surface of the substrate by a thermal oxidation method.

Thereafter, as shown in FIG. 10, a polysilicon film 22 doped with impurities is deposited on the entire surface including the silicon oxide film 21 by the CVD method. In this step, it is possible to deposit a polysilicon film which is not doped with an impurity. In this case, however, the polysilicon film is ion-implanted with impurity ions after the deposition or the polysilicon film is vapor-phase-diffused. It is preferable to introduce impurity ions into the silicon.

Next, as shown in FIG. 11, the polysilicon film 22 is polished by CMP or etched back.
A gate electrode 7b made of a polysilicon film is formed between the sidewalls 33 and on the gate oxide film 6b.
Thus, a fully depleted MOS transistor having an SOI structure is formed. That is, the single crystal S under the gate electrode
By etching the i-layer 4 to a predetermined depth, a single-crystal Si layer region under the gate electrode can be formed as shallow as about 10 nm. As a result, a fully depleted MOS transistor having an SOI structure can be formed. In addition, fully depleted M
The OS transistor has various features such as being able to sufficiently suppress the short channel effect. Next, an interlayer insulating film 23 made of a silicon oxide film or the like is deposited on the entire surface including the gate electrode 7b.

Thereafter, as shown in FIG. 12, the interlayer insulating film 23 and the silicon oxide film 21 are etched to form the contact holes 23a and the contact holes 23a located on the respective N-type diffusion layers 16 and 17 in the source / drain regions. 23b is formed. Thereafter, a wiring layer 25 is formed in the contact hole and on the interlayer insulating film.

In the second embodiment, the same effects as those in the first embodiment can be obtained. That is,
Since it is not necessary to reduce the thickness of the single crystal Si layer as in a conventional semiconductor device, process control is easy and a fully depleted transistor can be easily manufactured.

In the second embodiment, the sidewalls 33 made of a silicon oxide film having a lower dielectric constant than Si are formed on the sidewalls 13 and the inner side walls of the low concentration diffusion layer 15 in the step shown in FIG. The gate electrode 7b is formed between the side walls 33 and on the gate oxide film 6b. Therefore, the capacitance between the gate electrode 7b and the drain diffusion layer 17 can be reduced as compared with the first embodiment. Therefore, the operation speed of the transistor can be improved.

The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example,
Specific conditions for etching the single-crystal Si layer 4 using the silicon oxide film 21 and the sidewalls 13 as a mask can be selected from various appropriate ones depending on the thickness of the single-crystal Si layer 4 and the like. It is possible.

[0041]

As described above, according to the present invention, by using the second insulating film as a mask, the dummy gate electrode and the dummy gate insulating film are etched and the single-crystal Si layer is etched to a predetermined depth. The thickness of the single crystal Si layer in the channel portion below the electrode is reduced. Therefore, it is possible to provide a semiconductor device and a method of manufacturing the semiconductor device, in which process control is easy and a fully depleted transistor can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, illustrating a step subsequent to FIG. 1;

FIG. 3 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, illustrating a step subsequent to FIG. 2;

FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, which is a step subsequent to FIG. 3;

FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, which is a step subsequent to FIG. 4;

FIG. 6 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention, which illustrates a step subsequent to that of FIG. 5;

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, which is a step subsequent to FIG. 6;

FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention, which is a step subsequent to FIG. 8;

FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention, which is a step subsequent to FIG. 9;

FIG. 11 illustrates a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and is a cross-sectional view illustrating a step subsequent to FIG.

FIG. 12 is a sectional view illustrating the manufacturing method of the semiconductor device according to the second embodiment of the present invention, and showing a step subsequent to FIG. 11;

FIG. 13 is a sectional view showing a conventional fully depleted semiconductor device having an SOI structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,101 SOI substrate 2,102 Support substrate 3,103 Insulating film 4,104 Single-crystal Si layer 5,105 Element isolation film 6a Dummy gate oxide film 6b, 106 Gate oxide film 7a Dummy gate electrode 7b, 107 Gate electrode 8 Oxygen Implantation layer 9 oxygen ions 11 buried oxide insulating layer 13, 113 sidewall 15, 115 low-concentration N-type diffusion layer 16, 116 source diffusion layer 17, 117 drain diffusion layer 21 silicon oxide film 22 polysilicon film 23 interlayer insulating film 23a, 23b Contact hole 25 Wiring layer

Claims (3)

[Claims] An SOI having a support substrate, a first insulating film formed thereon, and a single-crystal Si layer formed thereon
A first step of preparing a substrate; a second step of forming a dummy gate insulating film on the surface of the single-crystal Si layer; a third step of forming a dummy gate electrode on the dummy gate insulating film; A fourth step of implanting impurity ions into the single-crystal Si layer as a mask, and annealing the single-crystal Si layer to obtain a single-crystal Si layer.
Forming a source / drain region diffusion layer in the layer; depositing a second insulating film on the entire surface including the dummy gate electrode;
A sixth step of exposing the upper surface of the dummy gate electrode by CMP polishing or etching back the second insulating film; and etching the dummy gate electrode and the dummy gate insulating film using the second insulating film as a mask, and etching the single-crystal Si. A seventh step of etching the layer to a predetermined depth, an eighth step of forming a gate insulating film on the single crystal Si layer, and a ninth step of forming a gate electrode on the gate insulating film. A method for manufacturing a semiconductor device. 2. Between the seventh step and the eighth step, a sidewall made of an insulating film having a relative dielectric constant lower than that of Si is formed on the inner side wall of the recess formed in the single-crystal Si layer in the seventh step. The method according to claim 1, further comprising a step. 3. An SOI substrate having a supporting substrate, an insulating film formed thereon, and a single-crystal Si layer formed thereon, a concave portion formed on the single-crystal Si layer and positioned on a channel region, and A sidewall formed of an insulating film having a lower dielectric constant than Si formed on the inner side wall of the recess, a gate insulating film formed on the bottom of the recess, and a sidewall formed on the gate insulating film; A semiconductor device comprising: a gate electrode formed therebetween; and a diffusion layer of a source / drain region formed in a single crystal Si layer and formed below a side wall of the gate electrode.