JPH0410746B2 - - Google Patents
Info
- Publication number
- JPH0410746B2 JPH0410746B2 JP60033817A JP3381785A JPH0410746B2 JP H0410746 B2 JPH0410746 B2 JP H0410746B2 JP 60033817 A JP60033817 A JP 60033817A JP 3381785 A JP3381785 A JP 3381785A JP H0410746 B2 JPH0410746 B2 JP H0410746B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- film
- polycrystalline silicon
- conductivity type
- silicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 4
- 238000002955 isolation Methods 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 239000005380 borophosphosilicate glass Substances 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- KCBJDDCXBCEDRU-UHFFFAOYSA-N 3,4-dihydro-2h-borole Chemical compound C1CB=CC1 KCBJDDCXBCEDRU-UHFFFAOYSA-N 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は相補型MOS半導体装置に関し、特に
半導体装置の素子分離領域の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary MOS semiconductor device, and more particularly to a method for forming an element isolation region of a semiconductor device.
相補型MOS（以下CMOSと略記する）半導体装
置においては、nMOSFET側に生じる寄生縦型
npnトランジスタ及びpMOSFETとnMOSFETの
間に生じる寄生の横型トランジスタにより寄生サ
イリスタが構成されることから、ラツチアツプが
発生する。第３図は従来のCMOS半導体装置の
断面図であるが、この欠点を防止するため、選択
酸化法を用いた従来例では、図示するようにｐウ
エル１０をはさんだｐ型領域（n+拡散層１１）
とｎ型領域（p+拡散層１２）をできるだけ離し
て配置する必要があつた。
In complementary MOS (hereinafter abbreviated as CMOS) semiconductor devices, parasitic vertical type that occurs on the nMOSFET side
Latch-up occurs because a parasitic thyristor is formed by the npn transistor and the parasitic lateral transistor that occurs between the pMOSFET and the nMOSFET. FIG. 3 is a cross-sectional view of a conventional CMOS semiconductor device. In order to prevent this drawback, in the conventional example using selective oxidation, a p-type region (n + diffusion Layer 11)
It was necessary to arrange the and n-type regions (p + diffusion layer 12) as far apart as possible.
一方、各導電型領域内に形成された素子間を分
離するに際しても、従来の選択酸化法を用いた場
合には、バーズ・ビークの発生により微細化が制
限される。このため、近年、半導体基板表面に溝
を形成し、これを絶縁膜で埋め込んで素子間分離
を行なう方法が提案されている。ところが、従来
述べられている溝分離法は、ウエル分離のために
必要とされる深い溝と、素子間分離のための浅く
広い溝に関して、それぞれ別個に論じられてお
り、同一半導体基板上に深さの異なる２種類の溝
を共に形成する方法に関しては知見がなかつた。 On the other hand, when conventional selective oxidation is used to isolate elements formed in each conductivity type region, miniaturization is restricted due to the occurrence of bird's beaks. Therefore, in recent years, a method has been proposed in which trenches are formed on the surface of a semiconductor substrate and the trenches are filled with an insulating film to isolate elements. However, in conventional trench isolation methods, the deep trenches required for well isolation and the shallow and wide trenches for element isolation are discussed separately. There is no knowledge regarding a method for forming two types of grooves with different widths.
CMOSにおいて、装置の微細化を一層進める
には、前記の２種類の分離溝を同一半導体基板上
に共に配置することが有効である。しかし、この
場合、次に示すような問題点がある。
In CMOS, in order to further advance the miniaturization of devices, it is effective to arrange the two types of separation trenches described above together on the same semiconductor substrate. However, in this case, there are problems as shown below.
すなわち、ウエル分離のために用いる溝はウエ
ルよりも深く形成する必要があり、この深い溝を
埋め込むためには被覆性の良好な堆積被膜を用い
ることが重要である。この要求を満たすものとし
て、従来は多結晶シリコンが用いられている。一
方、素子間分離のための浅い溝は一般に複雑な形
状を有し、かつ、比較的広い幅をもつため、この
材料を用いて前記の２種類の溝を同時に埋め込む
ことは工程上非常に困難であつた。 That is, the trenches used for well isolation must be formed deeper than the wells, and it is important to use a deposited film with good coverage to fill these deep trenches. Conventionally, polycrystalline silicon has been used as a material that satisfies this requirement. On the other hand, since shallow grooves for isolation between elements generally have a complex shape and a relatively wide width, it is extremely difficult to fill the two types of grooves at the same time using this material. It was hot.
本発明の目的は、上記のCMOS特有のラツチ
アツプを防止し、かつ高集積度を有するCMOS
半導体装置の製造方法を提供することにある。 The purpose of the present invention is to prevent the above-mentioned latch-up peculiar to CMOS, and to
An object of the present invention is to provide a method for manufacturing a semiconductor device.
本発明は、第１導電型の半導体基板上に多結晶
シリコン膜を堆積し、半導体基板に設けた第２導
電型領域との境界に沿つて多結晶シリコン膜及び
半導体基板をエツチングして深い溝を形成し、こ
の上にテトラエチルオルト珪酸を原材料とする絶
縁膜を堆積し、多結晶シリコン膜が露出するまで
除去することで深い溝を絶縁膜で埋設する。
The present invention deposits a polycrystalline silicon film on a semiconductor substrate of a first conductivity type, and etches the polycrystalline silicon film and the semiconductor substrate along the boundary with a second conductivity type region provided in the semiconductor substrate to form deep grooves. An insulating film made of tetraethylorthosilicate as a raw material is deposited thereon, and the deep trench is filled with the insulating film by removing the polycrystalline silicon film until it is exposed.
更に、第１導電型及び第２導電型領域の表面を
多結晶シリコンと共にエツチングして浅い溝を形
成し、この上にボロンリンガラスを堆積し、多結
晶シリコン膜が露出するまで除去することで浅い
溝をボロリンガラスで埋設する工程を備えてい
る。 Furthermore, the surfaces of the first conductivity type and second conductivity type regions are etched together with polycrystalline silicon to form shallow grooves, boron phosphorus glass is deposited thereon, and the polycrystalline silicon film is removed until it is exposed. It has a process of filling shallow trenches with boroline glass.
このように、半導体基板に深い溝と浅い溝を形
成し、テトラエチルオルト珪酸を原材料とする絶
縁膜及びボロンリンガラスを堆積しかつ同一の多
結晶シリコン膜をエツチングストツパに利用して
これらを除去することで、絶縁膜及びボロンリン
ガラスを深い溝と浅い溝に夫々選択的に埋設する
ことが可能となり、CMOS半導体装置に発生す
る寄生サイリスタの生成によるラツチアツプを防
止したCMOS半導体装置の製造が可能とされる。 In this way, deep trenches and shallow trenches are formed in a semiconductor substrate, an insulating film made of tetraethylorthosilicate and boron phosphorus glass are deposited, and the same polycrystalline silicon film is used as an etching stopper to remove these. This makes it possible to selectively embed insulating films and boron phosphorus glass in deep and shallow trenches, respectively, making it possible to manufacture CMOS semiconductor devices that prevent latch-up caused by the generation of parasitic thyristors that occur in CMOS semiconductor devices. It is said that
以下、図面を参照して本発明の実施例を説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.
第１実施例：
第１図は本発明のCMOS半導体装置の第１実
施例の概略断面図である。本実施例ではｎ型シリ
コン基板１の上にｐウエル１０を形成し、この中
にn+拡散層１１を設け、また、ｎ型シリコン基
板１内にp+拡散層１２を設け、さらにアイソレ
ーシヨンの目的でｐウエル１０とｎ型シリコン基
板１の境界領域に深い分離溝５を設け、さらに基
板１およびｐウエル１０の上面に形成された素子
間を分離するため浅い溝７を形成し、深い分離溝
５にはテトラエチルオルト珪酸を用いて成長した
酸化膜（以下、TEOS膜という）６で埋め、浅い
溝７はボロンリンガラス（以下、BPSGという）
８で埋めた構成となつている。First Embodiment: FIG. 1 is a schematic cross-sectional view of a first embodiment of a CMOS semiconductor device of the present invention. In this example, a p-well 10 is formed on an n-type silicon substrate 1, an n + diffusion layer 11 is provided in this, a p + diffusion layer 12 is provided in the n-type silicon substrate 1, and an isolator is further provided. A deep isolation groove 5 is provided in the boundary region between the p-well 10 and the n-type silicon substrate 1 for the purpose of separation, and a shallow groove 7 is further formed to isolate the elements formed on the upper surface of the substrate 1 and the p-well 10. The deep isolation groove 5 is filled with an oxide film 6 grown using tetraethylorthosilicate (hereinafter referred to as TEOS film), and the shallow groove 7 is filled with borophosphorus glass (hereinafter referred to as BPSG).
The structure is filled with 8 characters.
第２図ａ〜ｉは、本実施例の形成工程を示す断
面図である。 FIGS. 2a to 2i are cross-sectional views showing the forming steps of this embodiment.
第２図ａに示すように、ｎ型シリコン基板１を
熱酸化することにより基板１の表面上に二酸化シ
リコン膜２を形成し、化学気相成長法によつて多
結晶シリコン膜３を成長させた後、レジスト４を
パターニングする。 As shown in FIG. 2a, a silicon dioxide film 2 is formed on the surface of the substrate 1 by thermally oxidizing the n-type silicon substrate 1, and a polycrystalline silicon film 3 is grown by chemical vapor deposition. After that, the resist 4 is patterned.
次に、第２図ｂに示すように、通常の反応性イ
オンエツチング法により、前記レジストパターン
４をマスクとして、露出している多結晶シリコン
膜３及びｎ型シリコン基板１に深さ４ないし5μ
ｍの溝５を形成し、その後レジスト４を除去し、
熱酸化により溝５の内面及び基板表面上に二酸化
シリコン膜２を形成する。 Next, as shown in FIG. 2b, using the resist pattern 4 as a mask, the exposed polycrystalline silicon film 3 and n-type silicon substrate 1 are etched to a depth of 4 to 5 μm using a conventional reactive ion etching method.
m grooves 5 are formed, and then the resist 4 is removed,
A silicon dioxide film 2 is formed on the inner surface of the groove 5 and the surface of the substrate by thermal oxidation.
次に、第２図ｃに示すように、溝５内及び基板
表面上に化学気相成長法によりTEOS膜６を堆積
する。その後、通常のトリフルオルメタンを用い
る異方性エツチング（以下、RIEという）によ
り、基板表面上のTEOS膜６を選択的に除去し、
溝５内にのみTEOS膜６が埋め込まれた構造を得
る。 Next, as shown in FIG. 2c, a TEOS film 6 is deposited within the groove 5 and on the substrate surface by chemical vapor deposition. After that, the TEOS film 6 on the substrate surface is selectively removed by ordinary anisotropic etching (hereinafter referred to as RIE) using trifluoromethane.
A structure is obtained in which the TEOS film 6 is embedded only in the groove 5.
次に、第２図ｄに示すように、深い溝５で分離
された各導電型領域の素子間分離領域のみを露出
するようなレジストパターン４を形成する。その
後、レジストパターン４をマスクとして、露出し
ている多結晶シリコン３及びシリコン基板１に、
RIEにより深さ１〜1.5μｍ程度の浅い溝７を形成
する。次いでレジスト４を除去し、溝７の内面及
び基板表面上に熱酸化により二酸化シリコン膜２
を形成して第２図ｅに示す構造を得る。 Next, as shown in FIG. 2d, a resist pattern 4 is formed so as to expose only the element isolation regions of each conductivity type region separated by the deep grooves 5. After that, using the resist pattern 4 as a mask, the exposed polycrystalline silicon 3 and silicon substrate 1 are coated.
A shallow groove 7 having a depth of about 1 to 1.5 μm is formed by RIE. Next, the resist 4 is removed, and a silicon dioxide film 2 is formed on the inner surface of the groove 7 and the surface of the substrate by thermal oxidation.
is formed to obtain the structure shown in FIG. 2e.
次に、第２図ｆに示すように、浅い溝７及び基
板表面上にBPSG８を堆積した後、窒素ガス中で
アニールを行ない、このBPSG膜８をリフローす
る。その後、通常のRIEにより、基板表面上の
BPSG膜８を選択的に除去し、溝７内にのみ
BPSG膜が、また溝５内にTEOS膜が埋め込まれ
た構造第２図ｇを得る。次に、第２図ｈに示すよ
うに、基板表面上に残存する多結晶シリコン膜３
及び二酸化シリコン膜２を除去し、その後の熱酸
化により第２図ｉに示す構造が得られる。 Next, as shown in FIG. 2f, a BPSG film 8 is deposited on the shallow groove 7 and the surface of the substrate, and then annealed in nitrogen gas to reflow the BPSG film 8. After that, normal RIE is performed on the substrate surface.
BPSG film 8 is selectively removed and only inside the groove 7
A structure shown in FIG. 2g in which the BPSG film and the TEOS film are embedded in the groove 5 is obtained. Next, as shown in FIG. 2h, the polycrystalline silicon film 3 remaining on the substrate surface is
Then, the silicon dioxide film 2 is removed, and the structure shown in FIG. 2i is obtained by subsequent thermal oxidation.
以上説明したように、本発明は相補型MOS半
導体装置において必要とされるウエル分離のため
の深い溝と、素子間分離を行うための浅い溝を
夫々選択的に形成し、かつ同一の多結晶シリコン
膜をエツチングストツパに利用して各溝にテトラ
エチルオルト珪酸を原材料とする絶縁膜及びボロ
ンリンガラスを夫々埋設させるので、少ない工程
でウエル分離と素子間分離の各溝を形成すること
が可能となる。
As explained above, the present invention selectively forms deep trenches for well isolation and shallow trenches for element isolation, which are required in complementary MOS semiconductor devices, and uses the same polycrystalline Since the silicon film is used as an etching stopper and an insulating film made of tetraethylorthosilicate and boron phosphorus glass are buried in each groove, it is possible to form well isolation and element isolation grooves with fewer steps. becomes.
又、このウエル分離と素子間分離によつて、こ
れらの領域を従来に比べ大幅に縮小でき、
CMOS半導体装置の高密度、高集積化が実現で
きることは言うまでもない。 In addition, due to this well isolation and element isolation, these areas can be significantly reduced compared to conventional methods.
It goes without saying that high density and high integration of CMOS semiconductor devices can be achieved.
第１図は、本発明のCMOS半導体装置の第１
の実施例の縦断面図、第２図ａ〜ｉは、第１実施
例の形成工程断面図、第３図は従来例の断面図で
ある。
１……ｎ型シリコン基板、２……二酸化シリコ
ン膜、３……多結晶シリコン膜、４……レジス
ト、５……深い分離溝、６……TEOSによる酸化
膜、７……浅い分離溝、８……ボロンリンガラス
膜、９……窒化シリコン膜、１０……ｐウエル、
１１……n+拡散層、１２……p+拡散層。
FIG. 1 shows the first part of the CMOS semiconductor device of the present invention.
2A to 2I are sectional views of the forming process of the first embodiment, and FIG. 3 is a sectional view of the conventional example. DESCRIPTION OF SYMBOLS 1... N-type silicon substrate, 2... Silicon dioxide film, 3... Polycrystalline silicon film, 4... Resist, 5... Deep isolation trench, 6... Oxide film by TEOS, 7... Shallow isolation trench, 8...Boron phosphorus glass film, 9...Silicon nitride film, 10...P well,
11...n + diffusion layer, 12...p + diffusion layer.
Claims (1)
ル領域を有し、かつこれら半導体基板及びウエル
領域の表面に素子を形成してなる相補型MOS半
導体装置の製造方法において、前記半導体基板上
に多結晶シリコン膜を堆積する工程と、パターン
形成されたマスクを利用して前記第１導電型と第
２導電型領域の境界に沿つて前記多結晶シリコン
膜及び半導体基板をエツチングして半導体基板に
深い溝を形成する工程と、この深い溝の内面を含
む前記半導体基板上にテトラエチルオルト珪酸を
原材料とする絶縁膜を堆積する工程と、前記多結
晶シリコン膜の表面が露出するまで前記絶縁膜を
除去する工程と、パターン形成されたマスクを利
用して前記第１導電型及び第２導電型領域上の前
記多結晶シリコン膜及び半導体基板をエツチング
して前記半導体基板に浅い溝を形成する工程と、
この浅い溝を含む半導体基板上にボロンリンガラ
ス膜を堆積する工程と、このボロンリンガラス膜
を前記多結晶シリコン膜が露出するまで除去する
工程と、その後に前記多結晶シリコン膜を除去す
る工程とを含むことを特徴とする相補型MOS半
導体装置の製造方法。1. In a method for manufacturing a complementary MOS semiconductor device having a second conductivity type well region in a first conductivity type semiconductor substrate and forming elements on the surfaces of the semiconductor substrate and the well region, depositing a polycrystalline silicon film on the semiconductor substrate; and etching the polycrystalline silicon film and the semiconductor substrate along the boundary between the first conductivity type and second conductivity type regions using a patterned mask. forming a deep groove in the semiconductor substrate, depositing an insulating film made of tetraethylorthosilicate on the semiconductor substrate including the inner surface of the deep groove, and depositing the insulating film until the surface of the polycrystalline silicon film is exposed. and etching the polycrystalline silicon film and the semiconductor substrate on the first conductivity type and second conductivity type regions using a patterned mask to form a shallow groove in the semiconductor substrate. and,
A step of depositing a borophosphorus glass film on the semiconductor substrate including the shallow groove, a step of removing the borophosphorus glass film until the polycrystalline silicon film is exposed, and a step of removing the polycrystalline silicon film thereafter. A method for manufacturing a complementary MOS semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60033817A JPS61194767A (en) | 1985-02-22 | 1985-02-22 | Complementary type mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60033817A JPS61194767A (en) | 1985-02-22 | 1985-02-22 | Complementary type mos semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61194767A JPS61194767A (en) | 1986-08-29 |
| JPH0410746B2 true JPH0410746B2 (en) | 1992-02-26 |
Family
ID=12397029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60033817A Granted JPS61194767A (en) | 1985-02-22 | 1985-02-22 | Complementary type mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61194767A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07112006B2 (en) * | 1988-05-02 | 1995-11-29 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| DE3900769A1 (en) * | 1989-01-12 | 1990-08-09 | Fraunhofer Ges Forschung | INTEGRATED CIRCUIT WITH AT LEAST ONE N-CHANNEL FET AND AT LEAST ONE P-CHANNEL FET |
| JPH0779127B2 (en) * | 1989-12-27 | 1995-08-23 | 株式会社半導体プロセス研究所 | Method for manufacturing semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57113248A (en) * | 1980-12-29 | 1982-07-14 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5864044A (en) * | 1981-10-14 | 1983-04-16 | Toshiba Corp | Manufacture of semiconductor device |
| JPS58197841A (en) * | 1982-05-14 | 1983-11-17 | Toshiba Corp | Semiconductor device and its manufacture |
| JPS58220443A (en) * | 1982-06-16 | 1983-12-22 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5984572A (en) * | 1982-11-08 | 1984-05-16 | Nec Corp | Semiconductor device |
-
1985
- 1985-02-22 JP JP60033817A patent/JPS61194767A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57113248A (en) * | 1980-12-29 | 1982-07-14 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5864044A (en) * | 1981-10-14 | 1983-04-16 | Toshiba Corp | Manufacture of semiconductor device |
| JPS58197841A (en) * | 1982-05-14 | 1983-11-17 | Toshiba Corp | Semiconductor device and its manufacture |
| JPS58220443A (en) * | 1982-06-16 | 1983-12-22 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5984572A (en) * | 1982-11-08 | 1984-05-16 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61194767A (en) | 1986-08-29 |
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