JPH0779127B2 - Method for manufacturing semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device,
More specifically, TEOS (Tetra-Etyl-Ortho-Silicate,
The present invention relates to a method of depositing SiO ₂ by a CVD method of Si (OC ₂ H ₅ ) ₄ , alkoxysilane) -O ₃ reaction.

[Conventional technology]

As an element isolation technology, a Si ₃ N ₄ film is formed on a Si substrate, and the S
Selective oxidation of Si substrate using i ₃ N ₄ film as a mask
A selective oxidation (LOCOS) method for forming a SiO ₂ film is known.

However, according to this method, the edge of the field SiO ₂ film has a bird's beak shape and the element formation region is narrowed, which is not sufficient for the recent demand for high integration.

On the other hand, there is a method of forming a U groove or a V groove in a Si substrate and embedding an insulator in the groove to perform element isolation.
FIG. 5 is a diagram explaining this method.

That is, after selectively etching the Si substrate 42, for example, a SiO ₂ film 44 is deposited by a CVD method of a normal SiH ₄ -O ₂ reaction,
Then, for example, after applying a resist film 46 having the same etching rate characteristics as the SiO ₂ film to planarize the surface, Si
Etch back until the surface of the substrate 42 is exposed. In this way, element isolation can be performed by embedding an insulator such as the SiO ₂ film 44a only in the U groove and the V groove.

This method is effective for high integration because bird's beak does not occur.

[Problems to be Solved by the Invention]

However, according to the conventional method, it is embedded in the U groove or the V groove.
There is a possibility that a resist film 46 having the same etching rate as the SiO ₂ film 44 may be required, or the resist film 46 may contaminate the substrate.

In addition, in a semiconductor device having an SOI structure, there is a similar problem when embedding an insulator for element isolation.

The present invention has been made in view of such problems, utilizing the deposition characteristics of the SiO ₂ film of the TEOS-O ₃ reaction CVD method,
An object of the present invention is to provide a method for manufacturing a semiconductor device, which enables SiO ₂ to be easily embedded in a groove or a recess.

[Means for Solving the Problem and Its Action]

FIG. 2 is a characteristic diagram for explaining the principle of the method for manufacturing a semiconductor device according to the present invention, in which the horizontal axis represents ozone (O ₃ ) concentration (%) and the vertical axis represents deposition rate (Å / min). There is. The deposition conditions at this time were a substrate temperature of 400 ° C., a TEOS solution (source) temperature of 65 ° C., a saturated vapor pressure of 20 mmHg, and a carrier gas N ₂ valve flow rate of 3.5 SLM.

As shown in FIG. ₂ , SiO ₂ was formed by the TEOS-O ₃ reaction CVD method.
When the film is deposited, the difference in the SiO ₂ deposition rate between the underlying Si and the thermal SiO ₂ film gradually increases as the O ₃ concentration increases. For example, when the O ₃ concentration is about 2%, it is not so different, but when it is about 5%, 3 (Si): 2 (thermal SiO ₂ film)
The difference has widened to some extent.

Therefore, as shown in FIG. 1, there is a large difference in the film thickness of the CVD-SiO ₂ film 6 between the region directly deposited on the surface of the Si substrate 2 and the region directly deposited on the surface of the thermal SiO ₂ film 4. Will occur.

The present invention utilizes the fact that the deposition rate differs depending on the underlying layer, and the CVD using the thermal reaction of TEOS-O ₃ on the substrate in which the surface of the concave portion is the Si surface and the surface of the convex portion is the thermal SiO ₂ surface. Si by law
It is characterized in that O ₂ is deposited to fill the recess.

In addition, TEOS-O ₃ reaction SiO deposited using high concentration of O _3
2 has a characteristic of showing a gentle flow shape at the corners of the step, which is extremely convenient for filling the recess.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

(I) First Embodiment of the Present Invention FIG. 3 is a diagram illustrating a method of forming a MOS transistor by the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

First, the p-type Si substrate 8 is heat-treated, and the surface of the Si substrate is heated with Si.
An O ₂ film 10 is formed ((a) in the same figure).

Next, a resist film 12 is applied, and then the resist film is patterned ((b) in the same figure).

Next, using the resist film 12 as a mask, the thermal SiO ₂ film 10 is etched, and further, the surface of the Si substrate 8 is etched by anisotropic etching to form a groove 14 having a depth of about 1.5 μm. Figure (c)).

Next, a SiO ₂ film is deposited by the TEOS-O ₃ reaction. At this time, set the substrate temperature to 400 ° C and the O ₃ concentration to about 5%,
Process for about 0 minutes.

As shown in FIG. 2, the deposition rate at this time, the thermal SiO ₂
Approximately 800Å / min on the film 10 and approximately 1250Å / m on the Si substrate 8.
because it is in, together with the groove 14 is filled with SiO _2, the thermal SiO ₂
The SiO ₂ film 16 having a thickness of approximately 2.4 μm is deposited on the film 10 and the surface of the substrate becomes substantially flat (FIG. 7D).

Then, etching back is performed until the surface of the Si substrate 8 is exposed, so that the SiO ₂ 16a is completely embedded in the groove 14 (FIG. 8E).

Next, heat treatment is performed to form a gate SiO ₂ film 18, and further CVD
After the poly-Si film is formed by the method, the poly-Si film is patterned to form the gate electrode 20 ((f) in the figure).

Then, phosphorus (P) is implanted using the gate electrode 20 as a mask to form the source / drain 22 and 24, and the PSG film 26 is formed thereon.
To form an n-channel MOS according to the embodiment of the present invention.
The transistor is completed ((g) in the same figure).

(Ii) Second Embodiment of the Present Invention FIG. 4 is a diagram for explaining a method of embedding SiO ₂ for element isolation of an SOI structure by a method of manufacturing a semiconductor device according to a second embodiment of the present invention. is there.

First, the p-type Si substrate 28 is heat-treated, and a thermal Si is applied to the surface of the Si substrate.
An O ₂ film 30 is formed, and a poly-Si film having a thickness of about 1 μm is further formed on the SiO ₂ film 30, and then laser light is irradiated to the poly-Si film 30.
The film is recrystallized to form a recrystallized Si film 32 ((a) in the figure).

It should be noted that single crystal Si is formed on an insulating substrate such as sapphire (Al ₂ O ₃ ).
This step is not necessary when using a SOI substrate having a film formed thereon.

Next, heat treatment is applied to the surface of the recrystallized Si film 32, and several hundred Å of thermal SiO ₂
A film 34 is formed ((b) of the same figure).

Then, a resist film 36 is applied, and then the resist film is patterned ((c) in the same figure).

Next, the thermal SiO ₂ film 34 is etched by using the resist film 36 as a mask, and then recrystallized by anisotropic etching.
The Si film 32 is etched to form an opening 38 (FIG. 3D).

Next, a SiO ₂ film is deposited by the TEOS-O ₃ reaction. At this time, set the substrate temperature to 400 ° C and the O ₃ concentration to about 5%,
Process for about 0 minutes.

As shown in FIG. 2, the deposition rate at this time, the thermal SiO ₂
Approximately 800Å / min on the film 10 and approximately 1250Å / m on the Si substrate 8.
Since it is in, the inside of the opening 38 is filled with SiO ₂ and heat
A SiO ₂ film 40 having a thickness of about 1.6 μm is deposited on the SiO ₂ film 34,
It becomes almost flat on the surface of the substrate ((e) in the figure).

Then, etching back is performed until the surface of the recrystallized Si film 32 is exposed, so that the SiO ₂ 40a is completely embedded in the opening 38 ((f) in the figure). In this way, a flat substrate in which the element isolation SiO ₂ is embedded is obtained.

After this, the recrystallized Si film is
When MOS transistors and the like are formed in 32, a semiconductor integrated circuit device having a flat structure with complete isolation between elements is completed.

In each of the above embodiments, the case of applying to element isolation has been described, but it is also possible to appropriately apply to the case of flattening the unevenness generated in the process of the multilayer wiring structure.

〔The invention's effect〕

As described above, according to the present invention, the fact that the deposition rate of CVD-SiO _{2 in} the TEOS-O ₃ reaction varies depending on the substrate depending on whether the substrate is thermal SiO ₂ or Si At the same time as filling the inter-element isolation trenches such as the U-groove and the V-groove provided on the substrate surface, the substrate surface can be easily flattened. Similarly, the surface of the substrate can be easily flattened at the same time when the elements in the element formation region of the SOI structure are separated.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the manufacturing method of the present invention, FIG. 2 is a characteristic diagram for explaining the principle of the present invention, FIG. 3 is a diagram for explaining the first embodiment of the present invention, and FIG. FIG. 5 is an explanatory diagram of a second embodiment of the present invention, and FIG. 5 is an explanatory diagram of a manufacturing method according to a conventional example. (Explanation of symbols) 2,8,28 …… Si substrate, 4,10,30,34 …… Thermal SiO ₂ film, 6,16,16
a, 40,40a …… CVD-SiO ₂ film, 12,36 …… Resist film, 14…
… Groove, 18 …… Gate SiO ₂ film, 20 …… Gate electrode, 22,24
...... Source / drain, 32 …… Recrystallized Si film, 38 …… Opening.

Claims (3)

[Claims] 1. A concave surface is a Si surface and a convex surface is heat.
A method of manufacturing a semiconductor device, characterized in that SiO ₂ is deposited on a substrate, which is an SiO ₂ surface, by a TEOS-O ₃ reaction CVD method to fill the recess. Wherein the steps of forming a thermal SiO ₂ film on the Si substrate, the thermal SiO ₂ film and the Si substrate is patterned in the same pattern, opening the thermal SiO ₂ film, and a groove on the Si substrate And a method of manufacturing a semiconductor device, characterized in that SiO ₂ is deposited by a CVD method of TEOS-O ₃ reaction to fill the groove. 3. A step of forming a Si film on an insulating substrate, or a step of forming a Si film after forming an insulating film on a substrate, a step of forming a thermal SiO ₂ film on the surface of the Si film, the thermal SiO ₂ layer and the Si film is patterned in the same pattern SiO, open the thermal SiO ₂ membrane and forming an opening through the Si film by CVD of TEOS-O ₃ reaction _{2. A} method for manufacturing a semiconductor device, comprising depositing ₂ to fill the opening.