JP3539483B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an element isolation method using a shallow trench isolation (hereinafter, abbreviated as “STI”) method.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in manufacturing a semiconductor device, a LOCOS (Local Oxidation of Silicon) method has been widely used as an element isolation method. However, with the miniaturization of the processing dimensions, problems such as bird's beak have arisen in the LOCOS method using thermal oxidation.
[0003]
Then, as a means for solving the problem of the LOCOS method, the STI method has been proposed. In the STI method, an element isolation region is formed by forming a groove called a trench in a silicon substrate, embedding an insulating film, and then removing an insulating film other than the insulating film embedded in the trench by using a CMP method. I do. Since the insulating film can be formed by a plasma CVD method or the like as compared with the LOCOS method, the number of heat steps can be reduced, so that problems such as a bird's beak can be greatly improved.
[0004]
[Problems to be solved by the invention]
However, there is a problem unique to the STI method. In the LOCOS method, thermal oxidation is used, so that the surface irregularities after element isolation formation have a relatively gentle shape, whereas in the STI method, the end of element isolation after polishing of the insulating film by the CMP method. The portion has a shape substantially perpendicular to the substrate. As a result, in forming the gate electrode in a later step, as shown in FIG. 4, problems such as constriction of the pattern in photolithography and remaining polysilicon 25 in etching the gate electrode occur. FIG. 4 is a view for explaining the problem of the prior art, in which reference numeral 21 denotes a silicon substrate, 22 denotes a shallow trench isolation (STI) region, 23 denotes a gate insulating film, and 24 denotes a gate electrode.
[0005]
To cope with this problem, for example, as disclosed in Japanese Patent Application Laid-Open No. Hei 10-144781, a method of preventing a step in the STI region by using an SiN film as a CMP stopper at the time of forming the STI region, or removing a protrusion region in the STI region by etch-back. There are ways to do that.
[0006]
Hereinafter, the above method will be described with reference to FIG. FIG. 5 is a process chart for forming a conventional shallow trench isolation region.
[0007]
First, as shown in FIG. 5A, a first silicon nitride film 12, a first silicon oxide film 13, a second silicon nitride film 14, and a second silicon nitride film 12 are formed on a silicon substrate 11 by a CVD method. An oxide film 15 is formed sequentially. Next, a resist film (not shown) having an opening in a region where a trench is to be formed is formed by using a lithography technique. Next, as shown in FIG. 5B, anisotropic reaching from the surface of the second silicon oxide film 15 to the inside of the silicon substrate 11 by RIE using a resist film (not shown) as a mask. Etching is performed to form trench portion 11A.
[0008]
Next, as shown in FIG. 5C, after removing the resist film (not shown), a buried oxide film (third silicon oxide film 16) and a recess formed when the CMP method is performed by the CVD method. A formation suppression film (third silicon nitride film 17) is formed.
[0009]
Next, as shown in FIG. 5D, the third silicon nitride film 17 is polished by the CMP method, and the polishing is stopped when the surface of the second silicon nitride film 14 is exposed. Next, as shown in FIG. 5E, the third silicon nitride film 17 and the second silicon nitride film 14 are removed by wet etching. Next, as shown in FIG. 5F, the first silicon oxide film 13 is removed by RIE, and the height of the projection 16A made of the third silicon oxide film 16 is reduced. Thereafter, as shown in FIG. 5G, the first silicon nitride film 12 is removed by wet etching, and the surface of the silicon substrate 11 is exposed.
[0010]
However, there is a problem that the number of steps is extremely increased, that is, the cost is increased, for example, a stopper film of a CMP and an etch-back step is laminated in multiple layers, and further a removal step for each film type is required. .
[0011]
[Means for Solving the Problems]
Method of manufacturing a semi-conductor device of the present invention, the semiconductor substrate, after depositing a polishing stopper film, a photoresist is applied to the polishing stopper film, a step for exposing the region where the element isolation region of the photoresist ,
Using the photoresist as an etching mask, removing the polishing stopper film by dry etching, and further forming a groove of a predetermined depth in the semiconductor substrate;
After removing the photoresist, the first insulating film having a thickness corresponding to the depth of the groove and an etching rate of the first insulating film that can be etched in the same etching step as the first insulating film so as to fill the groove . Sequentially depositing a high second insulating film;
Polishing the first insulating film and the second insulating film using a CMP method until the surface of the polishing stopper film is exposed;
Forming a device isolation region by etching and removing the first insulating film and the second insulating film using the same etching agent after removing the polishing stopper film. Is what you do.
[0012]
Further, in the method of manufacturing a semiconductor device according to the present invention, it is preferable that the first insulating film is a USG film, the second insulating film is an LTO film, and hydrofluoric acid is used as the etching agent.
[0013]
Further, it is preferable that the method of manufacturing a semiconductor device according to the present invention is performed by controlling a wet etching rate of the LTO film by controlling an annealing temperature at the time of annealing the LTO film.
[0014]
Further, it is preferable that the etching of the first insulating film and the second insulating film is performed with hydrofluoric acid after removing the polishing stopper film with phosphoric acid .
[0015]
It is preferable that a silicon nitride film is used as the polishing stopper film, and a silicon oxide film is formed between the silicon nitride film and the semiconductor substrate.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail based on an embodiment.
[0017]
FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a shallow trench element isolation region when the present invention is used after forming a gate electrode, and FIG. 3 is an LTO annealing temperature and etching. It is a figure showing the relation with a rate. In the figure, 1 is a silicon substrate, 2 is a pad oxide film, 3 is a silicon nitride film, 4 is a resist pattern, 5 is a groove, 6 is a silicon oxide film, 7 is a USG film, 8 is an LTO film, 9 is a gate oxide film. Reference numeral 10 denotes a gate electrode.
[0018]
Hereinafter, a manufacturing process of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.
[0019]
First, as shown in FIG. 1A, a pad oxide film 2 and a silicon nitride film 3 are formed on a silicon substrate 1 by a thermal oxidation method and a CVD method to a thickness of 14 nm and 160 nm, respectively.
[0020]
Next, as shown in FIG. 1B, the pad oxide film 2 and the silicon nitride film 3 are etched by a dry etching technique using a resist pattern 4 as a mask using a photolithography technique as an element isolation pattern. Then, a groove 5 having a predetermined depth is formed. Here, the depth of the groove 5 is 350 nm. Note that it is desirable to process the tapered shape to some extent in consideration of the burying characteristics of the insulating film.
[0021]
Next, as shown in FIG. 1 (c), after removing the resist pattern 4, in order to prevent the occurrence of stress defects in the silicon substrate 1 from the buried oxide film in the trench 5, the film thickness is reduced by a thermal oxidation method. Forms a silicon oxide film 6 of about 30 nm.
[0022]
Next, as shown in FIG. 1D, a USG (Undoped Silicate Glass) film 7 containing no impurity is buried in the groove 5. In element isolation, an insulating film containing impurities deteriorates transistor characteristics. Therefore, it is preferable to use an insulating film containing no impurities. The USG film 7 is formed by, for example, a CVD method using a high-density plasma (hereinafter, referred to as “HDP”) device. At this time, the deposited film thickness of the USG film 7 is set to be equivalent to the groove depth. In the case of the present embodiment, it is 350 nm. After the formation of the USG film 7, annealing at about 1000 ° C. may be performed to densify the USG film 7. Next, an LTO (Low Temperature Oxide) film 8 is formed. The LTO film 8 is formed by a plasma CVD method, and the film thickness is set to 250 nm in the present embodiment although the appropriate value varies depending on the next CMP process. It is also effective to perform annealing for the purpose of controlling the wet etching rate of the LTO film 8 after the formation of the LTO film 8 in consideration of the film loss of the insulating film due to cleaning in the subsequent steps. Performs annealing at 750 ° C. for 1 hour. Until the gate electrode is formed, wet etching (cleaning step) equivalent to 200 to 500 ° in terms of a USG film is performed. At this time, it is necessary to control an etching rate difference in order to completely remove the LTO film 8 and to remove a protrusion in the STI region caused by an etching rate higher than that of the USG film 7. In this embodiment, the difference between the etching rates of the stacked buried films (USG film 7 and LTO film 8) is 3 to 10 times that of the lower insulating film (USG film 7) in the upper insulating film (LTO film 8). Is desirable. However, an appropriate difference in the etching rate is different depending on the remaining film in the buried portion after the later-described CMP process. Therefore, the difference in the etching rate between the stacked buried films does not restrict the present invention.
[0023]
Next, as shown in FIG. 1E, the LTO film 8 and the USG film 7 other than the groove buried portion are removed by a CMP process using the silicon nitride film 3 as a stopper. At this time, the remaining insulating film inside the trench has a thickness of 350 nm for the USG film 7 and 20 to 150 nm for the LTO film 8. When the buried film in the trench is formed by a single layer of the USG film, the remaining film becomes 370 to 500 nm, and this variation makes it difficult to reduce the step in the STI region.
[0024]
Next, as shown in FIG. 1F, the silicon nitride film 3 and the pad oxide film 2 are sequentially removed by wet etching. Phosphoric acid whose temperature is controlled to about 150 ° C. is used for removing the silicon nitride film 3, and hydrofluoric acid at room temperature is used for removing the oxide film. Next, the USG film 6 and the LTO film 7 are removed in a single step up to the silicon substrate surface by performing wet etching with the same etchant and hydrofluoric acid.
[0025]
Next, as shown in FIG. 1G, the STI shape when the gate oxide film 9 and the gate electrode 10 are formed through steps such as ion implantation into the silicon substrate 1 and cleaning is shown. In this embodiment, the gate oxide film 9 is formed to have a thickness of 32 nm by thermal oxidation, and the gate electrode 10 is formed to have a thickness of 200 nm of polysilicon by the LP-CVD method. The thickness of the STI region is reduced by the cleaning process such as the HF process after the STI-CMP process until the gate electrode forming process. Here, since the STI region is a laminated film of the LTO film 7 and the USG film, the etching rate with hydrofluoric acid is reduced faster in the LTO film, and after the LTO film is completely removed, that is, the surface of the USG film 7 Is exposed, the etching rate decreases, so that the remaining film variation of the insulating film inside the trench after the above-described STI-CMP process is reduced, and the step in the STI region is controlled to be flatter and smaller. It becomes possible. As a result, as shown in FIG. 2, the problem of the prior art, such as the residual etching at the time of processing the gate electrode due to the step in the STI region, is solved.
[0026]
Further, in the process shown in FIG. 1, the amount of hydrofluoric acid cleaning and the like in the process from the STI-CMP process to the formation of the gate oxide film varies, but for example, the annealing in the LTO film 8 as shown in FIG. A desired etching rate can be obtained by controlling the temperature of the heat treatment after the formation of the LTO film 8 using the relationship between the temperature and the etching rate.
[0027]
【The invention's effect】
As described in detail above, after depositing a polishing stopper film on a semiconductor substrate of the present invention, a photoresist is applied on the polishing stopper film, and a region to be an element isolation region of the photoresist is opened. Removing the polishing stopper film by dry etching using the photoresist as an etching mask, further forming a groove having a predetermined depth in the semiconductor substrate, and removing the photoresist. Sequentially depositing a first insulating film and a second insulating film which can be etched in the same etching step as the first insulating film and has a high etching rate so as to bury the groove, and the polishing stopper film Polishing the first insulating film and the second insulating film using a CMP method until the surface is exposed; and removing the polishing stopper film, Forming a device isolation region by etching and removing the first insulating film and the second insulating film using a etching agent. In order to eliminate the difficulty of processing the gate electrode caused by the step in the STI region, which has been a problem in the conventional method in the STI region type in the CMP process, without significantly changing the existing STI region forming process. In particular, an increase in the number of steps becomes almost unnecessary, and it is possible to not only improve the yield of the semiconductor device, that is, not only reduce the cost, but also cope with further miniaturization of element isolation, and it is also possible to achieve high integration of the semiconductor device. .
[0028]
Further, in addition to the above configuration of the present invention, the first insulating film is a USG film, the second insulating film is an LTO film, and hydrofluoric acid is used as the etching agent. By using the method for manufacturing a semiconductor device, the first insulating film and the second insulating film can be etched while maintaining an appropriate etching rate difference in a single wet etching step, and the step in the STI region is reduced. Can be.
[0029]
Further, in addition to the above structure, the present invention provides a method for manufacturing a semiconductor device, wherein the wet etching rate of the LTO film is controlled by controlling an annealing temperature when annealing the LTO film. Thereby, the step in the STI region with respect to the surface of the semiconductor substrate can be further reduced.
[0030]
Further, in addition to the above structure of the present invention, the steps are simplified by using a method of manufacturing a semiconductor device, wherein the wet etching is performed simultaneously with cleaning of an element formed on the semiconductor substrate. can do.
[0031]
Further, in the semiconductor device according to the present invention, in addition to the above configuration, a silicon nitride film is used as the polishing stopper film, and a silicon oxide film is formed between the silicon nitride film and the semiconductor substrate. By using the manufacturing method, polishing can be stopped more reliably.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a shallow trench element isolation region when the present invention is used after forming a gate electrode.
FIG. 3 is a diagram showing a relationship between an annealing temperature of LTO and an etching rate.
FIG. 4 is a diagram for explaining a problem of forming a conventional shallow trench element isolation region.
FIG. 5 is a process chart of forming a conventional shallow trench element isolation region.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 silicon substrate 2 pad oxide film 3 silicon nitride film 4 resist pattern 5 groove 6 silicon oxide film 7 USG film 8 LTO film 9 gate oxide film 10 gate electrode

Claims (5)

After depositing a polishing stopper film on the semiconductor substrate, applying a photoresist on the polishing stopper film, opening a region to be an element isolation region of the photoresist,
Using the photoresist as an etching mask, removing the polishing stopper film by dry etching, and further forming a groove of a predetermined depth in the semiconductor substrate;
After removing the photoresist, the first insulating film having a thickness corresponding to the depth of the groove and an etching rate of the first insulating film that can be etched in the same etching step as the first insulating film so as to fill the groove . Sequentially depositing a high second insulating film;
Polishing the first insulating film and the second insulating film using a CMP method until the surface of the polishing stopper film is exposed;
Forming a device isolation region by etching and removing the first insulating film and the second insulating film using the same etching agent after removing the polishing stopper film. To manufacture a semiconductor device. 2. The semiconductor device according to claim 1, wherein the first insulating film is a USG film, the second insulating film is an LTO film, and hydrofluoric acid is used as the etching agent. 3. Method. 3. The method according to claim 2, wherein the wet etching rate of the LTO film is controlled by controlling an annealing temperature when the LTO film is annealed. 5. The semiconductor device according to claim 1, wherein the etching of the first insulating film and the second insulating film is performed with hydrofluoric acid after removing the polishing stopper film with phosphoric acid . Production method. 5. The semiconductor device according to claim 1, wherein a silicon nitride film is used as said polishing stopper film, and a silicon oxide film is formed between said silicon nitride film and said semiconductor substrate. Manufacturing method.

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