CN101944483A - Method for enhancing anti-etching capacity of photoresist - Google Patents
Method for enhancing anti-etching capacity of photoresist Download PDFInfo
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- CN101944483A CN101944483A CN2010102505252A CN201010250525A CN101944483A CN 101944483 A CN101944483 A CN 101944483A CN 2010102505252 A CN2010102505252 A CN 2010102505252A CN 201010250525 A CN201010250525 A CN 201010250525A CN 101944483 A CN101944483 A CN 101944483A
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- silicon dioxide
- photoresist
- etching
- low temperature
- antireflective coating
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Abstract
The invention provides a method for enhancing the anti-etching capacity of photoresist, which is characterized by utilizing a low temperature silica depositing (LTO) technique, depositing film silica on the photoresist and the outside surface of a bottom anti-reflective coating after finishing the dry etching on the bottom anti-reflective coating and then carrying out dry back-etching operation, thus forming a silica protecting sidewall at the bottom of the sidewall of an etched pattern and improving the whole anti-etching capacity of the material.
Description
Technical field
The present invention relates to field of IC technique, particularly a kind of method that improves the anti-etching ability of photoresist.
Background technology
Photoetching technique is followed the continuous progress of integrated circuit fabrication process, constantly dwindling of live width, it is more and more littler that the area of semiconductor device is just becoming, and semi-conductive layout develops into the integrated circuit of integrating high-density multifunction from common simple function discrete device; By initial IC (integrated circuit) subsequently to LSI (large scale integrated circuit), VLSI (very lagre scale integrated circuit (VLSIC)), until the ULSI of today (ultra large scale integrated circuit), the area of device further dwindles, function is powerful more comprehensively.Consider the complexity of technique research and development, the restriction of chronicity and high cost or the like unfavorable factor, how on the basis of prior art level, further to improve the integration density of device, dwindle area of chip, as much as possiblely on same piece of silicon chip obtain effective chip-count, thereby the raising overall interests will more and more be subjected to the chip designer, the attention of manufacturer.Wherein photoetching process is just being undertaken crucial effect, and resolution and alignment precision promptly are the most important things wherein for photoetching technique.
Resolution: the photoetching technique of using in the semiconductor production is mainly based on the diffraction principle of optics.The diffraction of optics is light by the opaque body edge, passes slit or produce deviation and some bright band parallel to each other and blanking bars occur when drawing the surface reflection that parallel lines is arranged.When light passes through mask, owing to be subjected to the influence of mask plate patterns, make light generation deviation, thereby produce the different diffraction progression of quantity, basic calculating worker formula according to the size of mask plate patterns:
P*Sin α=n* λ (formula 1)
P is the summation of the width of the transparent region of figure and opaque section; α is an angle of diffraction; λ is the wavelength that mask aligner uses; N promptly is a diffraction progression.
According to numerical aperture, the notion of resolution and computing formula:
NA=N*Sin α (formula 2)
R=K1* λ/NA (formula 3)
NA (Numerical Aperture) is the important sign of photoetching machine lens ability, the high more resolution R that it brings is high more for numerical value, K1 is the coefficient factor, ability with technology, the wavelength of equipment, the basic parameter of numerical aperture etc. is relevant, and N is the refractive index of medium between optical lens and the silicon chip, and the numerical aperture of the big more gained of refractive index is also high more.Usually the medium of dry lithography technology is an air, thus the size of numerical aperture only to catch the angle of diffraction relevant with maximum.Catch the angle of diffraction when numerical aperture can obtain maximum by formula 2 when certain definite value, bring formula 1 thus into and obtain the diffraction progression that to be collected by camera lens.The diffraction progression of collecting is many more, and the degree true to nature of figure is high more, and the spatial image contrast that obtains thus also can improve greatly.Spatial image is absorbed by light-sensitive material subsequently, by developing to picture.Along with the introducing of the technology of immersion exposure, numerical aperture has broken through traditional notion, and this has promoted the performance of resolution greatly.
Except the lifting of above-mentioned hardware device aspect, the thickness that reduces photoresist also is the method that can directly improve the technology performance.Through a large amount of experiments, the design configuration size of semiconductor technology and the proportionate relationship between the photoresist thickness are roughly 1: 3 at present, but variation along with the lifting of figure complexity and material, technology, this thickness is to be not enough to satisfied demand of producing, can produce many technological problemses thus, this also is one of industry problem of having to pay attention to.
Summary of the invention
The present invention proposes a kind of method that improves the anti-etching ability of photoresist, can effectively improve the anti-etching ability of photoresist.
In order to achieve the above object, the present invention proposes a kind of method that improves the anti-etching ability of photoresist, comprises the following steps:
Semi-conductive substrate is provided;
On described Semiconductor substrate, be coated with bottom antireflective coating;
On described bottom antireflective coating, be coated with photoresist;
Described photoresist is exposed, develops, the exposed portions serve bottom antireflective coating;
The described bottom antireflective coating that exposes is carried out etching, until exposing described Semiconductor substrate;
Utilize low temperature deposition silicon dioxide technology, at said structure outer surface deposition silicon dioxide film;
Described silica membrane is carried out dry back carve etching operation, form silicon dioxide protection side wall.
Further, the deposition temperature of described low temperature deposition silicon dioxide technology is 100～200 degree.
Further, the deposition temperature of described low temperature deposition silicon dioxide technology is 150 degree.
Further, the silica membrane thickness of described low temperature deposition silicon dioxide technology institute deposit is 1 nanometer～1000 nanometers.
Further, the silica membrane thickness of described low temperature deposition silicon dioxide technology institute deposit is 50 nanometers.
The method of the anti-etching ability of raising photoresist that the present invention proposes; be characterized in utilizing low temperature deposition silicon dioxide (LTO) technology; after finishing the bottom antireflective coating dry etching; at photoresist and bottom antireflective coating outer surface deposition film silicon dioxide; carry out dry back subsequently and carve operation; and then at litho pattern sidewall bottom formation silica protection abutment wall, and then improve the anti-etching ability of material monolithic.
Description of drawings
Figure 1 shows that the structural representation behind coating bottom antireflective coating and the photoresist;
Figure 2 shows that the structural representation behind exposure, development, the etching bottom antireflective coating;
Figure 3 shows that the structural representation behind the low temperature deposition silicon dioxide;
Figure 4 shows that carrying out dry back carves etching operation, forms the structural representation of silicon dioxide protection side wall.
Embodiment
In order more to understand technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
Please refer to Fig. 1～Fig. 4, the present invention proposes a kind of method that improves the anti-etching ability of photoresist, comprises the following steps:
Coating bottom antireflective coating 200 on described Semiconductor substrate 100;
Described photoresist 300 is exposed, develops, exposed portions serve bottom antireflective coating 200;
The described bottom antireflective coating that exposes 200 is carried out etching, until exposing described Semiconductor substrate 100;
Utilize low temperature deposition silicon dioxide technology, at said structure outer surface deposition silicon dioxide film 400;
Described silica membrane 400 is carried out dry back carve etching operation, form silicon dioxide protection side wall 500.
Further, the deposition temperature of described low temperature deposition silicon dioxide technology is 100～200 degree, and the silica membrane thickness of described low temperature deposition silicon dioxide technology institute deposit is 1 nanometer～1000 nanometers.
The preferred embodiment according to the present invention, the deposition temperature of described low temperature deposition silicon dioxide technology are 150 degree, and the silica membrane thickness of described low temperature deposition silicon dioxide technology institute deposit is 50 nanometers.
In sum; the present invention proposes a kind of method that improves the anti-etching ability of photoresist; be characterized in utilizing low temperature deposition silicon dioxide (LTO) technology; after finishing the bottom antireflective coating dry etching; at photoresist and bottom antireflective coating outer surface deposition film silicon dioxide; carry out dry back subsequently and carve operation, and then form silica protection abutment wall, and then improve the anti-etching ability of material monolithic in litho pattern sidewall bottom.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (5)
1. a method that improves the anti-etching ability of photoresist is characterized in that, comprises the following steps:
Semi-conductive substrate is provided;
On described Semiconductor substrate, be coated with bottom antireflective coating;
On described bottom antireflective coating, be coated with photoresist;
Described photoresist is exposed, develops, the exposed portions serve bottom antireflective coating;
The described bottom antireflective coating that exposes is carried out etching, until exposing described Semiconductor substrate;
Utilize low temperature deposition silicon dioxide technology, at said structure outer surface deposition silicon dioxide film;
Described silica membrane is carried out dry back carve etching operation, form silicon dioxide protection side wall.
2. the method for the anti-etching ability of raising photoresist according to claim 1 is characterized in that, the deposition temperature of described low temperature deposition silicon dioxide technology is 100～200 degree.
3. the method for the anti-etching ability of raising photoresist according to claim 2 is characterized in that, the deposition temperature of described low temperature deposition silicon dioxide technology is 150 degree.
4. the method for the anti-etching ability of raising photoresist according to claim 1 is characterized in that, the silica membrane thickness of described low temperature deposition silicon dioxide technology institute deposit is 1 nanometer～1000 nanometers.
5. the method for the anti-etching ability of raising photoresist according to claim 4 is characterized in that, the silica membrane thickness of described low temperature deposition silicon dioxide technology institute deposit is 50 nanometers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102505252A CN101944483A (en) | 2010-08-11 | 2010-08-11 | Method for enhancing anti-etching capacity of photoresist |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102505252A CN101944483A (en) | 2010-08-11 | 2010-08-11 | Method for enhancing anti-etching capacity of photoresist |
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| CN101944483A true CN101944483A (en) | 2011-01-12 |
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| CN2010102505252A Pending CN101944483A (en) | 2010-08-11 | 2010-08-11 | Method for enhancing anti-etching capacity of photoresist |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110858541A (en) * | 2018-08-24 | 2020-03-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN116825628A (en) * | 2023-08-30 | 2023-09-29 | 粤芯半导体技术股份有限公司 | Side wall forming method and semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207517B1 (en) * | 1998-08-18 | 2001-03-27 | Siemens Aktiengesellschaft | Method of fabricating a semiconductor insulation layer and a semiconductor component containing the semiconductor insulation layer |
| JP2001102439A (en) * | 1999-09-28 | 2001-04-13 | Sharp Corp | Manufacturing method of semiconductor device |
| CN1799138A (en) * | 2003-06-24 | 2006-07-05 | 国际商业机器公司 | Interconnect structures in integrated circuit devices |
| CN101399189A (en) * | 2007-09-28 | 2009-04-01 | 东京毅力科创株式会社 | Manufacturing method, manufacturing apparatus, control program and program recording medium of semicontructor device |
| CN101630630A (en) * | 2009-08-04 | 2010-01-20 | 上海集成电路研发中心有限公司 | Method for preventing lateral erosion in wet etching |
-
2010
- 2010-08-11 CN CN2010102505252A patent/CN101944483A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207517B1 (en) * | 1998-08-18 | 2001-03-27 | Siemens Aktiengesellschaft | Method of fabricating a semiconductor insulation layer and a semiconductor component containing the semiconductor insulation layer |
| JP2001102439A (en) * | 1999-09-28 | 2001-04-13 | Sharp Corp | Manufacturing method of semiconductor device |
| CN1799138A (en) * | 2003-06-24 | 2006-07-05 | 国际商业机器公司 | Interconnect structures in integrated circuit devices |
| CN101399189A (en) * | 2007-09-28 | 2009-04-01 | 东京毅力科创株式会社 | Manufacturing method, manufacturing apparatus, control program and program recording medium of semicontructor device |
| CN101630630A (en) * | 2009-08-04 | 2010-01-20 | 上海集成电路研发中心有限公司 | Method for preventing lateral erosion in wet etching |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110858541A (en) * | 2018-08-24 | 2020-03-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110858541B (en) * | 2018-08-24 | 2022-05-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN116825628A (en) * | 2023-08-30 | 2023-09-29 | 粤芯半导体技术股份有限公司 | Side wall forming method and semiconductor device |
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Application publication date: 20110112 |