CN116825628A - Side wall forming method and semiconductor device - Google Patents
Side wall forming method and semiconductor device Download PDFInfo
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- CN116825628A CN116825628A CN202311103428.4A CN202311103428A CN116825628A CN 116825628 A CN116825628 A CN 116825628A CN 202311103428 A CN202311103428 A CN 202311103428A CN 116825628 A CN116825628 A CN 116825628A
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000010410 layer Substances 0.000 claims abstract description 98
- 230000008021 deposition Effects 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000002346 layers by function Substances 0.000 claims abstract description 36
- 238000006243 chemical reaction Methods 0.000 claims abstract description 26
- 238000009616 inductively coupled plasma Methods 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000005137 deposition process Methods 0.000 claims abstract description 9
- 239000012495 reaction gas Substances 0.000 claims description 33
- 239000007789 gas Substances 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 239000000376 reactant Substances 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 238000000151 deposition Methods 0.000 description 38
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000003929 acidic solution Substances 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 230000005674 electromagnetic induction Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Abstract
The application discloses a side wall forming method and a semiconductor device, wherein the side wall forming method comprises the steps of providing a substrate, wherein the substrate comprises a semiconductor substrate and a functional layer formed on the semiconductor substrate; placing the substrate in an inductively coupled plasma reaction chamber for a deposition process to form a deposition layer covering the semiconductor substrate and the functional layer; performing first etching on the deposition layer in the inductively coupled plasma reaction chamber to form a deposition layer with a preset pattern; and performing second etching on the deposition layer with the preset pattern in the inductively coupled plasma reaction cavity to remove the deposition layer on the semiconductor substrate, reserving the deposition layer covering the side wall of the functional layer, wherein the deposition layer covering the side wall of the functional layer is a side wall. The technical process for forming the side wall can be simplified, so that the production cost of the side wall is saved.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a side wall forming method and a semiconductor device.
Background
The spacer structure is widely used in the process of semiconductor devices, for example, the gate electrode needs to form a spacer to block ion implantation, thereby forming a low doped drain electrode; the photoresist needs to be modified by forming a side wall to modify the width of the photoresist.
In the prior art, the dielectric layer is deposited by a furnace tube process, and then the side wall is formed by dry etching, so that the manufacturing process is complex and the production cost is high. In order to reduce the manufacturing cost of the chip, it is necessary to develop a new sidewall forming method and a semiconductor device.
Disclosure of Invention
The application provides a side wall forming method and a semiconductor device, which can simplify the process flow for forming the side wall, thereby saving the production cost.
In a first aspect, the present application provides a method for forming a sidewall, including:
providing a base, wherein the base comprises a semiconductor substrate and a functional layer formed on the semiconductor substrate;
placing the substrate in an inductively coupled plasma reaction chamber for a deposition process to form a deposition layer covering the semiconductor substrate and the functional layer;
performing first etching on the deposition layer in the inductively coupled plasma reaction cavity to form a deposition layer with a preset pattern;
and performing second etching on the deposition layer with the preset pattern in the inductively coupled plasma reaction cavity to remove the deposition layer on the semiconductor substrate, and reserving the deposition layer covering the side wall of the functional layer, wherein the deposition layer covering the side wall of the functional layer is a side wall.
In the method for forming the side wall provided by the application, the technological parameters of the deposition process comprise intra-cavity pressure, power supply power, temperature, flow of the first reaction gas and flow of the second reaction gas;
the pressure in the cavity, the power of the power supply and the temperature are 40-60 mtorr, 850-650W and 30-50 ℃ respectively, and the flow of the first reaction gas and the flow of the second reaction gas are 140-160 sccm.
In the method for forming the side wall provided by the application, the technological parameters of the first etching comprise intra-cavity pressure, power supply power, bias voltage, temperature, flow of the first reaction gas, flow of the second reaction gas and flow of the third reaction gas;
the pressure in the cavity, the power of the power supply, the bias voltage and the temperature are respectively 10 mtorr-15 mtorr, 450W-550W, 300V-400V and 30-50 ℃, and the flow of the first reaction gas, the flow of the second reaction gas and the flow of the third reaction gas are respectively 20 sccm-30 sccm, 12 sccm-16 sccm and 63 sccm-67 sccm.
In the method for forming the side wall provided by the application, the first reaction gas is HBr, and the second reaction gas is CH 3 F。
In the sidewall forming method provided by the application, the third reaction gas is CF 4 。
In the method for forming a sidewall provided by the application, after the second etching is performed on the deposition layer with the preset pattern, the method further comprises:
and performing ion implantation by taking the side wall as a blocking layer.
In the method for forming a side wall provided by the application, after the ion implantation is performed by taking the side wall as a barrier layer, the method further comprises the following steps:
and removing the side wall by adopting a wet cleaning process.
In the method for forming the side wall provided by the application, the functional layer is a gate layer or a photoresist layer.
In the method for forming the side wall provided by the application, the material of the deposition layer is isotropic polymer.
In a second aspect, the present application provides a semiconductor device manufactured by using the sidewall formation method of any one of the above-mentioned aspects.
In summary, the method for forming a sidewall includes providing a substrate, where the substrate includes a semiconductor substrate and a functional layer formed on the semiconductor substrate; placing the substrate in an inductively coupled plasma reaction chamber for a deposition process to form a deposition layer covering the semiconductor substrate and the functional layer; performing first etching on the deposition layer in the inductively coupled plasma reaction cavity to form a deposition layer with a preset pattern; and performing second etching on the deposition layer with the preset pattern in the inductively coupled plasma reaction cavity to remove the deposition layer on the semiconductor substrate, and reserving the deposition layer covering the side wall of the functional layer, wherein the deposition layer covering the side wall of the functional layer is a side wall. According to the scheme, all the process flows for forming the side wall are completed in the inductively coupled plasma reaction cavity, so that the process flow for forming the side wall can be simplified, and the production cost of the side wall is saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for forming a side wall according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a first intermediate member formed by the sidewall forming method according to the embodiment of the present application.
Fig. 3 is a schematic structural diagram of a second intermediate piece formed by the sidewall forming method according to the embodiment of the present application.
Fig. 4 is a schematic structural diagram of a third intermediate member formed by the sidewall forming method according to the embodiment of the present application.
Fig. 5 is a schematic structural diagram of a fourth intermediate member formed by the sidewall forming method according to the embodiment of the present application.
Fig. 6 is a schematic illustration of ion implantation according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Embodiments of the application are described herein with reference to schematic illustrations that are idealized embodiments of the present application. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing.
The spacer structure is widely used in the process of semiconductor devices, for example, the gate electrode needs to form a spacer to block ion implantation, thereby forming a low doped drain electrode; the photoresist needs to be modified by forming a side wall to modify the width of the photoresist. In the prior art, the dielectric layer is deposited by a furnace tube process, and then the side wall is formed by dry etching, so that the manufacturing process is complex, and the production cost is high.
Based on the above, the embodiment of the application provides a side wall forming method and a semiconductor structure. The technical scheme shown in the application will be described in detail through specific examples. The following description of the embodiments is not intended to limit the priority of the embodiments.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for forming a sidewall according to an embodiment of the application. The specific flow of the side wall forming method can be as follows:
101. a base is provided, the base including a semiconductor substrate and a functional layer formed on the semiconductor substrate.
The semiconductor substrate 11 may include a wafer layer, a buried layer, and an epitaxial layer, among others. The buried layer and the epitaxial layer are sequentially stacked on the wafer layer.
In an implementation process, the buried layer may be formed by performing ion implantation of a first conductivity type on an upper surface layer of the wafer layer. For example, sb ion implantation may be performed on the upper surface layer of the wafer layer to obtain the buried layer. There are various methods of forming the epitaxial layer, such as physical vapor deposition, chemical vapor deposition, or other suitable methods.
The material of the wafer layer may be monocrystalline silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium, the wafer layer may be a silicon germanium wafer, a group iii-v element compound wafer, a silicon carbide wafer or a stacked structure thereof, or a silicon-on-insulator structure, or may be a diamond wafer or other semiconductor material wafer known to those skilled in the art, for example, P atoms may be implanted into monocrystalline silicon to form an N-type conductive wafer layer, or B atoms may be implanted into monocrystalline silicon to form a P-type conductive wafer layer.
It should be noted that, in the embodiment of the present application, the material of the functional layer 12 may be polysilicon or photoresist. That is, the functional layer 12 may be a gate layer or a photoresist layer. The structure formed by this step may be as shown in fig. 2.
102. And placing the substrate in an inductively coupled plasma reaction chamber for a deposition process to form a deposition layer covering the semiconductor substrate and the functional layer.
Wherein the inductively coupled plasma reaction chamber (Inductively Coupled Plasma, ICP) is a reaction chamber having a time-varying magnetic field electromagnetic induction generated current as a source of energy.
At least one rf power source is typically applied to the inductively coupled plasma reaction chamber to generate and sustain a plasma in the reaction chamber. There are many different ways to apply rf power, each of which may be designed to result in different characteristics such as efficiency, plasma dissociation, uniformity, etc. In inductively coupled plasma reaction chambers, the rf power source typically emits rf energy into the reaction chamber via a coil-shaped antenna.
It should be noted that the process parameters of the deposition process may include intra-chamber pressure, power supply, temperature, and flow rate of the reactant gases.
Specifically, the pressure in the cavity, the power and the temperature of the power supply can be 40-60 mtorr, 850-650W and 30-50 ℃ respectively, and the flow of the first reaction gas and the flow of the second reaction gas are 140-160 sccm. Preferably, the flow rates of the first reaction gas and the second reaction gas are 150sccm at this time.
Wherein the material of the deposition layer 20 is an isotropic polymer. It will be appreciated that the deposition time of the deposition layer 20 may be set by the thickness of the deposition layer 20 to be deposited, and that the thicker the thickness of the deposition layer 20 to be deposited, the longer the deposition time of the deposition layer 20. The structure formed by this step can be as shown in fig. 3.
103. And performing first etching on the deposition layer in the inductively coupled plasma reaction cavity to form the deposition layer with a preset pattern.
The process parameters of the first etch may include, among other things, intra-chamber pressure, power supply, bias voltage, temperature, flow of the first reactant gas, flow of the second reactant gas, and flow of the third reactant gas.
Specifically, the pressure in the cavity, the power supply power, the bias voltage and the temperature can be 10mtorr to 15mtorr, 450W to 550W, 300V to 400V and 30 ℃ to 50 ℃ respectively, and the flow of the first reaction gas, the flow of the second reaction gas and the flow of the third reaction gas are 20sccm to 30sccm, 12sccm to 16sccm and 63sccm to 67sccm respectively. Preferably, the flow rate of the first reaction gas is 25sccm, the flow rate of the second reaction gas is 14sccm, and the flow rate of the third reaction gas is 65sccm.
It should be noted that, in the embodiment of the present application, the first reaction gas is HBr, and the second reaction gas is CH 3 F, the third reaction gas is CF 4 。
It will be appreciated that in order to avoid damage to the surface of the semiconductor substrate 11 and the surface of the functional layer 12 by overetching, a thinner deposition layer 20 needs to be reserved on the surface of the semiconductor substrate 11 and the surface of the functional layer 12 during the first etching. The time of the first etching may be set according to the thickness of the deposited layer 20 to be reserved on the surface of the semiconductor substrate 11 and the surface of the functional layer 12, and the thinner the thickness of the deposited layer 20 to be reserved is, the longer the time of the first etching is. Wherein the structure formed by this step may be as shown in fig. 4.
104. And performing second etching on the deposition layer with the preset pattern in the inductively coupled plasma reaction cavity to remove the deposition layer on the semiconductor substrate, reserving the deposition layer covering the side wall of the functional layer, wherein the deposition layer covering the side wall of the functional layer is a side wall.
It will be appreciated that in order to avoid over-etching, damage is caused to the surface of the semiconductor substrate 11 and the surface of the functional layer 12, during the second etching, the pressure in the cavity, the power supply, the bias voltage, the temperature, and the flow rates of the first reactive gas, the second reactive gas, and the third reactive gas may be adjusted accordingly according to the actual situation, so as to achieve the purpose of removing the deposited layer 20 on the surface of the semiconductor substrate 11 and the surface of the functional layer 12 without damaging the surface of the semiconductor substrate 11 and the surface of the functional layer 12.
In some embodiments, after performing the second etching on the deposited layer 20 having the predetermined pattern to form the structure shown in fig. 5, ion implantation or etching may be performed by using the sidewall 21 as a barrier layer. For example, as shown in fig. 6, when the functional layer 12 is a gate layer, the sidewall 21 may be used to block ion implantation, thereby forming a low doped drain. Alternatively, when the functional layer 12 is a photoresist layer, the sidewall 21 may be used to block etching, so as to modify the width of the photoresist layer.
In some embodiments, a wet clean process may also be used to remove the sidewall 21 after ion implantation. For example, the structure shown in fig. 6 is cleaned with a chemical agent to form the structure shown in fig. 7. Wherein the chemical reagent may comprise one or more of sulfuric acid, hydrochloric acid, nitric acid, hydrofluoric acid. That is, the acidic solution may include any one of the above-mentioned various solutions, or may also include a combination of any two or more of the above-mentioned various solutions, which is not limited herein.
In some embodiments, the embodiment of the present application further provides a semiconductor device, where the semiconductor device shown in fig. 7 may be manufactured by using the sidewall forming method provided by the embodiment of the present application. Note that, the meaning of the terms in this embodiment is the same as that of the terms in the above-described semiconductor device embodiment, and specific implementation details may refer to the description in the above-described semiconductor device embodiment.
In summary, the method for forming a sidewall according to the embodiments of the present application includes providing a substrate 10, where the substrate 10 includes a semiconductor substrate 11 and a functional layer 12 formed on the semiconductor substrate 11; placing the base 10 in an inductively coupled plasma reaction chamber for deposition process to form a deposition layer 20 covering the semiconductor substrate 11 and the functional layer 12; performing first etching on the deposition layer 20 in the inductively coupled plasma reaction chamber to form the deposition layer 20 having a predetermined pattern; and performing second etching on the deposition layer 20 with the preset pattern in the inductively coupled plasma reaction chamber to remove the deposition layer 20 on the semiconductor substrate 11, and reserving the deposition layer 20 covering the side wall of the functional layer 12, wherein the deposition layer 20 covering the side wall of the functional layer 12 is a side wall 21. The scheme completes all the process flows for forming the side wall 21 in the inductively coupled plasma reaction chamber, and can simplify the process flow for forming the side wall 21, thereby saving the production cost and time.
The side wall forming method and the semiconductor device provided by the application are described in detail, and specific examples are applied to the application to explain the principle and the implementation mode of the application, and the description of the examples is only used for helping to understand the core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (10)
1. The side wall forming method is characterized by comprising the following steps of:
providing a base, wherein the base comprises a semiconductor substrate and a functional layer formed on the semiconductor substrate;
placing the substrate in an inductively coupled plasma reaction chamber for a deposition process to form a deposition layer covering the semiconductor substrate and the functional layer;
performing first etching on the deposition layer in the inductively coupled plasma reaction cavity to form a deposition layer with a preset pattern;
and performing second etching on the deposition layer with the preset pattern in the inductively coupled plasma reaction cavity to remove the deposition layer on the semiconductor substrate, and reserving the deposition layer covering the side wall of the functional layer, wherein the deposition layer covering the side wall of the functional layer is a side wall.
2. The sidewall formation method of claim 1, wherein said process parameters of said deposition process include intra-chamber pressure, power supply, temperature, flow of a first reactant gas, and flow of a second reactant gas;
the pressure in the cavity, the power of the power supply and the temperature are 40-60 mtorr, 850-650W and 30-50 ℃ respectively, and the flow of the first reaction gas and the flow of the second reaction gas are 140-160 sccm.
3. The sidewall formation method of claim 1, wherein said process parameters of said first etch include intra-chamber pressure, power supply, bias voltage, temperature, flow of a first reactant gas, flow of a second reactant gas, and flow of a third reactant gas;
the pressure in the cavity, the power of the power supply, the bias voltage and the temperature are respectively 10 mtorr-15 mtorr, 450W-550W, 300V-400V and 30-50 ℃, and the flow of the first reaction gas, the flow of the second reaction gas and the flow of the third reaction gas are respectively 20 sccm-30 sccm, 12 sccm-16 sccm and 63 sccm-67 sccm.
4. A side wall forming method according to claim 2 or 3, wherein said first reaction gas is HBr and said second reaction gas is CH 3 F。
5. The sidewall forming method of claim 3, wherein said third reactant gas is CF 4 。
6. The sidewall forming method of claim 1, further comprising, after said second etching said deposited layer having said predetermined pattern:
and performing ion implantation by taking the side wall as a blocking layer.
7. The method of forming a sidewall of claim 6, further comprising, after said ion implantation using said sidewall as a barrier:
and removing the side wall by adopting a wet cleaning process.
8. The method of claim 1, wherein the functional layer is a gate layer or a photoresist layer.
9. The sidewall spacer forming method of claim 1, wherein said deposited layer is an isotropic polymer.
10. A semiconductor device, characterized in that the semiconductor device is manufactured using the sidewall formation method according to any one of claims 1 to 9.
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| CN202311103428.4A CN116825628A (en) | 2023-08-30 | 2023-08-30 | Side wall forming method and semiconductor device |
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| CN202311103428.4A CN116825628A (en) | 2023-08-30 | 2023-08-30 | Side wall forming method and semiconductor device |
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