CN102881566A - Forming method for through-hole graphs - Google Patents
Forming method for through-hole graphs Download PDFInfo
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- CN102881566A CN102881566A CN2012103699517A CN201210369951A CN102881566A CN 102881566 A CN102881566 A CN 102881566A CN 2012103699517 A CN2012103699517 A CN 2012103699517A CN 201210369951 A CN201210369951 A CN 201210369951A CN 102881566 A CN102881566 A CN 102881566A
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Abstract
The invention provides a forming method for through-hole graphs. The method includes: sequentially depositing a medium layer, a first hard mask layer and a second mask layer on a substrate; coating a first photoresistance film, and using a latticed first through-hole subgraph to pattern the second mask layer by exposure and etching processes; removing the first photoresistance film; coating a second photoresistance film again, and using a latticed second through-hole subgraph to pattern the second photoresistance film after photoetching; using a superposed graph of the first through-hole subgraph and the second through-hole subgraph to pattern the first hard mask layer and the medium layer; and finally removing the second photoresistance film and the second hard mask layer. Consequently, by the forming method for the through-hole graphs, photoetching limit that single exposure patterning cannot obtain can be reached, difficulty of photoetching process is lowered, resolution ratio is effectively improved, process can be simplified, production efficiency can be improved, and cost can be saved.
Description
Technical field
The invention belongs to the semiconductor integrated circuit manufacturing process technology field, relate to a kind of photoetching technique, relate in particular to a kind of formation method of via hole image.
Background technology
Photoetching is the pusher of semiconductor development as one of key technology of semiconductor and related industry development and progress thereof, is supporting the development of semiconductor industry, also is the bottleneck of semiconductor manufacturing industry development.
Resolution is interpreted as can be by the minimum spacing of two figures of clear parsing.In photoetching, lens have been collected the diffracted ray of different stage during imaging, and resolution is defined as the clear very near right ability of feature pattern in interval on the silicon chip of telling, and the formula of resolution R is as follows:
Wherein, λ is the wavelength of light source, and NA is the numerical aperture of lens, and K1 is the process factor of optical system, comprises that exposure sources, mask plate, photoresist and resolution enhance technology etc., K1 have reflected the complexity of photoetching.By following formula as can be known, larger NA value allows lens to collect more diffracted ray, thereby is conducive to the reduction of resolution R value, yet this effect is with the cost that is reduced to of depth of focus DOF (depth of focus).When depth of focus refers to guarantee clear picture, the distance that focus moves along optical axis, the formula of depth of focus (DOF) is as follows:
Wherein, K2 is the constant relevant with photoresist, and λ is the wavelength of light source, and NA is the numerical aperture of lens.
In order to improve resolution, the wavelength of optical exposure machine constantly reduces, and has developed into the deep ultraviolet (DUV) of 248 nm, 193nm from the near ultraviolet (NUV) of 436nm, 365nm, and characteristic size has also experienced the process from micron, sub-micron to nanometer.In exploring the process of small-feature-size more, it is found that still has very large space that existing ripe photoetching technique is extended.Liquid immersion lithography, polarized light source, resolution enhance technology (RET) is ripe available scheme now that becomes gradually, these schemes and technological break-through are so that utilize the 193nm wavelength light source to realize that the printing of λ/4 even less figure becomes possibility, said method has solved the technical bottleneck of semiconductor industry in field of lithography to a certain extent, and promotes the development of Moore's Law.
Utilize the method for single exposure technology patterned media layer to be generally: the deposition medium material forms dielectric layer on substrate, form hard mask layer at dielectric layer, at hard mask layer coating photoresistance film, in the photoresistance film, form via hole image after the photoetching, pass through etching technics, with via hole image patterned hard mask layer and dielectric layer, remove at last hard mask layer.Yet along with semiconductor device miniature, the figure spacing of dielectric layer figure is dwindled gradually, to the accordingly gradually raising of requirement of resolution.Because the restriction of exposure device and photoresist, utilize existing application resolution develop skill (RET) improve resolution, formation has closely spaced via hole image and realizes having had certain difficulty in its technique, therefore, industry is badly in need of under the prerequisite that does not change existing photoetching infrastructure, the solution of Effective Raise photoetching resolution.
Application number is in the patent of 200710129438.X, proposition utilizes double-exposure technique to form the method for pattern in semiconductor device, at first, on semiconductor substrate (its top layer is dielectric layer), deposit successively multi-functional hard mask layer, the first hard mask layer and the second hard mask layer, by double exposure and etching, form the stack pattern of the first and second hard mask layers, utilize this stack pattern to come the multi-functional hard mask layer of patterning, then carry out resistance agent flow process at multi-functional hard mask layer pattern, form through-hole pattern, utilize at last this through-hole pattern to come the patterned semiconductor substrate.Although double exposure technique is proposed in this patent,, the hard mask layer number of plies is more, and after through-hole pattern forms, also will carry out again resistance agent flow process and form manhole, not only processing step is more, prolong the process time, also increased unnecessary production cost.In order to overcome the problems referred to above, need to utilize double-exposure technique, develop simple and direct technique and finish high resolution design.Because waffle-like pattern after photoetching, etching, can be formed directly in the through-hole pattern with certain fillet structure, so this pattern is applied in the double-exposure technique, will simplify processing step, bring larger productivity effect.
Summary of the invention
For the problems referred to above, main purpose of the present invention not only can utilize existing exposure technique to improve exposure resolution ratio for a kind of formation method of via hole image is provided, and can also simplify production stage, enhances productivity, and saves cost, increases economic benefit.
For reaching above purpose, the invention provides a kind of formation method of via hole image, comprise the steps:
Step S01: the deposition medium material forms dielectric layer on Semiconductor substrate, and forms successively the first hard mask layer and the second hard mask layer on dielectric layer; Wherein, the material of the first hard mask layer is different from the material of the second hard mask layer;
Step S02: at the second hard mask layer coating the first photoresistance rete, photoetching the first photoresistance rete has the first photoresistance rete of the first through hole spirte with formation;
Step S03: by etching technics, with the first through hole spirte patterning the second hard mask layer;
Step S04: remove described the first photoresistance rete;
Step S05: be coated with the second photoresistance rete at the body structure surface that forms through above-mentioned steps, photoetching the second photoresistance film has the second photoresistance rete of the second through hole spirte with formation;
Need to prove, the first and second through hole spirtes here are latticed figure.
Step S06: by etching technics, described the first hard mask layer of stack figure patterning and dielectric layer with the first through hole spirte and the second through hole spirte form through-hole pattern in described dielectric layer;
Step S07: remove the second photoresistance rete and the second hard mask layer.
Preferably, the first and second through hole spirtes are square net shape figure.
Preferably, the through hole live width in the first through hole spirte is more than 2 times of through hole live width of via hole image in the dielectric layer.
Preferably, the through hole live width in the first through hole spirte is 3 times of through hole live width of via hole image in the dielectric layer.
Preferably, the figure spacing in the first through hole spirte is more than 1.5 times of figure spacing of via hole image in the dielectric layer.
Preferably, the figure spacing in the first through hole spirte is 2 times of figure spacing of via hole image in the dielectric layer.
Preferably, the stack figure of the first through hole spirte and the second through hole spirte is etching through hole patterns figure.
Preferably, dielectric layer is silicon dioxide layer.
Preferably, dielectric layer is low K dielectric layer.
Preferably, dielectric layer is ultralow K dielectric material.
Preferably, the material of low K dielectric layer is the fluorine doped silicate glasses.
Preferably, also comprise among the step S05: between the second hard mask layer and the first photoresistance film, also be coated with one deck bottom anti-reflective rete.
Preferably, also comprise among the step S02: between the first hard mask layer and the second photoresistance film, also be coated with one deck bottom anti-reflective rete.
Can find out from technique scheme, compare with the photoetching through hole of routine, the manufacture method of a kind of via hole image of the present invention, the minimum spacing of the figure that the double exposure Graphics overlay forms reduces.And the first and second spirtes are latticed figure, can be formed directly in through hole with fillet by etching technics, do not need to hinder the agent flow process again.Not only can reduce the exposure technology difficulty, improve exposure resolution ratio, can also simplify technique, enhance productivity, save cost.
Description of drawings
Fig. 1 is the schematic diagram of the dielectric layer figure in the embodiment of the invention
Fig. 2 is the schematic diagram of the first through hole spirte of forming in the embodiment of the invention
Fig. 3 is the schematic diagram of the second through hole spirte of forming in the embodiment of the invention
Fig. 4 is the schematic diagram of the figure that forms of the first through hole spirte in the embodiment of the invention and the stack of the second through hole spirte
Fig. 5 is the schematic flow sheet of a preferred embodiment of the formation method of a kind of via hole image of the present invention
Fig. 6-Figure 12 is the generalized section of main technological steps of the formation method of a kind of via hole image of the embodiment of the invention
Fig. 6 is the generalized section that forms successively dielectric layer, the first and second hard mask layers in the embodiment of the invention on substrate
Fig. 7 is the generalized section of upper the first photoresistance rete of coating in the embodiment of the invention
Fig. 8 is the generalized section behind the exposure imaging for the first time in the embodiment of the invention
Fig. 9 is the generalized section after etching is removed photoresist for the first time in the embodiment of the invention
Figure 10 is the generalized section behind upper the second photoresistance film of coating in the embodiment of the invention
Figure 11 is the generalized section behind the exposure imaging for the second time in the embodiment of the invention
Figure 12 is the generalized section after etching is removed photoresist for the second time in the embodiment of the invention
Embodiment
Some exemplary embodiments that embody feature ﹠ benefits of the present invention will be described in detail in the explanation of back segment.Be understood that the present invention can have in different examples various variations, its neither departing from the scope of the present invention, and explanation wherein and be shown in the usefulness that ought explain in essence, but not in order to limit the present invention.
Above-mentioned and other technical characterictic and beneficial effect are elaborated to the formation method of a kind of via hole image of the present invention in connection with embodiment and accompanying drawing 1-12.
Among the present invention, the shape of the through hole in the dielectric layer figure can be arbitrarily.In the present embodiment, the dielectric layer figure that forms take identical square through-hole is as example is explained the present invention, is not the dielectric layer figure that other the shape of through holes among restriction the present invention forms.Seeing also Fig. 1, is the schematic diagram of the dielectric layer figure in the embodiment of the invention.101 is 1 through hole in the dielectric layer figure shown in the figure, and the below illustrates as an example of this through hole 101 example.Through hole 101 is square.The live width sum that the spacing of through hole 101 and adjacent through-holes adds through hole 101 is the minimum spacing that repeats of through hole 101 figures for this reason, also is the minimum spacing of dielectric layer figure.Minimum resolution to photoetching process requires common minimum spacing by figure to determine, minimum spacing is less, and is higher to the requirement of photoetching resolution.
Among the present invention, the shape of through holes in the first through hole spirte can be arbitrarily.In the present embodiment, the through hole in the first through hole spirte is identical square through-hole, is not the first through hole spirte that other the shape of through holes of restriction among the present invention forms.See also Fig. 2, Fig. 2 is the schematic diagram of the first through hole spirte of forming in the embodiment of the invention.201 is 1 through hole in the first through hole spirte shown in the figure.The below illustrates as an example of this through hole 101 example.Through hole 201 live widths are 3 times of through hole 101 live widths in as shown in Figure 1 the dielectric layer figure in the first through hole spirte.The live width sum that the spacing of through hole 201 and adjacent through-holes adds through hole 201 is the minimum spacing that repeats of through hole 201 figures for this reason, also is the minimum spacing of the first through hole spirte.The minimum spacing of the first through hole spirte is 2 times of minimum spacing of dielectric layer figure as shown in Figure 1, has reduced the resolution requirement to photoetching process.
Among the present invention, the shape of through holes in the second through hole spirte can be arbitrarily.In the present embodiment, the second through hole spirte among Fig. 3 is an example of the present invention, is not the second through hole spirte that other the shape of through holes of restriction among the present invention forms.See also Fig. 3, Fig. 3 is the schematic diagram of the second through hole spirte of forming in the embodiment of the invention.It is minimum spacings of the second through hole spirte that adjacent through-holes spacing in the second through hole spirte adds both sums of through hole live width, the minimum spacing of the second through hole spirte is 2 times of minimum spacing of dielectric layer figure as shown in Figure 1, has reduced the resolution requirement to photoetching process.
Fig. 4 is the schematic diagram of the figure that forms of the first through hole spirte in the embodiment of the invention and the stack of the second through hole spirte.This figure is patterning the first hard mask layer and the employed figure of dielectric layer.
Now by reference to the accompanying drawings 5 ~ 12, by a specific embodiment method that the present invention forms the double-exposure technique of the dielectric layer pattern described in Fig. 1 is progressively described in detail.
Fig. 5 is the schematic flow sheet of a preferred embodiment of the formation method of a kind of via hole image of the present invention.In the present embodiment, a kind of formation method of via hole image comprises step S01-S07, step S01-S07 passes through respectively accompanying drawing 6 ~ 12 namely along AA ' direction cut-away illustration among Fig. 4, formed cross-section structure during with the described manufacture method concrete steps of explanation Fig. 5 of the present invention.
See also Fig. 5, as shown in the figure, in this embodiment of the present invention, the formation method of sharp a kind of via hole image may further comprise the steps:
Step S01: see also Fig. 6, the deposition medium material forms dielectric layer 502 on Semiconductor substrate 501, and forms successively the first hard mask layer 503 and the second hard mask layer 504 on dielectric layer 502.The material of the first hard mask layer 503 is different from the material of the second hard mask layer 504.
Preferably, dielectric layer 502 is silicon dioxide layer, low K dielectric layer or ultralow K dielectric material.
Further, the low K dielectric layer material of dielectric layer 502 is advanced low-k materials, such as the fluorine doped silicate glasses.
Step S02: see also Fig. 7, at the second hard mask layer 504 coating the first photoresistance rete 505, see also Fig. 8, photoetching the first photoresistance rete 505 has the first photoresistance rete 505 of the first through hole spirte with formation.
Further, please consult again Fig. 8, between the second hard mask layer 504 and the first photoresistance film 1, be coated with bottom anti-reflective film 2.
Particularly, by a series of photoetching processes such as front baking, aligning, exposure, rear baking, developments, with the first through hole spirte patterning the first photoresistance rete 505 shown in Fig. 2.
Further, the first through hole spirte is please consulted Fig. 2 again, and dielectric layer 502 figures are please consulted Fig. 1 again.Generally, the through hole live width in the first through hole spirte can be more than 2 times of through hole live width of the figure in the dielectric layer 502, and the figure spacing in the first through hole spirte can be more than 1.5 times of figure in the dielectric layer 502.In embodiments of the present invention, preferably, the through hole live width in the first through hole spirte is 3 times of through hole live width of the figure in the dielectric layer 502, and the figure spacing in the first through hole spirte is 2 times of figure in the dielectric layer 502.
Step S03: by etching technics, with the first through hole spirte patterning the second hard mask layer 504.
Step S04: remove the first photoresistance rete 505.
Further, see also Fig. 9, by etching technics, remove photoresist after, finish the first through hole spirte to the patterning of the second hard mask layer 504.
Step S05: see also Figure 10, at the first hard mask layer 503 coating the second photoresistance rete 506, see also Figure 11, photoetching the second photoresistance rete 506 has the second photoresistance rete 506 of the second through hole spirte with formation.
Further, please consult again Figure 10, between the first hard mask layer 503 and the second photoresistance film 3, be coated with bottom anti-reflective film 4.
Particularly, by a series of photoetching processes such as front baking, aligning, exposure, rear baking, developments, with the second through hole spirte patterning the second photoresistance rete 506 shown in Fig. 3.
Further, the second through hole spirte is please consulted Fig. 3 again, and dielectric layer 502 figures are please consulted Fig. 1 again.In embodiments of the present invention, the second through hole spirte is the even partition to the through hole in described the first through hole spirte so that the through hole live width of the stack figure of the first through hole spirte and the second through hole spirte be in the first spirte the through hole live width 1/3.In embodiments of the present invention, because the first through hole spirte and the second through hole spirte are square net shape figure, therefore the second through hole spirte correspondingly is divided into 4 identical little square through-holes with each through hole of the first through hole spirte, wherein the figure spacing in the second through hole spirte is 2 times of via hole image in the dielectric layer 502, and the through hole live width in the second through hole spirte is 2 times of via hole image in the dielectric layer 502.This embodiment is explanation the preferred embodiments of the present invention, but does not limit the scope of the invention.
Step S06: by etching technics, with described the first hard mask layer 503 of the stack figure patterning of the first through hole spirte and the second through hole spirte and dielectric layer 502;
It is worth mentioning that, the stack figure of the first through hole spirte and the second through hole spirte is etching through hole patterns figure.
Step S07: remove the second photoresistance rete 506 and the second hard mask layer 504.
Particularly, see also Figure 12, by etching technics with after removing photoresist, with pictorial patternization the first hard mask layer 503 and the dielectric layer 502 of the first through hole spirte and the second through hole spirte stack formation.507 is the through hole of dielectric layer 502.
Further, please consulting Fig. 4, is the schematic diagram of the figure of the first through hole spirte and the second through hole spirte stack formation again.This figure is patterning the first hard mask layer 503 and dielectric layer 502 employed figures.
Further, please consulting Fig. 1, is the figure that dielectric layer 502 forms again.The 101st, a through hole in dielectric layer 502 figures.
In sum, by method of the present invention, can make the double exposure live width of figure and minimum spacing all greater than the dielectric layer figure, reduce the difficulty of photoetching process, and the minimum spacing of the figure that forms of double exposure Graphics overlay reduces, improved resolution.
Above-described only is embodiments of the invention; described embodiment limits scope of patent protection of the present invention; therefore the equivalent structure done of every utilization specification of the present invention and accompanying drawing content changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. the formation method of a via hole image is characterized in that, described method comprises the steps:
Step S01: the deposition medium material forms dielectric layer on Semiconductor substrate, and forms successively the first hard mask layer and the second hard mask layer on described dielectric layer; Wherein, the material of described the first hard mask layer is different from the material of described the second hard mask layer;
Step S02: at described the second hard mask layer coating the first photoresistance rete, described the first photoresistance rete of photoetching has the first photoresistance rete of the first through hole spirte with formation; Wherein, described the first through hole spirte is latticed figure;
Step S03: by etching technics, with described the second hard mask layer of described the first through hole spirte patterning;
Step S04: remove described the first photoresistance rete;
Step S05: be coated with the second photoresistance rete at the body structure surface that forms through above-mentioned steps, described the second photoresistance rete of photoetching has the second photoresistance rete of the second through hole spirte with formation; Wherein, described the second through hole spirte is latticed figure;
Step S06: by etching technics, described the first hard mask layer of stack figure patterning and dielectric layer with described the first through hole spirte and the second through hole spirte form via hole image in described dielectric layer;
Step S07: remove described the second photoresistance rete and the second hard mask layer.
2. manufacture method according to claim 1 is characterized in that, described the first through hole spirte and the second through hole spirte are square net shape figure.
3. manufacture method according to claim 1 is characterized in that, the through hole live width in described the first through hole spirte is more than 2 times of through hole live width of via hole image in the described dielectric layer.
4. manufacture method according to claim 3 is characterized in that, the through hole live width in described the first through hole spirte is 3 times of through hole live width of via hole image in the described dielectric layer.
5. manufacture method according to claim 1 is characterized in that, the figure spacing in described the first through hole spirte is more than 1.5 times of figure spacing of via hole image in the described dielectric layer.
6. manufacture method according to claim 5 is characterized in that, the figure spacing in described the first through hole spirte is 2 times of figure spacing of via hole image in the described dielectric layer.
7. manufacture method according to claim 1 is characterized in that, described the first through hole spirte and described the second through hole spirte stack figure are etching through hole patterns figure.
8. manufacture method according to claim 1 is characterized in that, described dielectric layer is silicon dioxide layer, low K dielectric layer or ultralow K dielectric materials layer.
9. manufacture method according to claim 7 is characterized in that, the material of described low K dielectric layer is the fluorine doped silicate glasses.
10. manufacture method according to claim 1 is characterized in that, between described the second hard mask layer and the first photoresistance film, also is coated with one deck bottom anti-reflective rete among the described step S02; Among the described step S05, between described the first hard mask layer and the second photoresistance film, also be coated with one deck bottom anti-reflective rete.
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| CN104460244A (en) * | 2013-12-30 | 2015-03-25 | 苏州矩阵光电有限公司 | Process for assisting integrated optical production by utilizing double exposure technology |
| CN104752319A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Method for forming conductive hole array pattern |
| CN106129042A (en) * | 2016-06-30 | 2016-11-16 | 上海华力微电子有限公司 | The structure of regulation substrate surface reflectance and method, photoetching method |
| CN110707005A (en) * | 2018-08-03 | 2020-01-17 | 联华电子股份有限公司 | Semiconductor device and method of forming the same |
| CN112086363A (en) * | 2020-09-16 | 2020-12-15 | 北京智创芯源科技有限公司 | Ion implantation method, preparation method of mercury cadmium telluride chip and mercury cadmium telluride chip |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104752319A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Method for forming conductive hole array pattern |
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| CN112086363A (en) * | 2020-09-16 | 2020-12-15 | 北京智创芯源科技有限公司 | Ion implantation method, preparation method of mercury cadmium telluride chip and mercury cadmium telluride chip |
| CN112086363B (en) * | 2020-09-16 | 2021-04-13 | 北京智创芯源科技有限公司 | Ion implantation method, preparation method of mercury cadmium telluride chip and mercury cadmium telluride chip |
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