KR0156151B1 - Isolation method of device of semiconductor apparatus - Google Patents

Isolation method of device of semiconductor apparatus Download PDF

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KR0156151B1
KR0156151B1 KR1019950019680A KR19950019680A KR0156151B1 KR 0156151 B1 KR0156151 B1 KR 0156151B1 KR 1019950019680 A KR1019950019680 A KR 1019950019680A KR 19950019680 A KR19950019680 A KR 19950019680A KR 0156151 B1 KR0156151 B1 KR 0156151B1
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oxide film
substrate
trench
device isolation
field
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KR1019950019680A
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KR970008473A (en
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한정수
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문정환
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체장치의 소자격리방법에 관한 것으로, 새부리현상을 방지하고 평탄화에 유리하도록 한 얕은 트렌치형 소자격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a device isolation method for a semiconductor device, and more particularly to a shallow trench type device isolation method for preventing bird beaks and for flattening.

본 발명은 필드산화막이 형성될 소자격리영역에 해당하는 실리콘 기판부위를 선택적으로 식각하여 트렌치를 형성하는 공정과, 상기 트렌치 내측면에 산화막측벽을 형성하는 공정, 필드산화공정을 행하여 노출된 기판부위와 상기 산화막측벽과 기판이 접촉되는 부위에 열산화막을 성장시키는 공정, 기판 전면에 실리콘 산화물을 형성하는 공정, 및 상기 실리콘 산화막을 에치백하는 공정을 포함하여 이루어지는 반도체장치의 소자격리방법을 제공한다.The present invention provides a method of forming a trench by selectively etching a silicon substrate region corresponding to an element isolation region in which a field oxide film is to be formed, a process of forming an oxide sidewall on the inner surface of the trench, and a field oxidation process. And growing a thermal oxide film on a portion where the oxide film side wall is in contact with the substrate, forming a silicon oxide on the entire surface of the substrate, and etching back the silicon oxide film. .

Description

반도체장치의 소자격리방법Device isolation method of semiconductor device

제1도는 종래의 LOCOS에 의한 소자격리방법을 도시한 공정순서도.1 is a process flowchart showing a device isolation method using a conventional LOCOS.

제2도는 종래의 얕은 트랜치형 소자격리방법을 도시한공정순서도 .2 is a process flowchart showing a conventional shallow trench type device isolation method.

제3도는 본 발명에 의한 소자격리방법을 도시한 공정순서도.3 is a process flowchart showing the device isolation method according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1. 실리콘기관 2. 초기산화막1. Silicon organ 2. Initial oxide film

3. 질화막 4. 필드산화막3. Nitride 4. Field Oxide

5. 산화막측벽 6. 열산화막5. Oxide sidewall 6. Thermal oxide

7. 산화물 8. 불순물을 포함한 박막7. Oxide 8. Thin film containing impurities

본 발명은 반도체장치의 소자격리방법에 관한 것으로, 특히 새부리(bird's beak) 현상을 방지하고 평탄화에 유리하도록 한 얕은 트렌치형 소자격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a device isolation method for a semiconductor device, and more particularly to a shallow trench type device isolation method for preventing bird's beak and advantageous for planarization.

종래의 반도체장치의 소자격리방법을 제1도 및 제2도를 참조하여 설명하면 다음과 같다.A device isolation method of a conventional semiconductor device will now be described with reference to FIGS. 1 and 2.

제1도는 16M DRAM급 이하에서 많이 사용되고 있는 LOCOS(Local oxidation of silicon) 공정으로서, 먼저, 제1도 (a)와 같이 실리콘기판(1)상에 초기산화막 (2)과 질화막(3)을 차례로 형성한 후, 제1도 (b)와 같이 소자격리영역의 질화막(3)을 선택적으로 제거한 다음, 제1도 (c)와 같이 필드산화공정을 행하여 필드산화막(4)을 성장시키고 제1도 (d)와 같이 질화막을 제거함으로써 소자격리 영역을 형성하는 것이다.FIG. 1 is a local oxidation of silicon (LOCOS) process that is widely used in 16M DRAM and below. First, the initial oxide film 2 and the nitride film 3 are sequentially turned on the silicon substrate 1 as shown in FIG. After the formation, the nitride film 3 of the device isolation region is selectively removed as shown in FIG. 1 (b), and then the field oxide film 4 is grown by performing the field oxidation process as shown in FIG. By removing the nitride film as shown in (d), the device isolation region is formed.

제2도는 얕은 트렌치(shallow trench)형 격리방법으로서, 제2도 (a)와 같이 실리콘기판(1)상에 초기산화막(2)과 질화막(3)을 차례로 형성한 후, 질화막(3)과 초기산화막(2)을 선택적으로 식각하여 소자격리영역의 기판부위를 노출시킨 다음, 노출된 기판부위를 식각하여 트렌치를 형성한다.FIG. 2 is a shallow trench isolation method, in which the initial oxide film 2 and the nitride film 3 are sequentially formed on the silicon substrate 1 as shown in FIG. The initial oxide film 2 is selectively etched to expose the substrate portion of the device isolation region, and then the exposed substrate portion is etched to form a trench.

이어서 제2도 (b)와 같이 트렌치를 포함한 기판 전면에 필드 도핑을 위해 불순물을 포함한 박막(8)을 증착한 다음, 제2도 (c)와 같이 필드 도핑시킬 부분만 제외한 나머지 영역상의 불순물을 포함한 박막(8)은 선택적으로 제거한다.Subsequently, a thin film 8 including impurities is deposited on the entire surface of the substrate including the trench as shown in FIG. 2 (b), and then impurities on the remaining regions except for the portion to be field doped as shown in FIG. The included thin film 8 is selectively removed.

다음에 제2도 (d)와 같이 상기 불순물을 포함한 박막(8)으로부터 기판으로 불순물을 드라이브인(drive-in)시킨 후, 불순물을 포함한 박막을 제거한 다음, 열산화막(6)을 성장시키고, 그 위에 두꺼운 산화막(5)을 증착한 후, 제2도 (e)와 같이 상기 두꺼운 산화막(5)을 에치백등과 같은 평탄화공정을 통해 평탄화 시키고, 상기 질화막을 제거함으로써 소자격리영역을 형성한다.Next, as shown in FIG. 2 (d), the impurities are drive-in from the thin film 8 containing the impurities to the substrate, the thin film containing the impurities are removed, and then the thermal oxide film 6 is grown, After the thick oxide film 5 is deposited thereon, the thick oxide film 5 is planarized through a planarization process such as etchback, as shown in FIG. 2E, and the device isolation region is formed by removing the nitride film. .

상기한 종래의 기술에 있어서, LOCOS방법은 새부리에 의한 활성영역의 감소라는 문제가 있어 소자의 고집적화에 한계가 따르게 된다.In the above-described conventional technique, the LOCOS method has a problem of reducing the active area due to a bird's beak, which leads to a limitation in high integration of the device.

또한, 상기 얕은 트렌치형 소자격리방법은 불순물의 확산을 막기 위해 질화막을 사용해야 하며, 최종 단계에서 질화막 제거시 완전한 평탄화가 이루어지지 않는 문제점이 있다.In addition, the shallow trench isolation device method has to use a nitride film to prevent the diffusion of impurities, there is a problem that the complete planarization is not performed when removing the nitride film in the final step.

본 발명은 이와 같은 문제점들을 해결하기 위한 것으로, 새부리현상을 방지하고 평탄화에 유리하도록 한 반도체장치의 소자격리방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for isolating a device of a semiconductor device which prevents bird beaks and is advantageous for flattening.

상기 목적을 달성하기 위한 본 발명의 반도체장치의 소자격리방법은 필드산화막이 형성될 소자격리영역에 해당하는 실리콘 기판부위를 선택적으로 식각하여 트렌치를 형성하는 공정과, 상기 트렌치 내측면에 산화막측벽을 형성하는 공정, 필드산화공정을 행하여 노출된 기판부위와 상기 산화막측벽과 기판이 접촉되는 부위에 열산화막을 성장시키는 공정, 기판 전면에 실리콘 산화물을 형성하는 공정, 및 상기 실리콘 산화막을 에치백하는 공정을 포함하여 이루어진다.The device isolation method of the semiconductor device of the present invention for achieving the above object is a step of forming a trench by selectively etching the silicon substrate portion corresponding to the device isolation region in which the field oxide film is to be formed; Forming a field; forming a field oxide; growing a thermal oxide film on an exposed portion of the substrate and a portion where the oxide film side wall is in contact with the substrate; forming a silicon oxide on the entire surface of the substrate; and etching back the silicon oxide film. It is made, including.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제3도에 본 발명에 의한 반도체장치의 소자격리방법을 공정순서에 따라 도시하였다.3 shows the device isolation method of the semiconductor device according to the present invention according to the process sequence.

먼저, 제3도 (a)와 같이 실리콘기판(1)상에 초기산화막(2)을 성장시킨 후, 필드산화막이 형성될 소자격리영역상의 초기산화막(2)을 선택적으로 제거하고 그에 따라 노출되는 기판부위를 소정깊이로 식각하여 얕은 트렌치를 형성한다. 이어서 제3도 (b)와 같이 기판 전면에 산화막측벽(5)을 형성한 후, 제3도 (c)와 같이 상기 실리콘산화막을 기판 전면에 산화막측벽(5)을 형성한 후, 제3도 (c)와 같이 상기 실리콘산화막을 에치백하여 트렌치 내측면에 산화막측벽(5)을 형성한다.First, after the initial oxide film 2 is grown on the silicon substrate 1 as shown in FIG. 3 (a), the initial oxide film 2 on the device isolation region where the field oxide film is to be formed is selectively removed and exposed accordingly. The substrate portion is etched to a predetermined depth to form a shallow trench. Subsequently, an oxide film side wall 5 is formed on the entire surface of the substrate as shown in FIG. 3 (b), and then an oxide film side wall 5 is formed on the entire surface of the substrate as shown in FIG. As shown in (c), the silicon oxide film is etched back to form an oxide film side wall 5 on the inner side of the trench.

다음에 제3도 (d)와 같이 필드산화공정을 통해 열산화막(6)을 형성하고, 그위에 SOG(Spin On Glass)법등에 의해 산화물(7)을 도포한 다음, 이를 다시 에치백하여 제3도 (e)에 도시된 바와 같이 소자격리영역을 형성한다.Next, as shown in FIG. 3 (d), a thermal oxide film 6 is formed through a field oxidation process, and the oxide 7 is coated thereon by, for example, SOG (Spin On Glass), and then etched back. As shown in FIG. 3 (e), the device isolation region is formed.

상기 필드 열산화막(6) 형성시 제2도 (d)에 도시된 바와 같이 필드영역의 하단 및 실리콘기판과 산화막측벽(5)이 접하는 부분에도 열산호막이 형성되므로 실리콘기판과 실리콘산화막 사이의 계면 특성을 개선시킬 수 있다. 또한, 실리콘기판(1)과 산화막측벽(5) 사이에 성장되는 열산화막은 측벽 자체의 두께와 열산화공정에 의해 결정되며 필드영역의 크기에는 거의 영향을 미치지 않는다.When the field thermal oxide film 6 is formed, as shown in FIG. 2 (d), a thermal coral film is also formed at the bottom of the field region and in contact with the silicon substrate and the side wall of the oxide film 5, so that the interface between the silicon substrate and the silicon oxide film Properties can be improved. In addition, the thermal oxide film grown between the silicon substrate 1 and the oxide film side wall 5 is determined by the thickness of the side wall itself and the thermal oxidation process and has little effect on the size of the field region.

이와 같이 형성되는 본 발명의 필드산화막은 제3도 (f)에 도시된 바와 같이 각각 서로 다른 공정에 의해 형성된 3가지 산화물의 복합체(5, 6, 7)로서, 실리콘 기판(1)과의 접합면에는 열산화막(6)이 형성되며, 그 안쪽으로는 측벽을 이루고 있는 산화막측벽(5)이 형성되고, 나머지 부분은 SOG와 같은 산화물(7)이 형성되어 있다.The field oxide film of the present invention formed as described above is a composite of three oxides (5, 6, 7) formed by different processes as shown in FIG. 3 (f), and is bonded to the silicon substrate 1. A thermal oxide film 6 is formed on the surface, and an oxide film side wall 5 constituting a side wall is formed therein, and an oxide 7 such as SOG is formed on the remaining portion.

상기한 바와 같이 본 발명에 의하면, 새부리를 없앰으로써 필드영역을 정확하게 규정할 수 있으며, 필드산화막을 트랜지스터 형성영역과의 사이에 단차가 없는 평면구조로 형성할 수 있으므로 고집적소자의 제조에 있어 배선등의 공정수행에 앞서 평탄화 공정 측면에서 유리하게 된다.As described above, according to the present invention, the field region can be precisely defined by removing the beak, and the field oxide film can be formed in a planar structure without a step between the transistor formation region. It is advantageous in terms of the planarization process prior to performing the process.

또한, 기존의 필드산화막 형성과정에서는 시리콘기판이 고온에서 장시간 노출되기 때문에 필드산화막이 성정되기 전에 접합 아이솔레이션(Junction Isolation)을 위해 주입된 불순물 원자가 과다하게 확산되는데 비해 본 발명에서는 1000℃ 이하의 온도에서 1시간 이내의 시간동안 비교적 적은 열적 부담(thermal budget)을 겪음으로써 불순물의 과다확산으로 인한 접합 아이솔레이선 효과의 저하를 방지할 수 있다.In addition, in the conventional field oxide film formation process, since the silicon substrate is exposed to a high temperature for a long time, the impurity atoms implanted for junction isolation before diffusion of the field oxide film are excessively diffused. By experiencing a relatively low thermal budget for less than 1 hour at, it is possible to prevent the degradation of the bonded isolray effect due to overdiffusion of impurities.

이와 같이 본 발명은 고집적소자의 제조에 적용시킬 큰 효과를 얻을 수 있게 된다.As described above, the present invention can obtain a great effect to be applied to the manufacture of the highly integrated device.

Claims (4)

필드산화막이 형성될 소자격리영역에 해당하는 실리콘 기판부위를 선택적으로 식각하여 트렌치를 형성하는 공정과, 상기 트렌치 내측면에 산화막측벽을 형성하는 공정, 필드산화공정을 행하여 노출된 기판부위와 상기 산화막측벽과 기판이 접촉되는 부위에 열산화막을 성장시키는 공정, 기판 전면에 실리콘 산화물을 형성하는 공정, 및 상기 실리콘 산화막을 에치백하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체장치의 소자격리방법.Selectively etching the silicon substrate portion corresponding to the device isolation region in which the field oxide film is to be formed, forming a trench, forming an oxide sidewall on the inner surface of the trench, and performing a field oxidation process to expose the exposed substrate portion and the oxide layer. A method of isolating a semiconductor device, comprising: growing a thermal oxide film at a portion where a sidewall is in contact with a substrate, forming a silicon oxide on the entire surface of the substrate, and etching back the silicon oxide film. 제1항에 있어서, 상기 기판을 식각하여 트렌치를 형성하는 공정전에 실리콘 기판상에 초기산화막을 형성하는 공정이 더 포함되는 것을 특징으로 하는 반도체장치의 소자격리방법.The device isolation method of claim 1, further comprising forming an initial oxide film on a silicon substrate before etching the substrate to form a trench. 제1항에 있어서, 상기 트렌치를 형성하는 공정후에 필드 이온주입을 실시하는 공정이 더 포함되는 것을 특징으로 하는 반도체장치의 소자격리방법.The device isolation method of claim 1, further comprising a field ion implantation step after the trench formation step. 제1항에 있어서, 상기 산화막 측벽은 상기 트렌치를 형성한 후, 기판 전면에 실리콘산호막을 증착하고 이를 에치백하여 형성하는 것을 특징으로 하는 반도체장치의 소자격리방법.The device isolation method of claim 1, wherein the oxide sidewall is formed by depositing a silicon coral film on the entire surface of the substrate and etching back the trench.
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