JP2891932B2 - Vertical field-effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a vertical field effect transistor, and more particularly to a structure of a vertical field effect transistor for improving its characteristics.

[0002]

2. Description of the Related Art Conventionally, in a vertical field effect transistor, a groove is formed on the surface of a semiconductor substrate to reduce the on-resistance, and the side surface of the groove is used as a channel region. Thus, the channel width per unit area is increased, and the driving capability of the vertical field effect transistor is increased.

Hereinafter, a conventional technique will be described with reference to FIG. FIG. 5 is a sectional view of a conventional vertical field effect transistor. As shown in FIG. 5, the N ⁺ type semiconductor substrate 2
An N ⁻ -type semiconductor layer 22 is formed on the substrate 1 by epitaxial growth. Then, the upper part of the N ⁻ type semiconductor layer 22 is changed to a P type conductive layer, and a P type base region 23 is formed. Further, an N ⁺ type source region 24 is formed in a surface region of the P type base region 23.

Then, the N ⁺ type source region 24 and the P type base region 23 are dry-etched to form a groove 25. A gate insulating film 26 and a gate electrode 27 are formed on the side wall of the groove 25. This gate electrode 27
Is formed so as to cover. The surface of P-type base region 23 of this interlayer insulating film 28 and N
^{The +} type source region 24 is exposed, and a source electrode 29 electrically connected thereto is formed. On the back surface of the N ⁺ type semiconductor substrate 21, a drain electrode 30 is formed.

[0005]

In the above-mentioned vertical field effect transistor having a groove structure according to the prior art, since the grooves are formed by dry etching, crystal defects remain on the side walls of the grooves and metal contamination is likely to occur. As a result, the withstand voltage of the gate insulating film 26 formed on the side wall of the trench decreases. Such a vertical field effect transistor has 100
A high withstand voltage operation of about V is performed. For this reason, a slight deterioration in the breakdown voltage of the gate insulating film greatly impairs the reliability of the vertical field effect transistor.

Further, according to this conventional technique, the on-resistance of the vertical field effect transistor greatly varies.
This is because, as described above, the depth of the groove formed by dry etching tends to vary, making it difficult to control the channel length. In particular, the on-resistance of this vertical field-effect transistor is sensitive to the channel length, and cannot be dealt with by etching control using ordinary dry etching technology.

It is an object of the present invention to improve the reliability of a gate insulating film in a high breakdown voltage vertical field effect transistor, and to improve the driving capability and stability of the vertical field effect transistor.

[0008]

For this purpose, in the vertical field effect transistor of the present invention, a semiconductor substrate containing a high-concentration impurity of one conductivity type and a low conductivity type semiconductor formed on the semiconductor substrate are provided. and a first semiconductor layer and said first element are formed in a predetermined region of the semiconductor layer isolation insulating film layer containing impurity concentration, the said first semiconductor layer above containing
A second semiconductor layer of selectively opposite conductivity type formed in and on a part of the surface of the child isolation insulating layer, moreover, the second semiconductor layer
The contact angle between the side wall surface of the device and the surface of the element isolation insulating film layer is
A third semiconductor layer containing the same conductivity type high-concentration impurity is formed on the second semiconductor layer, the third semiconductor layer being formed so as to exceed 90 degrees, and a gate formed on a side wall surface of the second semiconductor layer; A gate electrode is formed to cover the insulating film and the element isolation insulating film.

In the vertical field effect transistor for high withstand voltage, the semiconductor substrate and the first semiconductor layer serve as a drain region, the second semiconductor layer serves as a base region, and the third semiconductor layer serves as a source region. It is formed as follows.

Here, the first semiconductor layer and the element
Formed on the same plane where the surface of the insulating layer is {100}
And the side wall surface of the second semiconductor layer has a {111} plane
Alternatively, it may be formed so as to have a {311} plane.

Here, the second semiconductor layer and the third semiconductor layer are formed by a molecular beam epitaxial growth method.

Alternatively, the second semiconductor layer is formed by a chemical vapor deposition method.

Alternatively, a side wall surface of the second semiconductor layer is formed so as to be perpendicular to a surface of the element isolation insulating film, and the gate electrode is etched back by reactive ion etching of a conductive material. The second semiconductor layer is formed on the side wall.

According to the present invention, a second semiconductor layer serving as a channel region or a base region of a vertical field effect transistor is selectively deposited on the first semiconductor layer so as to have a predetermined thickness. Therefore, the crystal quality of the side wall surface of the formed second semiconductor layer is high, and the cleanliness of the side wall surface is also very good. Further, the controllability of the thickness of the second semiconductor layer is very high. Then, the side wall surface of the second semiconductor layer is isolated from the element isolation.
Formed so that the contact angle with the surface of the rim layer exceeds 90 degrees
The gate insulating film is formed uniformly on the side wall surface.
Swell.

For this reason, the quality of the gate insulating film is greatly improved. In addition, the performance of the vertical field-effect transistor is improved and its variation is reduced.

The gate electrode is formed of N serving as a drain region.
It is formed on a ⁺ type semiconductor substrate via a thick insulating film.

Therefore, the parasitic capacitance between the gate and the drain of the vertical field effect transistor is reduced, and the driving capability of the vertical field effect transistor is greatly improved.

[0018]

Next, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a sectional structural view of a vertical field effect transistor of the present invention.

As shown in FIG. 1, an N ⁻ type semiconductor layer 2 is formed as a first semiconductor layer on the surface of an N ⁺ type semiconductor substrate 1 by an epitaxial growth method. Then, an element isolation insulating film 3 is formed between the plurality of N ⁻ -type semiconductor layers 2. A P-type base region 4 is selectively formed as a first semiconductor layer on the surface of the N ⁻ -type semiconductor layer 2. further,
On this P-type base region 4, an N ⁺⁺ type source region 5 is formed as a third semiconductor layer. Here, the P-type base region 4 and the N ⁺⁺ -type source region 5 are formed so as to be perpendicular to the surface of the N ⁻ -type semiconductor layer 2. Here, the P-type base region 4 and the N ⁺⁺ -type source region 5 are formed by a molecular beam epitaxial growth method, that is, MBE (Molec).
This is selectively grown on the N ⁻ -type semiconductor layer 2 by the method of “ultra-beam epitaxy”.

A gate insulating film 6 is formed on the side walls of the P-type base region 4 and the N ^++- type source region 5 thus formed. Then, the gate electrode 7 is formed of the element isolation insulating film 3.
Is formed on. The gate electrode 7 covers the gate insulating film 6.

An interlayer insulating film 8 is formed so as to cover the gate electrode 7. The N ⁺⁺ type source region 5 of the interlayer insulating film 8 is exposed, and a source electrode 9 electrically connected thereto is formed. Also, the N ⁺ type semiconductor substrate 1
The drain electrode 10 is formed on the back surface of the substrate.

Next, a method of manufacturing the vertical field effect transistor according to the first embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 2A, the crystal plane is (10)
A silicon epitaxial layer having a thickness of about 2 μm is formed on an N ⁺ type semiconductor substrate 1 such as the N ⁺ type silicon substrate on the 0) plane, and an N ⁻ type semiconductor layer 2 is provided. The N ^-
The type semiconductor layer 2 is a first semiconductor layer.

Next, a predetermined region of the N ^- type semiconductor layer 2 is etched, and the etched region is selectively oxidized. Then, a thick silicon oxide film reaching the N ⁺ type semiconductor substrate 1 is formed. Next, the surface of this thick silicon oxide film is subjected to chemical mechanical polishing (CMP).
It is ground by the method of. An element isolation insulating film 3 planarized by the CMP method is formed. Here, the element isolation insulating film 3
Is mechanically polished so as to be flush with the surface of the N ⁻ type semiconductor layer 2.

Next, as shown in FIG. 2B, a P-type silicon film is selectively grown on the N ⁻ type semiconductor layer 2 by the MBE method. This P-type silicon film becomes the second semiconductor layer. This P-type silicon film having a thickness of about 2 μm becomes the P-type base region 4. Here, the P-type base region 4 is formed so as to be perpendicular to the surface of the element isolation insulating film 3. That is, a plane equivalent to the (100) plane is formed. In the selective growth of the P-type silicon film, the crystal growth in the lateral direction is suppressed. That is, P
The protrusion of the mold base region 4 on the element isolation insulating film 3 hardly occurs.

Subsequently, a third semiconductor layer is formed by MBE. An N ⁺⁺ source region 5 is formed in the third semiconductor layer. Here, the film thickness of the N ⁺⁺ source region 5 is 1 μm.
Is set to Further, in this case, the arsenic impurity is contained in excess of the solid solution limit, and the electric resistance in this region becomes smaller than in the normal case.

Next, the entire surface is thermally oxidized to form a gate insulating film 6. Here, the thickness of the gate insulating film 6 is 50
It is set to about nm.

Next, as shown in FIG. 2C, a polycrystalline silicon film 11 containing a phosphorus impurity is deposited on the entire surface by a chemical vapor deposition (CVD) method. Here, the thickness of the polycrystalline silicon film 11 is about 3 μm.

Next, reactive ion etching (hereinafter referred to as R
IE), the entire surface is anisotropically etched. That is, the polycrystalline silicon film 11 is etched back. By this etch back, the polycrystalline silicon film on the N ⁺⁺ type source region 5 is removed by etching. Then, as shown in FIG. 3A, a sidewall-shaped gate electrode 7 is formed on the side walls of the P-type base region 4 and the N ^++- type source region 5. Note that this gate electrode 7 is used for the element isolation insulating film 3.
Also formed on top.

Next, as shown in FIG. 3B, an interlayer insulating film 8 is formed so as to cover the gate electrode 7. Here, the interlayer insulating film 8 is a PSG (silicon oxide film containing phosphor glass) having a thickness of about 1 μm deposited by the CVD method. Then, a contact hole is provided in the interlayer insulating film 8 on the N ⁺⁺ type source region 5. Next, a source electrode 9 electrically connected to the N ⁺⁺ type source region 5 through the contact hole is formed. The source electrode 9 is an aluminum metal having a thickness of about 3 μm.

Finally, a drain electrode is formed on the back surface of the N ⁺ type semiconductor substrate 1, and the vertical field effect transistor of the present invention described with reference to FIG. 1 is formed.

In the vertical field effect transistor according to the present invention,
The P-type base region 4 or the N ^++- type source region 5 is formed not by a dry etching method but by selective growth of a semiconductor film by MBE. Therefore, there is no crystal defect on the side wall of the P-type base region 4 and no metal contamination. Then, the withstand voltage of the gate insulating film 6 formed on the side wall is greatly improved.

Further, in the case of the present invention, the variation in the on-resistance of the vertical field effect transistor is very small.
This is, as described above, the MB forming the P-type base region.
This is because the E method is very excellent in controlling the film thickness.

In the present invention, since the gate electrode is formed on the element isolation insulating film having a large thickness, the parasitic capacitance between the gate and the drain of the vertical field effect transistor is greatly reduced. The value of this parasitic capacitance is 1 in the conventional case.
/ 20 or so. For this reason, the feedback capacitance during the operation of the vertical field effect transistor is reduced, and the switching speed is greatly improved.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a sectional view of a vertical field effect transistor according to the second embodiment.

In the second embodiment, the side wall surface of the P-type base region is formed so as to be inclined with respect to the element isolation insulating film. Others are almost the same as those described in the first embodiment. That is, as shown in FIG.
-Type semiconductor layer 2 is formed ^- N by epitaxial growth in the N ⁺ semiconductor substrate 1 of the surface of 0). And
An element isolation insulating film 3 is formed between the plurality of N ⁻ type semiconductor layers 2. P-type base region 4a is selectively formed on the surface of N ^- type semiconductor layer 2. Further, N ⁺ type source region 5a is formed on P type base region 4a. Here, these P type base region 4a and N ⁺ type source region 5
“a” is formed so as to have a certain inclination angle with respect to the element isolation insulating film 3 or the surface of the N ⁻ type semiconductor layer 2. Here, the P-type base region 4a and the N ⁺ -type source region 5a
Is selectively grown on the N ⁻ type semiconductor layer 2 by the selective CVD method.

Hereinafter, a gate insulating film 6 is formed on the side walls of the P-type base region 4a and the N ⁺ -type source region 5a. The gate electrode 7a is formed so as to cover the gate insulating film 6 and the element isolation insulating film 3. Here, the gate electrode 7a is formed so as to bury the entire recess.

Then, an interlayer insulating film 8 is formed so as to cover the gate electrode 7a. This interlayer insulating film 8
The N ⁺ -type source region 5a is exposed, a source electrode 9 electrically connected to these are formed. On the back surface of the N ⁺ type semiconductor substrate 1, a drain electrode 10 is formed.

In the second embodiment, the side wall surface of the P-type base region 4a becomes (111) or (311) or the like, and is a surface inclined from (100). Therefore, the mobility of electrons in the channel region is improved, and the operation speed of the vertical field-effect transistor is increased.

Furthermore, since the contact angle between the side wall surface of the P-type base region 4a and the surface of the element isolation insulating film 3 is 90 degrees or more, the gate insulating film 6 is formed uniformly on the P-type base region 4a surface. Become so. Normally, the gate insulating film is formed by thermal oxidation. However, when the contact angle is small, the oxidation at the contact portion of the surface of the oxidized P-type base region 4a with the element isolation insulating film 3 is suppressed. You. Therefore, the thickness of the gate insulating film at the contact portion is reduced.

In the above embodiment, the case where the vertical field-effect transistor is an N-channel type has been described. The present invention is not limited to the N-channel type, but is similarly formed in the P-channel type.

[0042]

As described above, in the vertical field effect transistor according to the present invention, the P type base region 4 or the N type
^{The ++} type source region 5 is formed not by a dry etching method but by selective growth of a semiconductor film by a molecular beam epitaxial growth method or a chemical vapor deposition method.

Therefore, there is no crystal defect on the side wall of the P-type base region and no metal contamination. Then, the withstand voltage of the gate insulating film formed on the side wall is greatly improved.

Further, in the case of the present invention, the variation in the on-resistance of the vertical field effect transistor becomes very small.
This is because, as described above, the method of growing a P-type base region crystal is very excellent in controlling the film thickness.
Among them, especially in the molecular beam epitaxial growth method, the variation of the on-resistance becomes 1/10 or less of the conventional one.

In the present invention, since the gate electrode is formed on the element isolation insulating film having a large thickness, the parasitic capacitance between the gate and the drain of the vertical field effect transistor is greatly reduced. For this reason, the feedback capacitance during the operation of the vertical field effect transistor is reduced, and the switching speed is greatly improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a vertical field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the vertical field effect transistor in the order of manufacturing steps.

FIG. 3 is a sectional view of the vertical field-effect transistor in the order of manufacturing steps.

FIG. 4 is a cross-sectional view of a vertical field effect transistor according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view of a vertical field effect transistor illustrating a conventional technique.

[Explanation of symbols]

1,21 N ⁺ type semiconductor substrate 2,22 N ⁻ type semiconductor layer 3 Element isolation insulating film 4,4a, 23 P type base region 5N ⁺⁺ type source region 5a, 24 N ⁺ type source region 6,26 Gate insulation Film 7, 7a, 27 Gate electrode 8, 28 Interlayer insulating film 9, 29 Source electrode 10, 30 Drain electrode 11 Polycrystalline silicon film 25 Groove

Claims (5)

(57) [Claims] 1. A semiconductor substrate containing a high-concentration impurity of one conductivity type, a first semiconductor layer containing a low-concentration impurity of the same conductivity type formed on the semiconductor substrate, and the first semiconductor layer And a device isolation insulating film layer formed in a predetermined area of the first semiconductor layer and the device isolation insulating film layer.
A second semiconductor layer of the opposite conductivity type is selectively formed on a part of the surface, and the side wall surface of the second semiconductor layer and the second semiconductor layer are selectively formed.
The contact angle with the surface of the element isolation insulating film layer exceeds 90 degrees.
A third semiconductor layer containing a high-concentration impurity of the same conductivity type is formed on the second semiconductor layer; a gate insulating film formed on a side wall surface of the second semiconductor layer; A vertical field-effect transistor, wherein a gate electrode is formed so as to cover the isolation insulating film layer . 2. The first semiconductor layer and element isolation insulation.
The surface of the film layer is formed on the same plane as the {100} plane,
The side wall surface of the second semiconductor layer is {111} plane or
Vertical field effect transistor of claim 1, wherein that you have been formed so that the {311} plane. 3. The semiconductor substrate and the first semiconductor layer,
A drain region, wherein the second semiconductor layer is a base region;
Wherein the third semiconductor layer is a source region and has a high breakdown voltage.
2. The transistor according to claim 1, wherein:
Or a vertical field effect transistor according to claim 2. 4. The vertical field effect transistor according to claim 1, wherein said second semiconductor layer and said third semiconductor layer are formed by a molecular beam epitaxial growth method. . 5. The semiconductor device according to claim 1, wherein said second semiconductor layer is formed by a chemical vapor deposition method.
A vertical field effect transistor according to claim 3.