JPH0360076A - Manufacture of vertical field effect transistor - Google Patents

Abstract

PURPOSE:To severely control the thicknesses and impurity concentrations of source, channel and drain regions by forming the source, channel and drain regions on a semiconductor substrate by molecular layer epitaxy. CONSTITUTION:After an oxide film 2 is formed on a silicon substrate 1, three layers of a source region 3, a channel region 4 and a drain region 5 are formed in a state that the oxide film of an element forming part is removed by etching by a molecular layer epitaxy. In this case, semiconductor component element gas is introduced at a predetermined temperature with a time chart of a predetermined pressure as one cycle. This cycle is repeated to easily form a transistor having several thousands Angstrom of a channel length, and impurity concentration distribution is variously controlled to easily weaken a drain electric field.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a vertical field effect transistor.

[Summary of the invention]

The present invention makes it possible to strictly control the thickness and impurity density of each region by forming a source region, a channel region, and a drain region on the surface of a semiconductor substrate using a molecular layer epitaxial growth method. This is a method for manufacturing a vertical field effect transistor.

[Conventional technology]

In the prior art, when forming vertical field effect transistors, ion implantation or conventional epitaxial techniques were used to form P-type and n-type regions.

[Ll that the invention tries to solve! ! ! In the above conventional technology, when forming a semiconductor thin film such as three layers of P type, n type, and P type or three layers of n type, P type, and n type, each layer,
In particular, it is important to form the intermediate layer to a thickness of several hundred Å or less with good control because in ion implantation, impurities have a Gaussian distribution, and in normal epitaxial technology, the effects of autodoping and solid phase diffusion of impurities are large. It was difficult.

[Means to solve the problem]

In order to solve the above problems, in the present invention, using a molecular layer epitaxial growth method, P-type, n-type, P-type, or n-type
The source region, channel region, and drain region, which are three layers of P type and n type, were formed by molecular layer epitaxial growth.

[Effect]

According to the molecular layer epitaxial growth method, autodoping and solid phase diffusion are suppressed to a much lower level than when using normal epitaxial techniques, so that the source, channel, and drain regions of vertical field effect transistors can be Each film can be formed to a thickness of several hundred angstroms or less with an accuracy of several atomic layers, and the impurity concentration distribution can be precisely controlled.

〔Example〕

Examples of the present invention will be described below.

FIG. 1 shows an embodiment of the invention. FIG. 1 (al) shows the state where the oxide film 2 was formed on the silicon substrate 1, and the oxide film in the element formation area was removed by etching.

The first box) uses the molecular layer epitaxial growth method,
Source area 3. Channel region 4. The formation of the three layers of the drain region 5 is shown. In this case, in the molecular layer epitaxial method, since the mean free path of gas molecules is long, it is possible to form even an aspect ratio of about 1O.

At this time, using the silicon molecular layer epitaxial growth method, a semiconductor component element gas such as 5itlzcJz and a gas containing an impurity element such as B2H6 or AsH* are grown at a temperature of 825° C. for one cycle under a pressure time chart as shown in FIG. If introduced as,
The pressure at the time of introduction of 5iHzcJt is 1.5 x 10-'f
orr, the pressure at the time of introduction of 5zna is 5i11. c.
According to the ratio of 1 to the pressure at the time of introduction, a thin film having an impurity concentration as shown in FIG. 4 and a thickness as shown in FIG. 3 is formed. By repeating this cycle, a semiconductor thin film having a desired conductivity type, impurity concentration, and film thickness can be obtained.

For example, the pressure of 5IR1dz is 1.5X10-'yor
The pressure ratio of r+BJi to 5iHzJz is 4X10
-", 260 people in 100 cycles, B concentration 1.
If a 5X10"(am-") source region is formed and then AsTo is introduced at a pressure ratio of 1X10- to 5iHtdz, then in 300 cycles, 270 people and an As concentration of 1.0X10" (am-3) will be obtained. A channel region is formed, followed by a drain region in the same manner as the source region.

As described above, according to the molecular layer epitaxial growth method, the impurity concentration and film thickness of the source region, channel region, and drain region can be controlled very precisely, so that the impurity concentration distribution as shown in Fig. 5 can be achieved. By doing so, it is possible to easily create a structure that weakens the electric field near the junction. As mentioned above, it is also easy to form a transistor with a channel length of several thousand amperes or less.

Subsequently, FIG. 1 fcl shows the oxide film being etched to form a gate. Next, in FIG. 1 (dl shows the gate insulating film 6 formed by thermal oxidation or CVD. In FIG. 1 tel, the gate electrode 7 is formed by depositing polycrystalline silicon, photolithography, and etching.
The figure shows the formation of the .

〔Effect of the invention〕

As described above, by using the molecular layer epitaxial growth method, not only can transistors with channel lengths of several thousand lengths be easily formed, but also the drain electric field can be easily weakened by controlling the impurity concentration distribution in various ways.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view showing an example of the method of the present invention in the order of steps;
The figure is a time chart of an example of the gas introduction pressure in the molecular layer evitital growth method. Figure 3 is a diagram showing the relationship between the ratio of the pressure at the time of introduction of B, H, to 5iHzCjz and the film thickness grown per cycle. Figure 4 5 is a diagram showing the relationship between the ratio of the pressure at the time of introduction of BJ to 5 iHzdz and 84 degrees in the film, and FIG. 5 is a diagram showing the impurity concentration distribution of the structure that weakens the electric field of the junction.・Silicon substrate ・Oxide film ・Source region ・Channel region ・Drain region ・Gate insulating film ・Gate electrode ・B? s degrees/At concentration

Claims (1)

[Claims] A source or drain region is formed on the surface of the semiconductor substrate using a molecular layer epitaxial growth method using a gas containing component elements of the semiconductor and a gas containing an impurity element as a donor or acceptor. A channel region is formed with a gas containing an impurity element of opposite conductivity type and a gas containing a semiconductor component element, and then a gas containing an impurity element of opposite conductivity type and a gas containing a semiconductor component element are formed. 1. A method for manufacturing a vertical field effect transistor, characterized in that the impurity density distribution and channel length of the source region, channel region, and drain region are strictly controlled by forming the source or drain region.