JPS59222923A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To enable to manufacture a selective epitaxially grown substrate having flat surface by a method wherein a polycrystalline silicon is inserted as a buffer layer between an insulating film and epitaxially grown silicon. CONSTITUTION:An insulating film 2 is partially provided on a silicon substrate 1, and polycrystalline silicon 13 is coated on the side wall of said insulating film only. When an epitaxial silicon layer 4 is selectively grown on the exposed surface 3 of the silicon substrate, a very flat surface having no irregularity of facet in the vicinity of the interface of the insulating film can be obtained. The polycrystalline silicon is to be formed in the thickness within 500-800Angstrom .

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor substrate in which a silicon epitaxial layer is selectively grown on a single crystal substrate having an insulating film region.

In conventional semiconductor devices, a silicon substrate is made into a desired P-type or N-type conductivity type by using ion implantation or impurity diffusion methods, and is made into an active element. ) method was used. However, there is an increase in the stray capacitance of the junction and a dimensional change during the partial oxidation process, which has been an obstacle to increasing the speed and density of the device.

5O8 (Ston 5a) is a technology that compensates for the above drawbacks.
There is a method of using pphire as a substrate. Since the substrate is an insulator, there is little stray capacitance, which is advantageous for increasing the speed and density of devices. On the other hand, since the substrate and the silicon epitaxial layer are dissimilarly bonded, there are many lattice defects at the substrate-silicon interface due to mismatching of lattice constants, which causes leakage current.

Furthermore, there are graphite epitaxy technology and bridging epitaxy technology as new single crystallization technologies for silicon films on insulating substrates.

The former is published in Agelide Physics Letters, Vol. 35, No. 1, pp. 71-74, 1979 (Applied Ph.
ics Letter++, Vol 35. Nl
1, pp. 71-74, 1979).
In this method, a VD film is grown on the entire surface of a substrate and is made into a single crystal by laser irradiation.

The latter is published in Japan Journal of Applied Physics, Volume 19, Pages 1, L23-L26, 1980.
Year (Japan Journal of Applte)
d Physics, Vol 19.

Number 1. ppL23-L26, 1980), according to which an insulating film is partially formed on a semiconductor single crystal substrate, a polycrystalline silicon film is further deposited on the entire surface of the substrate, and the substrate is seeded with a seed crystal by laser irradiation. The aim is to perform recrystallization to form a single crystal layer even on an insulating substrate. However, all of these methods tend to have problems with the degree of single crystallization, crystal defects on the insulating film, etc., and have not yet reached the point where device characteristics that can withstand practical use have been obtained.

For these techniques, there is a selection technique.

In this method, an insulating film is partially formed on a semiconductor single crystal substrate, and epitaxial growth is performed only on the exposed substrate region without depositing on the insulating film, which becomes the active region of the device. Since this epitaxial method uses homogeneous junctions, it exhibits extremely high quality crystallinity, and has the excellent characteristics of being simple and easy to mass-produce.

However, in the conventional selective epitaxial method, after forming an insulating film on a single crystal substrate, the insulating film is partially opened, so the interface between the insulating film and the epitaxial film is not affected by interfacial tension. 7 assets are formed due to strong impact. For example, when a (100) substrate is used, a 4-fold symmetrical facet with a (111) plane is generated, and when a (111) substrate is used, the surface is flat, but the insulating film-epitaxial film interface has an asymmetric shape of unevenness. Facets are formed. These causes come from the fact that the interface material is discontinuous.

Insulated gate field effect transistors formed on substrates using conventional methods have a low withstand voltage of the gate insulating film due to the unevenness of the surface, and are prone to wire breakage. The drawback is that a large leakage current occurs through the membrane interface.

An object of the present invention is to provide a method for manufacturing a selective epitaxial growth substrate that can obtain an extremely flat surface without depending on the orientation of the single crystal substrate.

That is, interfacial tension acts at the interface between different amounts of substances, and the formation of facets is influenced by the magnitude of this interfacial tension. The following relational expression called Young's equation holds true between the surface tension of the insulating film, the surface tension of the epitaxially grown silicon, and the interfacial tension between the insulating film and the epitaxially grown silicon.

r s, -rs-1-r, CO3θ=0
(1) r8゜: Interfacial tension between the insulating film and epitaxially grown silicon rs: Surface tension of silicon r□: Surface tension of the insulating film θ: To suppress the contact angle facet between the insulating film and epitaxially grown silicon It is necessary to bring the contact angle closer to 90CVc. Facets can be suppressed by bringing the interfacial tension rJ close to the surface tension r8 of silicon.

The interfacial tension between an insulating film and epitaxially grown silicon is very large, so if polycrystalline silicon is placed between them as a buffer layer, the interfacial tension between it and the epitaxially grown silicon will vary depending on the thickness of the polycrystalline silicon. As a result, they discovered that the size of the facets differed, leading to the present invention.

Differences between the conventional method and the method of the present invention will be explained in detail using figures.

FIG. 1 is a schematic cross-sectional view showing the shape of an epitaxially grown film on a (1oo) substrate formed by a conventional method. (
100) Insulating film 2 is partially opened in silicon substrate 1, silicon substrate surface 3 is exposed, and epitaxial silicon layer 4 is grown only in that region. At this time, a tapered four-fold symmetrical facet 5 is formed from the insulating film-epitaxial silicon interface.

FIG. 2 is a schematic cross-sectional view showing the shape of an epitaxial silicon film formed by the method of the present invention in comparison with FIG. An insulating film 2 is partially opened in a silicon substrate 1, and only the side walls of the insulating film are covered with polycrystalline silicon 13. When epitaxial silicon NI4 is selectively grown on the exposed silicon substrate surface 3, an extremely flat surface can be obtained without unevenness or facets near the insulating film interface.

Next, the present invention will be explained in detail using the drawings.

FIG. 3 is a schematic cross-sectional view showing the manufacturing process of a semiconductor substrate obtained by the present invention. for example,
A (100) silicon substrate 11 having a resistivity of approximately 1 Ω is thermally oxidized at 1000°C to form an S film with a thickness of approximately 1 μm.
After depositing the i0g film, an insulating film pattern 12 is formed on the Si having vertical walls, leaving about 500 layers of the Si0g film, using conventional photolithography and reactive ion etching. The 5to= film of about 5ooX is used as an etching mask for the polycrystalline silicon 13 later.

Next, polycrystalline silicon 13 is deposited to a thickness of about 800λ using the CVD method, and at the same time boron, which is a P-type impurity, is doped to about 10cIIL of B-3.
becomes. Subsequently, reactive ion etching techniques (e.g. anisotropic etching using CCl2F + Ox gas)
When polycrystalline silicon is etched anisotropically using etching, polycrystalline silicon remains at the initial thickness only on the side walls of the 5iO1 film 12. At this time, FIG. 3 [bl] is obtained.

Etching the Si0g film with a normal diluted hexafluoride solution exposes the silicon substrate surface 14, followed by 5iHz etching.
In the gas system composed of Cfl* and hydrogen, H (4 is
When selectively epitaxially grown at a temperature in the range of 900°C to 110σC in addition to Vo1
The two-tone width was approximately 300OA.

The thickness of the polycrystalline silicon layer was increased to 50OA using the same process.
In this case, the facet width was approximately 6000A. That is, when the polycrystalline silicon layer is thin, the interfacial tension between the insulating film and the polycrystalline silicon is sufficiently relaxed, and the interfacial tension between the polycrystalline silicon and the epitaxial silicon becomes large, resulting in a large facet. On the other hand, if the polycrystalline silicon layer is thick, the isolation area will increase in device isolation applications, which is one of the purposes of selective epitaxial growth.
It's inconvenient.

FIG. 4 shows the relationship between the thickness of the polycrystalline silicon and the width of the seven assets formed when the thickness of the insulating film is 1 μm.

Facet width decreases inversely with increasing polycrystalline silicon thickness. If the thickness of the polycrystalline silicon is gooA, the facet width will be reduced to about 3000λ, and even if it is thicker than xoooi, there will be no significant effect in reducing the facet width.

When the thickness of the polycrystalline silicon layer is 500 mm, the width of the 7 assets increases to about 6000 λ. The limit of device isolation using the LOCO8 method is a little over 2 μm. If the thickness of the isolation wall using normal photolithography is 1 μm, and the polycrystalline silicon layer has 500 layers, the isolation region will be approximately 2 μm including the facets on both sides. .2 μm. Therefore, when selective epitaxial growth is used as an element isolation method superior to LOCO8, the thickness of the polycrystalline silicon layer must be at least 500λ. Further, in the present invention, the plane orientation of the silicon substrate is (511).
, (110).

(111) etc. are also valid.

[Brief explanation of the drawing]

Figures 1 and 2 show recon substrates according to the conventional method and the present invention, 2... insulating film, 3... exposed silicon M plate, 4... epitaxial silicon. Layer, 5...Tapered facet, 11...
...Silicon substrate with a general surface, 12...
- Si (% insulating film, 13... polycrystalline silicon doped with impurities, 14... exposed silicon substrate, 15... i. epitaxial silicon layer, 16... ...The channel stopper regions are shown respectively. 1°, snow, °1.・1', :2:,, +, i:i7.1
−? Rumor pole 1 figure and half 2 figure 3 mouth

Claims (1)

[Claims] An insulating film is partially provided on a Si single crystal substrate, a polycrystalline silicon thin film with a thickness t of 500 k < 4 < 80 OA is formed only on the side wall of the insulating film, and silicon is formed only in the opening of the insulating film. A method for manufacturing a semiconductor substrate, characterized by epitaxially growing a film.