JPH07169709A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a conductive layer containing an impurity at a high concentration at an extremely shallow depth in a semiconductor substrate at the time of forming a conductive layer containing an impurity having an extremely large diffusion coefficient against the substrate on the surface of the substrate. CONSTITUTION:A first insulating film composed of a silicon nitride film 12 having a thickness of 400Angstrom is formed on the surface of a GaAs substrate 11 by using the plasma CVD method. The ion of zinc which is a P-type impurity having a large diffusion coefficient against the substrate 11 is implanted into the substrate 11 through the film 12. The thickness of the film 12 is decided so that the concentration peak of the injected impurity can come to the boundary between the substrate 11 and film 12. Then a second insulating film composed of a silicon nitride film 13 is formed on the film 12 by the plasma CVD method. Thereafter, a P-type conductive layer 14 is formed by heat-treating the substrate 11 for 5 minutes at 700 deg.C in a nitrogen atmosphere.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including a step of forming an impurity layer having a large diffusion coefficient on a semiconductor substrate.

[0002]

2. Description of the Related Art Conventionally, it is important to realize a shallow conductive layer in order to improve the performance of a semiconductor device. Impurities with a large diffusion coefficient can easily obtain a high-concentration conductive layer,
It is difficult to form a shallow conductive layer. In the related art, when an impurity layer having a large diffusion coefficient is formed on the surface of a semiconductor substrate, thermal diffusion or lamp heat treatment using coherent light is adopted.

A conventional method of manufacturing a semiconductor device will be described below with reference to FIGS. FIG. 5 is a diagram showing a heat diffusion method in a conventional semiconductor device manufacturing method. According to this method, the solid impurities 3 and the semiconductor substrate 2 are placed in a quartz ampoule 1, and the temperature of the heater 4 is raised to evaporate the solid impurities 3 and the semiconductor substrate 2
This is a method of diffusing impurities on the surface of. FIG. 6 shows a change in the impurity concentration profile with respect to the diffusion time when this thermal diffusion method is used. As shown in FIG. 6, when the diffusion time is lengthened, the impurity concentration on the substrate surface is increased, and the inclination of the pull file having a relatively low concentration is slowed down.

FIG. 7 is a diagram showing a method of lamp heat treatment of coherent light in a conventional method of manufacturing a semiconductor device. In this method, the semiconductor substrate 6 in which impurities are ion-implanted is used.
Is installed in the quartz tube 5 and heat-treated by the coherent light lamp 7. FIG. 8 shows the change in the impurity concentration profile with respect to the diffusion time in the case of this lamp heat treatment method. As shown in FIG. 8, when the diffusion time is lengthened, the impurity concentration on the substrate surface is lowered, and the inclination of the pull file having a relatively low concentration is slowed down. In addition,
The broken line in FIG. 8 is the impurity concentration profile before the heat treatment.

[0005]

In the above conventional method, in the case of thermal diffusion, it is difficult to control a low concentration profile although the concentration near the substrate surface is high. Further, it is difficult to control the concentration near the substrate surface depending on the state of the substrate surface. on the other hand,
In the case of lamp heat treatment, the steepness of the low-concentration profile is better than in the case of thermal diffusion, but a decrease in surface concentration appears and causes a problem in contact with an electrode metal that is formed later.

An object of the present invention is to solve the above-mentioned conventional problems. When forming a conductive layer of impurities having a large diffusion coefficient with respect to a semiconductor substrate on the surface of the semiconductor substrate, the semiconductor layer is formed at a position extremely shallow from the surface of the semiconductor substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a conductive layer having a high impurity concentration.

[0007]

In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention comprises forming a first insulating film on a semiconductor substrate and then forming a first insulating film and a surface of the semiconductor substrate. The highest concentration of impurities at the interface of the first
Ion implantation of impurities through the insulating film of
Forming a second insulating film on the insulating film, and then performing a high temperature heat treatment to form a conductive layer under the first insulating film.

[0008]

According to the present invention, when the conductive layer of impurities having a large diffusion coefficient with respect to the semiconductor substrate is formed on the surface of the semiconductor substrate, the first insulating film is formed via the first insulating film formed on the semiconductor substrate. Impurities are ion-implanted so that the concentration of impurities becomes the highest at the interface between the semiconductor substrate surface and the semiconductor substrate. afterwards,
After forming the second insulating film on the first insulating film, high temperature heat treatment is performed to form a conductive layer under the first insulating film. As a result, a conductive layer having a high impurity concentration can be formed at an extremely shallow position from the surface of the semiconductor substrate without causing a decrease in concentration near the surface of the substrate and deterioration of steepness in a low concentration region due to high temperature heat treatment.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1A to 1D are schematic sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. In FIG. 1, 11 is a GaAs substrate (semiconductor substrate), 12 is a silicon nitride film that is a first insulating film used as an ion implantation through film, and 13 is a silicon nitride film that is a second insulating film used as a heat treatment protection film. The film, 14 is a P-type conductive layer.

The method of manufacturing the semiconductor device of this embodiment will be described below. First, as shown in FIG.
On the aAs substrate 11, a silicon nitride film 12, which is a first insulating film, is formed in a thickness of 400 Å by a plasma CVD method. After that, zinc, which is a P-type impurity having a large diffusion coefficient, is ion-implanted into the GaAs substrate 11 through the silicon nitride film 12 (arrow in the figure). Next, as shown in FIG. 1B, the silicon nitride film 13 which is the second insulating film is replaced with the silicon nitride film 1 which is the first insulating film by the plasma CVD method.
Form on top of 2. Then, in a nitrogen atmosphere, 700 ℃, 5
Heat treatment is performed for a minute to form the P-type conductive layer 14.

FIG. 2A shows an implantation profile after ion implantation. In this embodiment, the silicon nitride film 12 and G
The implantation conditions are 80 keV, 8.0 × 10 ¹⁴ cm in order to have a concentration peak of zinc as an impurity at the interface with the aAs substrate 11.
^-2 . The thickness of the silicon nitride film 12 is determined so that the concentration peak of the implanted impurities is located at the interface between the silicon nitride film 12 and the GaAs substrate 11. As shown in FIG. 2A, the zinc concentration distribution in the silicon nitride film 12 is 1.9 × 10 at the interface with the GaAs substrate 11.
²⁰ cm ^-3 , 5.4 × 10 ¹⁹ c on the surface of GaAs substrate 11
m ⁻³ , and the concentration difference at this interface becomes important in the heat treatment in the next step.

FIG. 2B shows the carrier profile after the heat treatment, A is the case of this embodiment in which the first and second insulating films are formed, and B is the second insulating film as a comparative example. If only the first insulating film is formed without forming, C
Indicates the case where neither the first nor the second insulating film is formed. As shown in FIG. 2B, the P-type carrier profile of zinc after the heat treatment is different from that in the case A of this example in the case B in which only the first insulating film is formed and in the first and second cases.
If the insulating film is not formed, C is GaAs substrate 11
The carrier concentration near the surface is drastically reduced, and the steepness near the low concentration is deteriorated.

In this embodiment, a second insulating film (silicon nitride film 1) is formed on the first insulating film (silicon nitride film 12).
3) is formed, the outdiffusion of zinc in the first insulating film (silicon nitride film 12) is suppressed, and the diffusion to the semiconductor substrate (GaAs substrate 11) side is promoted. For this reason, a decrease in concentration near the substrate surface is suppressed. Further, unlike the first insulating film (silicon nitride film 12), the second insulating film (silicon nitride film 13) is not externally damaged, and therefore As dissociation from the GaAs substrate 11 is prevented, so that the The steepness near the concentration is not impaired.

As described above, according to this embodiment, the first insulating film (silicon nitride film 12) is used as the through injection film, and the second insulating film (silicon nitride film 13) is formed on the first insulating film. ) Is formed and a high temperature heat treatment is performed, a conductive layer of impurities having a large diffusion coefficient with respect to the semiconductor substrate (GaAs substrate 11) is formed on the surface of the semiconductor substrate. Conductive layer (P
A type conductive layer 14) can be formed. As a result, P
The performance of a semiconductor device having a shallow junction or a conductive layer such as an N-junction diode or a PN junction field effect transistor can be improved.

Next, as a second embodiment, a method for manufacturing a PN junction type diode will be described with reference to the drawings. FIG. 3 shows a P to which the method for manufacturing a semiconductor device according to the present invention is applied.
It is a cross-sectional schematic diagram which shows the manufacturing process of an N junction diode. In FIG. 3, 21 is a GaAs substrate into which silicon is selectively ion-implanted, 22 is a silicon nitride film that is a first insulating film, 23 is an N-type conductive layer, 24 is photoresist, and 25
Is a silicon nitride film as a second insulating film, 26 is a P-type conductive layer, 27 is an Au / AuGeNi N-type ohmic electrode, and 28 is Pt.
/ Ti is a P-type ohmic electrode.

The method of manufacturing the semiconductor device of this embodiment will be described below. First, as shown in FIG.
Ion-implanted GaAs with selective ion implantation
A silicon nitride film 22, which is a first insulating film, is deposited on the substrate 21 by plasma CVD at a rate of 400 Å and is placed in a nitrogen atmosphere.
A heat treatment is performed at 820 ° C. for 15 minutes to form the N-type conductive layer 23.

Next, as shown in FIG. 3B, selective ion implantation (arrow in the figure) of zinc, which is a P-type impurity, is performed using the photoresist 24 as an implantation mask. At this time, as in the case of the first embodiment, in order to have a concentration peak of zinc as an impurity at the interface between the silicon nitride film 22 and the N-type conductive layer 23 formed on the GaAs substrate 21, the implantation conditions are 80 keV, 8.0 × 10.
¹⁴ cm ^-2 .

Next, as shown in FIG. 3C, the photoresist 24 is removed, and a silicon nitride film 25 which is a second insulating film is deposited by plasma CVD at 600 Å. P-type conductive layer 2 after heat treatment for 5 minutes
6 is formed. Next, as shown in FIG. 3D, the silicon nitride films 22 and 25 of the first and second insulating films are removed, and the Au / AuGeNi N-type ohmic electrode 27 is made to have an N-type conductivity by a normal lift-off method. A Pt / Ti P-type ohmic electrode 28 is formed on the surface of the layer 23 and a P-type conductive layer 26 is formed.
To form a pn junction diode.

FIG. 4 shows the dependence of the junction capacitance (C _D ) of this PN junction diode on the bias voltage (V _R ). In FIG. 4, D shows this embodiment, and C is the one according to the conventional technique for comparison. As is clear from FIG. 4, the change in the PN junction capacitance with respect to the bias voltage is
This embodiment (D) is steeper than the change obtained by the conventional technique (E). Generally, the change of junction capacitance is P type and N
The larger the concentration difference between the molds and the steeper the P-type and N-type carrier profiles at the junction, the larger the difference.

As described above, according to this embodiment, GaA
The P-type conductive layer 2 is made of zinc having a large diffusion coefficient with respect to the substrate 21.
By using the double-layered insulating film composed of the silicon nitride films 22 and 25 when forming 6, the junction capacitance is large even in the PN junction diode, and good characteristics with a high capacitance change ratio can be obtained. In the above-mentioned embodiment, the semiconductor substrate is the GaAs substrate 11 and 21, and the impurity having a large diffusion coefficient with respect to the semiconductor substrate is zinc. However, in the case of the GaAs substrate 11 and 21, the impurity is irrespective of P type and N type. For example, it may be N-type sulfur. Further, the semiconductor substrate may be a single element semiconductor of silicon or another compound semiconductor. Furthermore, the first insulating film is not limited to the silicon nitride films 12 and 22, and may be a silicon oxide film, an aluminum oxide film, or the like. The second insulating film is not limited to the silicon nitride films 13 and 25, and may be another insulating film like the first insulating film.
It may be a refractory metal film such as i.

[0021]

According to the method of manufacturing a semiconductor device of the present invention, when the conductive layer of an impurity having a large diffusion coefficient with respect to the semiconductor substrate is formed on the surface of the semiconductor substrate, it is formed on the semiconductor substrate.
Impurities are ion-implanted into the interface between the first insulating film and the surface of the semiconductor substrate through the insulating film so as to have the highest impurity concentration. After that, a second insulating film is formed over the first insulating film, and then high temperature heat treatment is performed, so that a conductive layer is formed under the first insulating film. As a result, a conductive layer having a high impurity concentration can be formed at a position extremely shallow from the surface of the semiconductor substrate. As a result, the performance of a semiconductor device having a shallow junction or a conductive layer such as a PN junction diode or a PN junction field effect transistor can be improved.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a step showing the method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a diagram of an impurity injection profile and a carrier profile in the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing the manufacturing process of the PN junction diode in the second embodiment of the present invention.

FIG. 4 is a diagram showing the bias voltage dependence of the junction capacitance of the PN junction diode in the second embodiment of the present invention.

FIG. 5 is a diagram showing a method of thermal diffusion in a conventional method of manufacturing a semiconductor device.

FIG. 6 is a diagram showing a diffusion time dependency of a carrier profile in the case of a conventional thermal diffusion method.

FIG. 7 is a diagram showing a lamp heat treatment method of coherent light in a conventional semiconductor device manufacturing method.

FIG. 8 is a diagram showing a diffusion time dependence of a carrier profile in the case of a conventional lamp heat treatment method.

[Explanation of symbols]

 11, 21 GaAs substrate (semiconductor substrate) 12, 22 Silicon nitride film (first insulating film) 13, 25 Silicon nitride film (second insulating film) 14, 26 P-type conductive layer

Claims (1)

[Claims] 1. After forming a first insulating film on a semiconductor substrate, the first insulating film is formed on the interface between the first insulating film and the surface of the semiconductor substrate so that the concentration of impurities becomes highest. Ion-implanting the impurity via the step of forming a second insulating film on the first insulating film, and then performing high-temperature heat treatment to form a conductive layer under the first insulating film. A method of manufacturing a semiconductor device, comprising: