JP3224432B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a shallow P-type diffusion layer is formed stably and with good reproducibility.

[0002]

Conventionally, P type diffusion region which is a diffusion layer of a field-effect transistor of P-type conductivity type, boron ⁽¹¹ B ⁺⁾
Is obtained by ion implantation.

However, with the miniaturization of the field effect transistor to submicron, it becomes more difficult to form a shallow diffusion layer by boron ion implantation as a shallow diffusion layer serving as a source / drain becomes necessary. .

[0004] This is because boron is a light element, so that the implantation range is large, and a shallow diffusion layer is hardly obtained due to the effect of channeling.

[0005] This channeling means that when the incident direction of ions coincides with the direction of a cavity surrounded by an atomic row of a silicon substrate to be implanted, ions penetrate deeply into the crystal without receiving large scattering. It is a phenomenon.

Further, boron has a large diffusion coefficient in the heat treatment, so that re-diffusion is likely to occur, and it is difficult to form a shallow diffusion layer.

To form a shallow diffusion layer, it is sufficient to reduce the energy at the time of boron implantation. However, when the energy is reduced, the critical angle of channeling becomes large.
Channeling cannot be suppressed at an injection angle of about 7 degrees.

Further, instead of boron, a material having a large mass number ⁴⁹
A method of reducing the implantation depth by ion implantation of BF ₂ ⁺ has also been proposed.

When BF ₂ ⁺ usually has a larger beam current than B ^{+ and the} implantation depth is the same, the B
It is known that the depth is about １ ／ of that of ⁺ , and as a result, low acceleration implantation is effectively achieved.

However, when BF ₂ ⁺ is heat-treated at a temperature of 950 ° C. or lower, a phenomenon that ion-implanted fluorine remains in a silicon substrate occurs.

Further, channeling also occurs in the ion implantation of BF ₂ ⁺ , and it is difficult to form a shallow P-type diffusion layer.

FIG. 7 is a cross-sectional view showing an example of a conventional technique for suppressing the occurrence of channeling in boron implantation.

As shown in FIG. 7, a single crystal silicon substrate 1
After the formation of the gate electrode 2, silicon ions 5 are ion-implanted into the surface of the diffusion layer region 4 using the photoresist 3 when the gate electrode 2 was formed as a mask.

After the amorphous layer 6 is formed on the single crystal silicon substrate 1 by this ion implantation, P-type conductivity type ions are implanted.

The amorphous layer 6 suppresses the occurrence of channeling, so that a shallow diffusion layer can be obtained as a source / drain capable of coping with miniaturization of the field effect transistor to submicron.

However, the silicon ions 5 having a certain energy are applied to the single crystal silicon substrate 1 in the diffusion layer region 4.
Since the surface is destroyed, even after the heat treatment near the interface between the amorphous layer 6 and the single-crystal silicon substrate 1, the crystallinity is not completely recovered due to the occurrence of secondary defects, which lowers the junction breakdown voltage. There is a problem that causes. For example, it is described in the following literature. (C. Carter et
al. : Appl. Phys. Lett. , Vol4
4, No. 4 (1984) p. 459)

[0017]

As described above, in the conventional method, a P-type shallow diffusion layer serving as a source / drain of a field-effect transistor of a submicron device is formed without crystal defects and with good reproducibility. Thus, it is difficult to manufacture a field effect transistor.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a P-type conductive shallow diffusion layer as a submicron device without crystal defects and with good reproducibility by solving the above problems. is there.

[0019]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention employs the following method.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film and a gate electrode on a single crystal silicon substrate, and a step of oxidizing a diffusion layer region to be a P-type diffusion layer, and the upper surface and side walls of the gate electrode are performed. Forming a silicon oxide film by
Removing the silicon oxide film on the diffusion layer region, forming an amorphous silicon film on the entire surface, implanting P-type conductive ions over the entire surface, and removing the amorphous silicon film on the upper surface of the gate electrode; Forming an interlayer insulating film and performing a heat treatment.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be specifically described below with reference to the cross-sectional views of FIGS.

First, as shown in FIG. 1, a gate insulating film 15 is formed on a single crystal silicon substrate 1, and a polycrystalline silicon film is formed on the entire surface. Thereafter, the gate electrode 2 is formed by photo-etching the polycrystalline silicon film.

Next, as shown in FIG. 2, in order to oxidize the diffusion layer region 4 of the single crystal silicon substrate 1 and the upper and side walls of the gate electrode 2, a thermal oxidation furnace is used to oxidize the region under an oxygen / nitrogen atmosphere. An oxidation treatment is performed at a temperature of 1000 ° C. for 15 minutes to form a silicon oxide film 7.

Next, as shown in FIG. 3, the silicon oxide film 7 on the surface of the diffusion layer region 4 is removed with a hydrofluoric acid-based aqueous solution.

Since the oxidation rate of the polycrystalline silicon film is higher than that of the single crystal silicon substrate 1, the thickness of the silicon oxide film 7 on the top and side walls of the polycrystalline silicon film forming the gate electrode 2 is smaller than that of the single crystal silicon substrate. The thickness is larger than the oxide film thickness on the surface of the first diffusion layer region 4.

For this reason, even if the silicon oxide film 7 is etched to expose the surface of the single crystal silicon substrate 1 which is the diffusion layer region 4, the silicon oxide film 7 on the upper surface and the side wall of the gate electrode 2 remains.

When a high-melting point metal such as tungsten or molybdenum or a silicide thereof is used for the gate electrode 2, the diffusion layer region 4, the upper part of the gate electrode 2 and the side walls are oxidized to form a silicon oxide film. After masking the upper portion of the gate electrode 2 with photoresist, the diffusion layer region 4 is formed.
What is necessary is just to remove the silicon oxide film on the surface.

[0028] Then 10 ^{- 7} atmospheres following A in high vacuum
The amorphous silicon film 8 is formed to a thickness of 1 by the C sputtering method.
It is formed to a thickness of about 50 nm.

Thereafter, ⁴⁹ BF was used as the P-type conductive ion 9.
₂ ⁺ implantation energy 40 keV, implantation dose 3 × 15 at
Ions are implanted over the entire surface of the amorphous silicon film 8 under the condition of oms / cm ² .

As a result, as shown in FIG. 4, a P-type ion layer 10 serving as a source / drain of a field effect transistor can be formed on the single crystal silicon substrate 1.

Note that, even when ¹¹ B ⁺ is ion-implanted as the P-type conductive ions 9, it can also be realized by selecting the film thickness of the amorphous silicon film 8 and the acceleration energy of the P-type conductive ions.

Thereafter, as shown in FIG. 4, an SOG (spin-on-glass) 11 is applied on the entire surface as a coating insulating film. Due to the fluidity of the SOG 11, the SOG 11 is formed thick in the concave portion. That is, the thickness of the SOG 11 on the gate electrode 2 is smaller than that on the diffusion layer region 4.

Next, as shown in FIG. 5, until the surface of the amorphous silicon film 8 above the gate electrode 2 is exposed, the SO
G11 is dry-etched to remove S
OG11 is removed, and SO remaining in diffusion layer region 4 is further removed.
The amorphous silicon film 8 on the gate electrode 2 is etched and removed using G11 as a mask.

Thereafter, the SOG 11 on the diffusion layer region 4 is removed by etching with a hydrofluoric acid-based solution.

Next, as shown in FIG.
An interlayer insulating film 1 which is a silicon oxide film at a temperature of 60 ° C.
2 was formed to a thickness of 550 nm, and the temperature was 850 in a nitrogen atmosphere.
A heat treatment is performed at 30 ° C. for 30 minutes.

Thus, the P-type ion layer 1 in the diffusion layer region 4 is formed.
0 is activated to obtain a P-type diffusion layer 13 serving as a source / drain of a field-effect transistor.

Thereafter, a contact hole is opened in the interlayer insulating film 12 and a metal electrode 14 is formed in the same manner as in the usual method for manufacturing a field effect transistor.

When the resistance of the amorphous silicon film 8 on the diffusion layer region 4 is high, ions of P-type conductivity may be implanted into the contact hole region before forming the contact hole.

The method of forming the amorphous silicon film 8 is as follows.
Other than the sputtering method, another method such as a CVD method may be used.

[0040]

As described above, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a gate insulating film and a gate electrode on a single crystal silicon substrate, a step of forming a diffusion layer region to be a P-type diffusion layer and a step of forming a gate are performed. A step of oxidizing the surface and the side wall of the electrode, a step of removing an oxide film on the diffusion layer region, a step of forming amorphous silicon on the entire surface, a step of implanting P-type conductive ions over the entire surface, The method includes a step of removing the upper amorphous silicon, a step of forming an interlayer insulating film, and a heat treatment step.

As a result, a P-type conductivity diffusion layer having a depth of about 100 nm applicable to submicron devices can be formed as a source / drain of a field effect transistor without crystal defects and with good reproducibility. Have.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view illustrating the method for manufacturing a semiconductor device of the present invention;

FIG. 7 is a cross-sectional view illustrating a method of manufacturing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Single crystal silicon substrate 2 Gate electrode 4 Diffusion layer area 7 Silicon oxide film 8 Amorphous silicon film 9 P-type conductivity type ion 13 P-type diffusion layer 15 Gate insulating film

Claims (2)

(57) [Claims] A step of forming a gate insulating film and a gate electrode on a single crystal silicon substrate; forming a silicon oxide film by oxidizing a diffusion layer region to be a P-type diffusion layer and an upper surface and side walls of the gate electrode; a step of the removing the silicon oxide film of the diffusion layer region, an amorphous silicon film is formed on the entire surface, a step of implanting P-type conductivity type ions over the entire surface, the gate electrode from the diffusion layer region upper surface Thin top surface
A coating insulating film so that the coating insulating film is
The upper surface of the gate electrode is removed and the upper surface of the diffusion layer region remains.
And etch the remaining applied insulating film.
A method of manufacturing a semiconductor device, comprising: a step of removing an amorphous silicon film on an upper surface of a gate electrode as a etching mask; and a step of forming an interlayer insulating film and then performing a heat treatment. 2. The method according to claim 1, wherein the coating insulating film is formed by spin-on glass.
2. The manufacturing of a semiconductor device according to claim 1, wherein
Method.