JPH02119123A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02119123A JPH02119123A JP27222488A JP27222488A JPH02119123A JP H02119123 A JPH02119123 A JP H02119123A JP 27222488 A JP27222488 A JP 27222488A JP 27222488 A JP27222488 A JP 27222488A JP H02119123 A JPH02119123 A JP H02119123A
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial layer
- temperature
- grown
- epitaxial
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 abstract description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に高濃度不純
物領域を有する半導体基板上へのエピタキシャル層の形
成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an epitaxial layer on a semiconductor substrate having a high concentration impurity region.
従来、高濃度不純物領域を有する半導体基板上にエピタ
キシャル成長を行う場合は、例えば第３図に示すように
、ＳｉＨ４（モノシラン）のソースガスを使用し、まず
１１５０℃の温度でＨＣｅガスを用いて高濃度不純物領
域を含む基板全面をエツチングして表面を清浄とし、次
いで温度を１０５０°Ｃに下げてＳｉＨ４ガスを所定の
エピタキシャル膜厚になるまで流し、エピタキシャル層
を形成する方法が主に用いられていた。Conventionally, when epitaxial growth is performed on a semiconductor substrate having a high concentration impurity region, for example, as shown in FIG. The most commonly used method is to etch the entire surface of the substrate, including the impurity concentration region, to clean the surface, then lower the temperature to 1050°C, and flow SiH4 gas until a predetermined epitaxial film thickness is reached to form an epitaxial layer. Ta.
しかしながら、上述した従来のエピタキシャル成長の方
法では、ガスエツチング後所定の温度まで下げて１回の
エピタキシャル成長で所定の膜厚のエピタキシャル層を
形成していた為、エピタキシャル成長中、基板からの不
純物のオートドーピングの影響が強く、エピタキシャル
層中に高濃度下物層が形成されてしまう。However, in the conventional epitaxial growth method described above, an epitaxial layer with a predetermined thickness is formed in one epitaxial growth by lowering the temperature to a predetermined temperature after gas etching. The influence is strong, and a highly concentrated underlayer is formed in the epitaxial layer.
例えば２択的に高濃度のＮ型不純領域（例えば層抵抗３
０Ω／口）を形成したＰ型のシリコン基板（例えば比抵
抗１０Ω−Ｃ）上に厚さ２μｍのＮ型シリコンエピタキ
シャルＮ（例えば比抵抗１Ω−ｃｍ ）を形成した場合
、第４図に示すように、エピタキシャル層の厚さがオー
トドーピングにより実質的に減少する不純物分布となっ
ていた。この為高密度でかつ高速度の半導体装置を形成
するため薄いエピタキシャル層を用いる場合、耐圧等の
特性が劣化するという欠点があった。For example, alternatively a high concentration N-type impurity region (for example, layer resistance 3
When N-type silicon epitaxial N (for example, resistivity 1Ω-cm) with a thickness of 2 μm is formed on a P-type silicon substrate (for example, resistivity 10Ω-C) on which a silicon substrate (for example, resistivity 10Ω-cm) has been formed, as shown in FIG. Moreover, the thickness of the epitaxial layer had an impurity distribution that was substantially reduced by autodoping. For this reason, when a thin epitaxial layer is used to form a high-density and high-speed semiconductor device, there is a drawback that characteristics such as breakdown voltage deteriorate.
本発明の半導体装置の製造方法は、高濃度不純物領域を
有する半導体基板上にエピタキシャル層を形成する半導
体装置の製造方法におて、所定のエピタキシャル成長温
度より低い温度で第１のエピタキシャル層を形成したの
ち所定の温度で第２のエピタキシャル層を形成するもの
である。The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which an epitaxial layer is formed on a semiconductor substrate having a high concentration impurity region, and the first epitaxial layer is formed at a temperature lower than a predetermined epitaxial growth temperature. A second epitaxial layer is then formed at a predetermined temperature.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を説明するための温度と時間
との関係を示す図である。FIG. 1 is a diagram showing the relationship between temperature and time for explaining one embodiment of the present invention.
まず、１１５０℃の温度でＨＣ１！ガスを用いて高濃度
不純物領域を有する半導体基板全面をエツチングし表面
を清浄とする０次に温度を１０００℃まで下げＳｉＨ４
ガスを用いて厚さ０．２μｍ程度の第１のエピタキシャ
ル層の成長を行なう０次いで温度を所定の１０５０℃に
上げ、所定の膜厚になるまで第２のエピタキシャル層の
成長を行なう。First, HC1 at a temperature of 1150℃! The entire surface of the semiconductor substrate having a high concentration impurity region is etched using gas to clean the surface.The temperature is then lowered to 1000°C and SiH4 etched.
A first epitaxial layer having a thickness of about 0.2 μm is grown using gas.Then, the temperature is raised to a predetermined temperature of 1050° C., and a second epitaxial layer is grown until a predetermined film thickness is achieved.
本実施例により、選択的に高濃度のＮ型不純物領域（例
えば層抵抗３０Ω／口）を形成したＰ型のシリコン基板
（例えば比抵抗１０Ω−ｃｍ＞上に厚さ２μｍのＮ型シ
リコンエピタキシャル層（例えば比抵抗１Ω−Ω）を形
成した場合、第２図に示すように、基板とエピタキシャ
ル層界面とで不純物濃度が急峻となる、オートドーピン
グのきわめて少ない不純物分布を有するエピタキシャル
層を得ることが出来る。According to this example, an N-type silicon epitaxial layer with a thickness of 2 μm is formed on a P-type silicon substrate (for example, with a specific resistance of 10 Ω-cm) on which a high-concentration N-type impurity region (for example, a layer resistance of 30 Ω/hole) is selectively formed. (For example, when forming a resistivity of 1Ω-Ω), it is possible to obtain an epitaxial layer having an impurity distribution with very little autodoping, in which the impurity concentration becomes steep at the interface between the substrate and the epitaxial layer, as shown in Figure 2. I can do it.
上記実施例はガスエツチング工程を入れた場合について
説明したが、ガスエツチング工程を省略しても同様の効
果を有する。又、Ｐ型シリコン基板にＮ型高濃度不純物
領域を形成し、５ｉｌ１４を用いてＮ型シリコンをエピ
タキシャル成長する場合について説明したが、これに限
定されるものではなく、高濃度不純物領域の形成された
半導体基板上にシ’Ｊコ、ンガス（５ｉＨＣ１Ｂ、５ｉ
Ｈ２Ｃｅ２，５ｉＣｅ ４等）の種類をとわずエピタキ
シャル成長してもよい。Although the above embodiment has been described with reference to the case where a gas etching step is included, the same effect can be obtained even if the gas etching step is omitted. In addition, although the case where an N-type high concentration impurity region is formed on a P-type silicon substrate and N-type silicon is epitaxially grown using 5il14 has been described, the present invention is not limited to this. 5iHC1B, 5i
Any type of material (H2Ce2, 5iCe4, etc.) may be epitaxially grown.
以上説明したように本発明は、高濃度不純物領域を有す
る半導体基板上にエピタキシャル層を形成する場合、ま
ず所定のエピタキシャル成長温度より低い温度で第１の
エピタキシャル層を形成し、次いで所定の温度で所定の
膜厚まで第２のエピタキシャル層を形成することにより
、オートドーピングの少ない不純物分布を有するエピタ
キシャル層を形成できるなめ、耐圧等の特性劣化の少な
い高密度でかつ高速度の半導体装置を得ることができる
。As explained above, when an epitaxial layer is formed on a semiconductor substrate having a high concentration impurity region, the present invention first forms a first epitaxial layer at a temperature lower than a predetermined epitaxial growth temperature, and then a predetermined epitaxial layer is formed at a predetermined temperature. By forming the second epitaxial layer to a thickness of , it is possible to form an epitaxial layer having an impurity distribution with little autodoping, and therefore it is possible to obtain a high-density and high-speed semiconductor device with less deterioration of characteristics such as breakdown voltage. can.
第１図及び第２図は本発明の一実施例を説明するための
エピタキシャル層形成時の温度と時間との関係を示す図
及びエピタキシャル層中の不純物分布を示す図、第３図
及び第４図は従来例を説明するためのエピタキシャル形
成時の温度と時間との関係を示す図及びエピタキシャル
層中の不純物分布を示す図である。1 and 2 are diagrams illustrating the relationship between temperature and time during epitaxial layer formation, diagrams illustrating impurity distribution in the epitaxial layer, and Figures 3 and 4 for explaining one embodiment of the present invention. The figures are a diagram showing the relationship between temperature and time during epitaxial formation and a diagram showing impurity distribution in the epitaxial layer to explain a conventional example.
Claims (1)
ル層を形成する半導体装置の製造方法におて、所定のエ
ピタキシャル成長温度より低い温度で第１のエピタキシ
ャル層を形成したのち所定の温度で第２のエピタキシャ
ル層を形成することを特徴とする半導体装置の製造方法
。In a method of manufacturing a semiconductor device in which an epitaxial layer is formed on a semiconductor substrate having a high concentration impurity region, a first epitaxial layer is formed at a temperature lower than a predetermined epitaxial growth temperature, and then a second epitaxial layer is formed at a predetermined temperature. 1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27222488A JPH02119123A (en) | 1988-10-27 | 1988-10-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27222488A JPH02119123A (en) | 1988-10-27 | 1988-10-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02119123A true JPH02119123A (en) | 1990-05-07 |
Family
ID=17510843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27222488A Pending JPH02119123A (en) | 1988-10-27 | 1988-10-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02119123A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100712900B1 (en) * | 2006-07-06 | 2007-05-02 | 김영수 | Beverage extracting apparatus |
| JP2015213102A (en) * | 2014-05-01 | 2015-11-26 | 信越半導体株式会社 | Method for manufacturing epitaxial wafer |
| WO2017183277A1 (en) * | 2016-04-20 | 2017-10-26 | 信越半導体株式会社 | Method for producing epitaxial wafer |
-
1988
- 1988-10-27 JP JP27222488A patent/JPH02119123A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100712900B1 (en) * | 2006-07-06 | 2007-05-02 | 김영수 | Beverage extracting apparatus |
| JP2015213102A (en) * | 2014-05-01 | 2015-11-26 | 信越半導体株式会社 | Method for manufacturing epitaxial wafer |
| WO2017183277A1 (en) * | 2016-04-20 | 2017-10-26 | 信越半導体株式会社 | Method for producing epitaxial wafer |
| CN109075039A (en) * | 2016-04-20 | 2018-12-21 | 信越半导体株式会社 | The manufacturing method of epitaxial wafer |
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