JPH06112512A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which a highly accurate high- resistance epitaxially grown layer can be obtained. CONSTITUTION:Thermally oxidized films 11 are formed at the peripheral parts on the rear surface, side faces, and front surface of an N<+> layer (sub-wafer) 10 and a high-resistance N<-> layer 12 is formed on the surface of the layer 10 by epitaxial growth. Therefore, auto-doping of the layer 12 with an impurity gas can be prevented by the films 11 at the time of performing the epitaxial growth for forming the layer 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device (particularly a PIN diode) which suppresses auto-doping of an impurity gas from a sub-wafer to a high resistance epitaxial growth layer.

[0002]

2. Description of the Related Art As a semiconductor device, for example, a PIN diode is generally a sandwich structure having a low resistance P ⁺ layer on one side of a high resistance semiconductor layer (I layer) and a low resistance N ⁺ layer on the other side. Is a diode of
It is called an IN diode. In such a PIN diode, when a high resistance semiconductor layer is epitaxially grown on an N ⁺ layer to be a sub-wafer, the concentration of the impurity gas is lowered and the impurity gas (eg, P) emitted from the N ⁺ layer is reduced.
In order to prevent the I layer (N ⁻ layer) from being doped with a high concentration, the back surface of the N ⁺ layer 70 is coated with a CVD film 71 or the like as shown in FIG. N ⁺
An I layer 72 is epitaxially grown on the layer 70 [see (b) of FIG. 7].

[0003]

The back surface of the N ⁺ layer 70 is C
When covered with the VD film 71 or the like, the impurity gas does not come out from the back surface of the N ⁺ layer 70, but since the side surface of the N ⁺ layer 70 is exposed, the impurity gas comes out from the side surface. As a result, the impurity gas is doped into the I layer 72 on the N ⁺ layer 70, so that it is difficult to obtain an epitaxial growth layer (I layer) with few impurities and high resistance (200 Ω · cm or more).

Therefore, an object of the present invention is to provide a semiconductor device in which a highly accurate high resistance epitaxial growth layer can be obtained.

[0005]

In order to achieve the above object, a semiconductor device of the present invention comprises a sub-wafer, an insulating film provided on a back surface, a side surface, and at least a peripheral portion of the front surface of the sub-wafer, and a front surface of the sub-wafer. And a high resistance epitaxial growth layer formed on the substrate.

[0006] In the semiconductor device of the present invention, since the side as well as back surface of Sabuueha are covered with an insulating film, a high-resistance epitaxial growth layer on Sabuueha (I layer, N ^-
When a layer or the like) is grown, the impurity gas does not come out not only from the back surface but also from the side surface of the sub-wafer, and the impurity gas from the sub-wafer is hardly doped into the high resistance epitaxial growth layer. Moreover, since the insulating film is also provided on the peripheral portion of the surface of the sub-wafer, doping of the impurity gas from the boundary surface between the sub-wafer and the high resistance epitaxial growth layer can be prevented. Therefore, the high resistance epitaxial growth layer can be grown on the surface of the sub-wafer with high accuracy.

It is sufficient that the insulating film provided on the surface of the sub-wafer covers at least the peripheral portion of the surface in order to prevent the impurity gas from being doped into the high-resistance epitaxial growth layer from the interface between the sub-wafer and the high-resistance epitaxial growth layer. is there. However, as can be seen from the following examples, if the entire surface other than the surface for manufacturing the device is covered with the insulating film, the doping of the impurity gas can be prevented more effectively. Of course, in this case, the pattern of the insulating film provided on the surface of the sub-wafer may be variously changed according to the device structure and the like.

The high resistance as referred to in the present invention means
At least 200 Ω · cm or more, and the device of the present invention has a high resistance epitaxial growth layer of 200 Ω · cm or more.

[0009]

EXAMPLES The semiconductor device of the present invention will be described below based on examples. FIG. 1 shows an example of the basic structure of a semiconductor device. In this basic structure, a thermal oxide film (eg, SiO ₂ ) 11 as an insulating film is coated on the back surface, side surface, and peripheral portion of the surface of an N ⁺ layer (sub-wafer) 10 doped with Sb or the like, and the surface of the N ⁺ layer 10 is An N ⁻ layer 12 is epitaxially grown as a high resistance epitaxial growth layer thereon.

In order to obtain this basic structure, first, the entire surface of the N ⁺ layer 10 shown in FIG. 2A is coated with a thermal oxide film 11 [see FIG. 2B]. Next, the thermal oxide film 11 existing on the back surface, side surface, and peripheral portion of the surface of the N ⁺ layer 10
And the other thermal oxide film portion is removed by photolithography and photoetching [(c) of FIG. 2].
reference〕. Next, the N ⁻ layer 12 is epitaxially grown on the surface of the N ⁺ layer 10. At this time, since the back surface of the N ⁺ layer 10, the peripheral portion of the side surface and the surface is covered by a thermal oxide film 11, the impurity gas is not dissipated from the back surface and side surfaces of the N ⁺ layer 10, the impurity gas autodoping In addition, the impurity gas is not auto-doped into the N ⁻ layer 12 from the interface between the N ⁺ layer 10 and the N ⁻ layer 12. Therefore, the high resistance N ⁻ layer 12 containing few impurities can be accurately grown.

FIG. 3 shows another basic structure. In this basic structure, the thermal oxide film 21 is provided not only on the peripheral portion of the surface of the N ⁺ layer 20. The pattern of the thermal oxide film 21a on the surface conforms to the structure of the device, and for example, as shown in FIG. 4, circular regions (non-film portions) A are formed at regular intervals. The device is manufactured on this region A, and the device cannot be manufactured on the thermal oxide film 21a. In order to obtain the thermal oxide film 21a having such a pattern, etching may be performed using a photoresist corresponding to the pattern shown in FIG. 4 at the time of photolithography.

Next, FIG. 5 shows a PIN diode manufactured by using the basic structure shown in FIG. This diode is manufactured as follows. First, in the basic structure of FIG. 1, N ^- for passivation layer 12 (passivation), N ^- layer 12 on a silicon oxide film (Si
Coat with O ₂ ) 15. After etching the silicon oxide film 15 in a predetermined pattern, it is doped with P-type impurities to form an upper layer of the N ⁻ layer 12 as a P layer 16. Next, the upper electrode 17 made of, for example, aluminum is formed on the P layer 16. Although not shown in FIG. 5, the N ⁺ layer 10
The back surface of the N ⁺ layer 10 is ground together with the thermal oxide film 11 to thin the N ⁺ layer 10 to a predetermined thickness, and then a lower electrode is formed on the back surface of the N ⁺ layer 10.

A PI having the basic structure shown in FIG.
The N diode is shown in FIG. In this diode, similarly to the above, a silicon oxide film 25 is provided on the N ⁻ layer 22 for passivation, the upper layer of the N ⁻ layer 22 is a P layer 26, and the upper electrode 27 is provided on a portion where the oxide film 25 is not provided. Has been formed. Further, although not shown, N
The back surface side of the ⁺ layer 20 is ground together with the thermal oxide film 21, and a lower electrode is provided on this back surface side. In this example, the silicon oxide film 25 is located on the thermal oxide film 21a and does not exist on the device manufacturing region A.

[0014]

As described above, in the semiconductor device of the present invention, the insulating film is provided on the back surface, side surface, and at least the peripheral portion of the surface of the sub-wafer, and the high resistance epitaxial growth layer is formed on the surface of the sub-wafer. Therefore, it has the following effects. (1) Since the insulating film exists on the back surface and the side surface of the sub-wafer, it is possible to prevent the automatic doping of the impurity gas from the back surface and the side surface of the sub-wafer when the epitaxial growth layer is grown. (2) Since the insulating film is also present in the peripheral portion of the surface of the sub-wafer, it is possible to prevent the automatic doping of the impurity gas from the boundary surface between the epitaxial growth layer and the sub-wafer when the epitaxial growth layer is grown. (3) On the surface of the sub-wafer, in addition to the peripheral portion,
By providing the insulating film on all surfaces other than the device manufacturing surface, autodoping of the impurity gas can be prevented more effectively. (4) From (1) to (3), a high resistance epitaxial growth layer containing few impurities can be obtained with high precision.

[Brief description of drawings]

FIG. 1 is a basic structural cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process drawing for obtaining the basic structure shown in FIG.

FIG. 3 is a basic structural cross-sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 4 is a pattern diagram of an insulating film in the basic structure shown in FIG.

5 is a cross-sectional view of a PIN diode manufactured by using the basic structure shown in FIG.

6 is a cross-sectional view of a PIN diode manufactured by using the basic structure shown in FIG.

FIG. 7 is a process diagram for obtaining a basic structure of a semiconductor device according to a conventional example.

[Explanation of symbols]

10,20 N ⁺ layer (sub-wafer) 11,21 Thermal oxide film (insulating film) 12,22 N ⁻ layer (high resistance epitaxial growth layer)

Claims (2)

[Claims] 1. A sub-wafer, a back surface and a side surface of the sub-wafer,
And an insulating film provided on at least the peripheral portion of the surface,
A high resistance epitaxial growth layer formed on the surface of a sub-wafer. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a PIN diode.