JPH0864843A - Fabrication of zener diode - Google Patents
Fabrication of zener diodeInfo
- Publication number
- JPH0864843A JPH0864843A JP6201850A JP20185094A JPH0864843A JP H0864843 A JPH0864843 A JP H0864843A JP 6201850 A JP6201850 A JP 6201850A JP 20185094 A JP20185094 A JP 20185094A JP H0864843 A JPH0864843 A JP H0864843A
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial layer
- semiconductor substrate
- polycrystalline silicon
- silicon film
- zener diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 10
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 238000009792 diffusion process Methods 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 abstract description 10
- 229910045601 alloy Inorganic materials 0.000 abstract description 6
- 239000000956 alloy Substances 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 17
- 238000000034 method Methods 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66106—Zener diodes
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ツェナーダイオードの
製造方法に関し、特に低電圧のツェナーダイオードの製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a Zener diode, and more particularly to a method of manufacturing a low voltage Zener diode.
【０００２】[0002]
【従来の技術】ツェナーダイオードは、ＰＮ接合に逆バ
イアスを印可することで生じる降伏現象（ツェナー降
伏）を利用したダイオードである。ツェナー降伏を生じ
ている範囲では、電圧が一定値に保持される特性を有す
ることからツェナーダイオードは定電圧素子として使用
されている。2. Description of the Related Art A Zener diode is a diode which utilizes a breakdown phenomenon (Zener breakdown) which occurs when a reverse bias is applied to a PN junction. The Zener diode is used as a constant voltage element because it has a characteristic that the voltage is held at a constant value in the range where Zener breakdown occurs.
【０００３】一般にツェナーダイオードの構造は、図３
に示すように、高濃度の例えば、Ｎ + 型の半導体基板１
の表層部の選択箇所にＰ型の拡散領域２を設けると共
に、拡散領域２の周辺にＰ+ 型のガードリング３を設け
ている。そして、拡散領域２上にはＡｌ，Ａｇ等のアノ
ード用の電極４が形成されており、半導体基板１の裏面
にはカソード用の電極５が形成されている。なお、半導
体基板１の表面は、拡散領域２上に形成された電極４の
部分を除き、絶縁膜６で覆われている。Generally, the structure of a Zener diode is shown in FIG.
As shown in FIG. + Type semiconductor substrate 1
When a P-type diffusion region 2 is provided at a selected location on the surface layer of
And P around the diffusion region 2+ Type guard ring 3
ing. Then, an anode such as Al or Ag is formed on the diffusion region 2.
The back surface of the semiconductor substrate 1 on which the electrode 4 for the substrate is formed.
An electrode 5 for a cathode is formed on the. In addition, semi-conduction
The surface of the body substrate 1 has electrodes 4 formed on the diffusion region 2.
Except for the portion, it is covered with the insulating film 6.
【０００４】上述の構造を有するツェナーダイオードの
ツェナー電圧は、Ｎ+ 型半導体基板１に形成されるＰ型
の拡散領域２の深さと、Ｎ+ 型半導体基板１の不純物濃
度によって所定の値に決定される。その値は、拡散領域
２の深さを浅くし、かつ半導体基板１の不純物濃度を高
くするほど低く（低電圧化）することができ、現在で
は、ツェナー電圧が３〜５０Ｖのものが一般に量産され
ている。[0004] determining the Zener voltage of the Zener diode having the structure described above, the depth of the P-type diffusion region 2 formed in the N + semiconductor substrate 1, the impurity concentration of the N + -type semiconductor substrate 1 to a predetermined value To be done. The value can be lowered (lowered in voltage) as the depth of the diffusion region 2 is made shallower and the impurity concentration of the semiconductor substrate 1 is made higher. At present, a Zener voltage of 3 to 50 V is generally used for mass production. Has been done.
【０００５】ところで、近年の電子機器の駆動電圧の低
電圧化に伴いツェナー電圧が１〜２Ｖのツェナーダイオ
ードが求められている。この要望に答えるため、Ｐ型の
拡散領域２の深さとＮ+ 型半導体基板１の不純物濃度を
調整することで、ツェナー電圧が１〜２Ｖ程度となるツ
ェナーダイオードの開発若しくは製造が進められてい
る。Incidentally, with the recent decrease in the drive voltage of electronic equipment, a Zener diode having a Zener voltage of 1 to 2 V is required. In order to meet this demand, development or manufacture of a Zener diode having a Zener voltage of about 1 to 2 V is underway by adjusting the depth of the P type diffusion region 2 and the impurity concentration of the N + type semiconductor substrate 1. .
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、ツェナ
ーダイオードのツェナー電圧を１〜２Ｖ程度にするに
は、次の点から非常に困難であった。まず、ツェナー電
圧を決定する一つの要因である、高濃度のＮ+ 型の半導
体基板は、不純物を添加しながら種結晶を回転させて引
き上げる方法（ＣＺ法）で作成されたシリコン単結晶棒
をスライス加工することで製造されている。しかし、Ｃ
Ｚ法では、種結晶を回転しながら引き上げるので、不純
物濃度がシリコン単結晶棒内でばらつき、この結果、こ
れをスライス加工した半導体基板も不純物濃度がらつく
という問題を生じていた。このため、特に、ＣＺ法によ
る半導体基板を用いてツェナー電圧を１〜２Ｖの範囲に
精度よく制御することは非常に困難なものとなってい
た。さらには、ＣＺ法による半導体基板の表面層はダイ
オードの製造過程で結晶欠陥等の不具合を生じ易く、Ｐ
Ｎ接合の形成に悪影響を与えツェナー電圧を１〜２Ｖに
精度よく制御する妨げとなっていた。However, it was very difficult to set the Zener voltage of the Zener diode to about 1 to 2 V from the following points. First, for a high-concentration N + type semiconductor substrate, which is one factor that determines the Zener voltage, a silicon single crystal ingot produced by a method of rotating a seed crystal and pulling it while adding impurities (CZ method) is used. It is manufactured by slicing. But C
In the Z method, since the seed crystal is pulled up while rotating, the impurity concentration varies within the silicon single crystal ingot, and as a result, the semiconductor substrate obtained by slicing this has a problem that the impurity concentration also fluctuates. For this reason, it has been extremely difficult to control the Zener voltage in the range of 1 to 2 V with high accuracy by using the semiconductor substrate according to the CZ method. Furthermore, the surface layer of the semiconductor substrate formed by the CZ method is liable to cause defects such as crystal defects in the process of manufacturing the diode.
This adversely affects the formation of the N-junction and hinders accurate control of the Zener voltage to 1 to 2V.
【０００７】また、ツェナー電圧を決定する他の要因で
ある、Ｐ型の拡散領域は、通常イオン打込みにより形成
されるが、この方法では拡散領域を一定以下に浅くする
ことは困難であり、ツェナー電圧を１〜２Ｖの範囲に相
当する深さに制御するのは困難であった。仮に、拡散領
域を非常に浅くできたとしても、この拡散領域上に電極
を形成した際に生じるアロイスパイクによるショートを
充分に防止することはできなかった。The P-type diffusion region, which is another factor that determines the Zener voltage, is usually formed by ion implantation, but it is difficult to make the diffusion region shallower than a certain level by this method. It was difficult to control the voltage to a depth corresponding to the range of 1 to 2V. Even if the diffusion region could be made extremely shallow, it was not possible to sufficiently prevent a short circuit due to an alloy spike generated when an electrode was formed on the diffusion region.
【０００８】本発明の目的は、上述した問題点を除去し
たツェナーダイオードの製造方法を提供することにあ
る。An object of the present invention is to provide a method of manufacturing a Zener diode which eliminates the above-mentioned problems.
【０００９】[0009]
【課題を解決するための手段】本発明は、上記の目的を
達成するために次のような構成をとる。すなわち、本発
明のツェナーダイオードの製造方法は、一導電型の半導
体基板上に前記半導体基板と不純物濃度が同程度の一導
電型のエピタキシャル層を形成する工程と、前記エピタ
キシャル層の表面に設けた絶縁膜に開口部を形成する工
程と、前記開口部に他導電型の不純物を添加した多結晶
シリコン膜を堆積した後、前記多結晶シリコン膜中の前
記不純物を前記エピタキシャル層内に拡散させ他導電型
の拡散領域を形成する工程と、前記多結晶シリコン膜上
及び半導体基板の裏面に電極を被着する工程を具備する
ことを特徴とするものである。The present invention has the following constitution in order to achieve the above object. That is, the method for manufacturing a Zener diode of the present invention includes a step of forming an epitaxial layer of one conductivity type on a semiconductor substrate of one conductivity type having an impurity concentration approximately the same as that of the semiconductor substrate, and providing the surface of the epitaxial layer. Forming an opening in the insulating film, depositing a polycrystalline silicon film doped with impurities of other conductivity type in the opening, and diffusing the impurities in the polycrystalline silicon film into the epitaxial layer The method is characterized by including a step of forming a conductive type diffusion region and a step of depositing an electrode on the polycrystalline silicon film and the back surface of the semiconductor substrate.
【００１０】[0010]
【作用】本発明では、高不純物濃度の半導体基板上にさ
らに前記半導体基板と同程度の濃度のエピタキシャル層
を成長させているので、高濃度のエピタキシャル層には
結晶欠陥が少なく、しかも不純物濃度のばらつきもほと
んどないので精度よく半導体基板の不純物濃度を制御で
きる。According to the present invention, since the epitaxial layer having the same concentration as that of the semiconductor substrate is further grown on the semiconductor substrate having high impurity concentration, the high concentration epitaxial layer has few crystal defects and has high impurity concentration. Since there is almost no variation, the impurity concentration of the semiconductor substrate can be controlled accurately.
【００１１】また、本発明では、多結晶シリコン膜を形
成して該膜中の不純物をエピタキシャル層内に拡散領域
を形成しているのでその深さを浅くすることができる。
さらに、拡散領域の形成に利用した多結晶シリコン膜を
残して該膜上に電極を形成しているのでアロイスパイク
によるショートを防止することができる。このような方
法を利用することでツェナー電圧が１〜２Ｖ程度のツェ
ナーダイオードを得ることができる。Further, in the present invention, since the polycrystalline silicon film is formed and the impurity in the film is formed as the diffusion region in the epitaxial layer, the depth can be made shallow.
Furthermore, since the polycrystalline silicon film used for forming the diffusion region is left and the electrode is formed on the film, a short circuit due to alloy spike can be prevented. By using such a method, a zener diode having a zener voltage of about 1 to 2 V can be obtained.
【００１２】[0012]
【実施例】以下、本発明の実施例を図１を参照しつつ説
明する。尚、従来と同一部分や相当部分には同一の符号
を付している。まず、図１（ａ）に示すように、比抵抗
５〜１８ｍΩ・ｃｍのＮ型のシリコンからなる半導体基
板１上に、これと同程度の比抵抗３〜６ｍΩ・ｃｍで厚
さの１５〜２５μｍのエピタキシャル層７を成長させ
る。この半導体基板１は比抵抗５〜１８ｍΩ・ｃｍとす
るためＣＺ法で製造されたシリコン単結晶棒をスライス
加工したものが使用されている。エピタキシャル層７を
成長させることにより該層中には結晶欠陥がなく、しか
も不純物濃度のばらつきもない半導体基板を得ることが
できる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. Incidentally, the same reference numerals are given to the same or corresponding portions as in the conventional case. First, as shown in FIG. 1A, on a semiconductor substrate 1 made of N-type silicon having a specific resistance of 5 to 18 mΩ · cm, a specific resistance of 3 to 6 mΩ · cm and a thickness of 15 to A 25 μm epitaxial layer 7 is grown. As this semiconductor substrate 1, a silicon single crystal ingot manufactured by the CZ method is sliced so as to have a specific resistance of 5 to 18 mΩ · cm. By growing the epitaxial layer 7, it is possible to obtain a semiconductor substrate having no crystal defects in the layer and no variation in impurity concentration.
【００１３】次に、図１（ｂ）に示すように、エピタキ
シャル層７の表面に熱酸化により形成した酸化膜９に選
択的に窓を開け、Ｐ型不純物を拡散してガードリング３
を形成する。このガードリング３は、ツェナー降伏をで
きるだけ半導体基板の内部で起こさせるために設けられ
ている。次に、酸化膜９を除去した後、図１（ｃ）に示
すように、エピタキシャル層７の表面に絶縁膜６を設
け、フォトレジストプロセスで開口部１０を形成する。
この後、ＣＶＤ法により温度約６００〜７５０℃で、開
口部１０を覆うようにＰ型の不純物、例えばボロンを添
加した多結晶シリコン膜８を厚さ約１μｍ程度に堆積す
る。Next, as shown in FIG. 1B, a window is selectively opened in the oxide film 9 formed on the surface of the epitaxial layer 7 by thermal oxidation to diffuse the P-type impurities and to form the guard ring 3.
To form. The guard ring 3 is provided to cause Zener breakdown inside the semiconductor substrate as much as possible. Next, after removing the oxide film 9, as shown in FIG. 1C, the insulating film 6 is provided on the surface of the epitaxial layer 7, and the opening 10 is formed by a photoresist process.
After that, a polycrystalline silicon film 8 to which a P-type impurity such as boron is added is deposited to a thickness of about 1 μm by the CVD method at a temperature of about 600 to 750 ° C. so as to cover the opening 10.
【００１４】次に、図１（ｄ）に示すように、図示しな
いポリボロンフィルムを多結晶シリコン膜８上に塗布し
た後、８温度約８００〜８５０℃のＮ2 雰囲気中で熱処
理することにより多結晶シリコン膜８に含まれているＰ
型の不純物がエピタキシャル層７中に拡散し、深さ０．
２〜０．３μｍの拡散領域２が形成される。ここでＰ型
の不純物は多結晶シリコン膜８から拡散させているの
で、非常に浅い拡散領域２を形成することができるとと
もに、多結晶シリコン膜８は電極を形成する際に発生す
るアロイスパイクに対するバッファ層として利用でき
る。Next, as shown in FIG. 1D, a polyboron film (not shown) is applied on the polycrystalline silicon film 8 and then heat-treated in a N 2 atmosphere at a temperature of about 800 to 850 ° C. P contained in the polycrystalline silicon film 8
Type impurities diffuse into the epitaxial layer 7 to a depth of 0.
A diffusion region 2 of 2 to 0.3 μm is formed. Here, since the P-type impurity is diffused from the polycrystalline silicon film 8, a very shallow diffusion region 2 can be formed, and the polycrystalline silicon film 8 can prevent alloy spikes generated when forming an electrode. It can be used as a buffer layer.
【００１５】最後に、図１（ｅ）に示すように、蒸着等
により多結晶シリコン膜８上にＡｇまたはＡｌ等の金属
を被着しバンプ用、またはワイヤボンディング用の電極
４を形成するとともに、半導体基板１の裏面に電極５を
形成する。本実施例では、アロイスパイクによるショー
トをより確実に防止するため、多結晶シリコン膜８と電
極４の間に厚さ５００〜４０００オングストロームのＴ
ｉのバッファ層１１を設けている。Finally, as shown in FIG. 1E, a metal such as Ag or Al is deposited on the polycrystalline silicon film 8 by vapor deposition or the like to form electrodes 4 for bumps or wire bonding. The electrode 5 is formed on the back surface of the semiconductor substrate 1. In this embodiment, in order to prevent a short circuit due to alloy spikes more reliably, a T-thickness of 500 to 4000 angstrom is provided between the polycrystalline silicon film 8 and the electrode 4.
i buffer layer 11 is provided.
【００１６】次に、図２は本発明の方法により製造され
たツェナーダイオードのツェナー電圧を測定した結果を
示したグラフである。本測定ではＩZ＝２０ｍＡを流し
たときのツェナー電圧（ＶZ ）のばらつきを示してい
る。本測定から明らかなように本発明により製造された
ツェナーダイオードは、従来のツェナーダイオードに比
較して低いツェナー電圧にすることができる。Next, FIG. 2 is a graph showing the results of measuring the Zener voltage of the Zener diode manufactured by the method of the present invention. In this measurement, the variation of the Zener voltage (VZ) when IZ = 20 mA is shown is shown. As is apparent from this measurement, the Zener diode manufactured according to the present invention can have a lower Zener voltage than the conventional Zener diode.
【００１７】[0017]
【効果】上述のように、本発明の製造方法によれば、結
晶欠陥がほとんどなく、しかも不純物濃度のばらつきの
ない高濃度の半導体基板を得ることができる。また、多
結晶シリコン膜から不純物を拡散してエピタキシャル層
内に拡散領域を形成しているのでその深さを浅くするこ
とができる。さらに、拡散領域の形成に利用した多結晶
シリコン膜を残して電極を形成しているので、多結晶シ
リコン膜がアロイスパイクに対するバッファ層となりシ
ョートを防止することができる。As described above, according to the manufacturing method of the present invention, it is possible to obtain a high-concentration semiconductor substrate having few crystal defects and no variation in impurity concentration. Further, since the impurity is diffused from the polycrystalline silicon film to form the diffusion region in the epitaxial layer, the depth can be made shallow. Further, since the electrode is formed by leaving the polycrystalline silicon film used for forming the diffusion region, the polycrystalline silicon film serves as a buffer layer for alloy spikes and short circuit can be prevented.
【００１８】そして、上記の効果により低いツェナー電
圧のツェナーダイオードを得ることができる。A Zener diode having a low Zener voltage can be obtained by the above effect.
【図１】本発明の製造方法の実施例を説明する図面。FIG. 1 is a diagram illustrating an embodiment of a manufacturing method of the present invention.
【図２】ＩZ＝２０ｍＡを流したときのＶZのばらつきを
示すグラフ。FIG. 2 is a graph showing variations in VZ when IZ = 20 mA is applied.
【図３】従来のツェナーダイオードを示す説明図。FIG. 3 is an explanatory diagram showing a conventional Zener diode.
１ 半導体基板 ２ 拡散領域 ３ ガードリング ４，５ 電極 ６ 絶縁膜 ７ エピタキシャル層 ８ 多結晶シリコン膜 10 開口部 1 Semiconductor Substrate 2 Diffusion Region 3 Guard Ring 4, 5 Electrode 6 Insulating Film 7 Epitaxial Layer 8 Polycrystalline Silicon Film 10 Opening
Claims (1)
板と不純物濃度が同程度の一導電型のエピタキシャル層
を形成する工程と、前記エピタキシャル層の表面に設け
た絶縁膜に開口部を形成する工程と、前記開口部に他導
電型の不純物を添加した多結晶シリコン膜を堆積した
後、前記多結晶シリコン膜中の前記不純物を前記エピタ
キシャル層内に拡散させ他導電型の拡散領域を形成する
工程と、前記多結晶シリコン膜上及び半導体基板の裏面
に電極を被着する工程を具備することを特徴とするツェ
ナーダイオードの製造方法。1. A step of forming an epitaxial layer of one conductivity type having the same impurity concentration as that of the semiconductor substrate on a semiconductor substrate of one conductivity type, and forming an opening in an insulating film provided on the surface of the epitaxial layer. And a step of depositing a polycrystalline silicon film to which an impurity of another conductivity type is added in the opening, and then diffusing the impurities in the polycrystalline silicon film into the epitaxial layer to form a diffusion region of another conductivity type. And a step of depositing an electrode on the polycrystalline silicon film and on the back surface of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6201850A JPH0864843A (en) | 1994-08-26 | 1994-08-26 | Fabrication of zener diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6201850A JPH0864843A (en) | 1994-08-26 | 1994-08-26 | Fabrication of zener diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0864843A true JPH0864843A (en) | 1996-03-08 |
Family
ID=16447926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6201850A Pending JPH0864843A (en) | 1994-08-26 | 1994-08-26 | Fabrication of zener diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0864843A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006013129A (en) * | 2004-06-25 | 2006-01-12 | Nec Electronics Corp | Semiconductor apparatus |
| WO2015050776A1 (en) * | 2013-10-01 | 2015-04-09 | Vishay General Semiconductor Llc | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
| US9190470B2 (en) | 2013-11-06 | 2015-11-17 | Seiko Epson Corporation | Semiconductor device which suppresses fluctuations in breakdown voltage |
-
1994
- 1994-08-26 JP JP6201850A patent/JPH0864843A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006013129A (en) * | 2004-06-25 | 2006-01-12 | Nec Electronics Corp | Semiconductor apparatus |
| WO2015050776A1 (en) * | 2013-10-01 | 2015-04-09 | Vishay General Semiconductor Llc | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
| US9202935B2 (en) | 2013-10-01 | 2015-12-01 | Vishay General Semiconductor Llc | Zener diode haviing a polysilicon layer for improved reverse surge capability and decreased leakage current |
| US9331142B2 (en) | 2013-10-01 | 2016-05-03 | Vishay General Semiconductor Llc | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
| CN105556679A (en) * | 2013-10-01 | 2016-05-04 | 威世通用半导体公司 | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
| EP3053198A1 (en) * | 2013-10-01 | 2016-08-10 | Vishay General Semiconductor LLC | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
| JP2016536778A (en) * | 2013-10-01 | 2016-11-24 | ヴィシェイ ジェネラル セミコンダクター，エルエルシーＶｉｓｈａｙ Ｇｅｎｅｒａｌ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ，Ｌｌｃ | Zener diode with polysilicon layer with improved reverse surge capability and reduced leakage current |
| EP3053198A4 (en) * | 2013-10-01 | 2017-05-03 | Vishay General Semiconductor LLC | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
| US9966429B2 (en) | 2013-10-01 | 2018-05-08 | Vishay General Semiconductor Llc | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
| US9190470B2 (en) | 2013-11-06 | 2015-11-17 | Seiko Epson Corporation | Semiconductor device which suppresses fluctuations in breakdown voltage |
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