JPH0464179B2 - - Google Patents
Info
- Publication number
- JPH0464179B2 JPH0464179B2 JP59030653A JP3065384A JPH0464179B2 JP H0464179 B2 JPH0464179 B2 JP H0464179B2 JP 59030653 A JP59030653 A JP 59030653A JP 3065384 A JP3065384 A JP 3065384A JP H0464179 B2 JPH0464179 B2 JP H0464179B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- region
- base
- polycrystalline semiconductor
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000012535 impurity Substances 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Description
【発明の詳細な説明】
産業上の利用分野
この発明は、ベース抵抗の低減をはつたバイポ
ーラトランジスタの製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a method of manufacturing a bipolar transistor with reduced base resistance.
従来例の構成とその問題点
バイポーラトランジスタの低雑音化、高周波化
を図るために、たとえばベース抵抗を下げること
が提唱されている。Conventional configurations and their problems In order to reduce the noise and increase the frequency of bipolar transistors, it has been proposed, for example, to lower the base resistance.
この方法の一つとして、たとえば、ベース領域
の不純物濃度を高くする方法があるが、この方法
には、活性ベース領域の不純物濃度も高くなるた
めエミツタからのキヤリアの注入効率が低くなり
電流増幅率hFEが低下する問題点がある。 One method for this, for example, is to increase the impurity concentration in the base region, but this method also increases the impurity concentration in the active base region, which lowers the carrier injection efficiency from the emitter and reduces the current amplification factor. h There is a problem that FE decreases.
この問題点を解決するため、さらに改良された
方法として、活性ベース領域を低不純物濃度と
し、ベースコンタクト領域を高不純物濃度にする
方法が提案されている。しかし、ベースコンタク
ト領域の不純物濃度を高くしすぎると格子欠陥や
転位などの発生が顕著となり結晶の完全性が得ら
れず１／雑音が大きくなるという不都合が生じ
る。 In order to solve this problem, a method has been proposed as a further improved method in which the active base region is made to have a low impurity concentration and the base contact region is made to be made to have a high impurity concentration. However, if the impurity concentration in the base contact region is made too high, the occurrence of lattice defects, dislocations, etc. becomes noticeable, resulting in the disadvantage that crystal perfection cannot be obtained and 1/noise increases.
これらの不都合を排除してベース抵抗を下げる
方法として、第１図に示すように、ベース電極と
して多結晶シリコン層を使用することにより、ベ
ース電極をエミツタ領域に近づけベースコンタク
ト領域でのベース抵抗を下げる方法がとられてい
る。 As a method to eliminate these disadvantages and lower the base resistance, as shown in Figure 1, by using a polycrystalline silicon layer as the base electrode, the base electrode can be brought closer to the emitter region and the base resistance in the base contact region can be reduced. There are ways to lower it.
この構造のトランジスタは、高不純物濃度のｎ
形シリコン基板１の上に低不純物濃度のｎ形のエ
ピタキシヤル層２を成長させ、この上に絶縁膜３
（図示していないがエミツタ領域形成部分の上に
もある）をマスクとしてｐ形の不純物がドープさ
れ、ベース電極となる多結晶シリコン膜４を選択
的に形成し、イオン注入と多結晶シリコン膜４か
らの不純物拡散によりベース領域５を作るととも
に、多結晶シリコン膜４の表面とベース領域５の
表面の一部分を酸化シリコン膜６に変換し、次
に、エミツタ領域形成部分の上の絶縁膜（図示せ
ず）を除去し、酸化シリコン膜６をマスクとして
ｎ形不純物をドープした多結晶シリコン膜７を選
択的に形成し、この多結晶シリコン膜７からの不
純物拡散によりエミツタ領域８を作り込み、最後
に、多結晶シリコン膜４と７に電極９を形成する
過程を経ることによつて実現される。 A transistor with this structure has a high impurity concentration
An n-type epitaxial layer 2 with a low impurity concentration is grown on a silicon substrate 1, and an insulating film 3 is formed on this.
(Although not shown, it is also on the emitter region formation part) is used as a mask to selectively form a polycrystalline silicon film 4 that is doped with p-type impurities and will become a base electrode. A base region 5 is formed by impurity diffusion from 4, the surface of the polycrystalline silicon film 4 and a part of the surface of the base region 5 are converted into a silicon oxide film 6, and then an insulating film ( (not shown) is removed, a polycrystalline silicon film 7 doped with n-type impurities is selectively formed using the silicon oxide film 6 as a mask, and an emitter region 8 is formed by diffusion of impurities from this polycrystalline silicon film 7. , and finally by forming electrodes 9 on polycrystalline silicon films 4 and 7.
ところで、このトランジスタの製造方法では、
マスク合せ精度の関係からエミツタ領域８の端か
らベース電極用多結晶シリコン膜４の端までの距
離Ａが1μm以上離れてしまう。この距離は、ベー
ス抵抗を低下させる観点からみると十分に短かい
距離とは言い難いためベース抵抗が十分に低くな
らない不都合が生じる。 By the way, in this method of manufacturing transistors,
Due to mask alignment accuracy, the distance A from the end of the emitter region 8 to the end of the base electrode polycrystalline silicon film 4 is 1 μm or more. This distance cannot be said to be a sufficiently short distance from the viewpoint of lowering the base resistance, resulting in the inconvenience that the base resistance cannot be lowered sufficiently.
発明の目的
本発明は上記の不都合を排除することができる
トランジスタ、すなわち、エミツタ領域の端から
ベース電極用多結晶シリコン層までの距離を1μm
以内に近づけベース抵抗を十分に下げることがで
きるトランジスタの製造方法を提供するものであ
る。Purpose of the Invention The present invention provides a transistor that can eliminate the above-mentioned disadvantages, that is, the distance from the edge of the emitter region to the polycrystalline silicon layer for the base electrode is 1 μm.
The present invention provides a method for manufacturing a transistor that can sufficiently lower the base resistance by bringing the base resistance closer to the lower limit.
発明の構成
コレクタ領域となる一導電形の半導体層上に逆
導電形の不純物をドープした第１多結晶半導体層
を選択的に形成し、同第１多結晶半導体層内の不
純物を前記半導体層へ拡散させベース領域を形成
すると同時に、前記第１多結晶半導体層の表面を
第１酸化物に変換する工程、前記ベース領域上に
選択的にエミツタ形成用の開口を形成し、前記開
口の底面および側面を第２酸化物に変換する工
程、垂直エツチング法により前記開口の底面の第
２酸化物を除去する工程、前記開口内に前記一導
電形の不純物をドープした第２多結晶半導体層を
選択的に形成し、同第２多結晶半導体層内の不純
物を前記ベース領域内に拡散させエミツタ領域を
形成する工程、前記第１多結晶半導体層と前記第
２多結晶半導体層に電極を形成する工程を経てバ
イポーラトランジスタを作り込むものである。こ
の方法によれば、ベース電極用多結晶半導体層の
端部がエミツタ領域から1μm以内の所に位置した
トランジスタが得られ、ベース抵抗を大きく下げ
ることができる。Structure of the Invention A first polycrystalline semiconductor layer doped with an impurity of an opposite conductivity type is selectively formed on a semiconductor layer of one conductivity type serving as a collector region, and the impurity in the first polycrystalline semiconductor layer is removed from the semiconductor layer. a step of converting the surface of the first polycrystalline semiconductor layer into a first oxide at the same time as forming a base region; selectively forming an opening for forming an emitter on the base region; and converting the side surfaces into a second oxide, removing the second oxide at the bottom of the opening by vertical etching, and adding a second polycrystalline semiconductor layer doped with impurities of one conductivity type into the opening. selectively forming and diffusing impurities in the second polycrystalline semiconductor layer into the base region to form an emitter region; forming electrodes in the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer; Bipolar transistors are fabricated through the following steps. According to this method, a transistor can be obtained in which the end of the polycrystalline semiconductor layer for the base electrode is located within 1 μm from the emitter region, and the base resistance can be greatly reduced.
実施例の説明
本発明のトランジスタの製造方法の一実施例を
第２図ａ〜ｆの断面図を参照にして説明する。DESCRIPTION OF EMBODIMENTS An embodiment of the method for manufacturing a transistor according to the present invention will be described with reference to cross-sectional views of FIGS. 2a to 2f.
まず、コレクタ領域となる高不純物濃度のｎ形
のシリコン基板１を準備し、その上に低不純物濃
度のｎ形のエピタキシヤル層２を１〜20μmの厚
さに成長させる。この後に、表面に酸化シリコン
膜１０を形成し、周知の写真蝕刻法によりベース
領域となる部分の酸化シリコン膜１０を除去す
る。次に、表面全域に多結晶シリコン膜１１を形
成し、イオン注入法により多結晶シリコン膜１１
の中にボロンイオンB+を注入する。この後、ベ
ース領域を形成するべき部分およびベース電極の
コンタクト部分にある多結晶シリコン膜１１のみ
を残し、他を全て除去する。次に、多結晶シリコ
ン膜１１の中にドープされたボロンの不純物をｎ
形エピタキシヤル層中に酸化性雰囲気中で拡散さ
せてベース領域５を形成すると同時に、多結晶シ
リコン膜１１の表面を酸化シリコン膜１２に変換
する。この時、酸化シリコン膜１０の表面にも酸
化シリコン膜１２が形成される。〔第２図ａ〕。 First, an n-type silicon substrate 1 with a high impurity concentration that will become a collector region is prepared, and an n-type epitaxial layer 2 with a low impurity concentration is grown thereon to a thickness of 1 to 20 μm. Thereafter, a silicon oxide film 10 is formed on the surface, and a portion of the silicon oxide film 10 that will become a base region is removed by a well-known photolithography method. Next, a polycrystalline silicon film 11 is formed over the entire surface, and an ion implantation method is used to form the polycrystalline silicon film 11.
Inject boron ions B + into the Thereafter, only the polycrystalline silicon film 11 in the portion where the base region is to be formed and the contact portion of the base electrode is left, and all other parts are removed. Next, the boron impurity doped into the polycrystalline silicon film 11 is
The base region 5 is formed by diffusion into the epitaxial layer in an oxidizing atmosphere, and at the same time the surface of the polycrystalline silicon film 11 is converted into a silicon oxide film 12. At this time, a silicon oxide film 12 is also formed on the surface of the silicon oxide film 10. [Figure 2a].
次に、写真蝕刻法によりベース領域上で、しか
もエミツタ領域を形成するべき部分の上に位置す
る酸化シリコン膜１２と多結晶シリコン膜１１を
選択的に除去して開口１３を形成する。そして熱
酸化法により表面全域を酸化することにより、開
口１３の底面と側面をも覆う酸化シリコン膜１４
を形成する〔第２図ｂ〕。 Next, an opening 13 is formed by selectively removing the silicon oxide film 12 and the polycrystalline silicon film 11 located on the base region and on the portion where the emitter region is to be formed by photolithography. Then, by oxidizing the entire surface using a thermal oxidation method, a silicon oxide film 14 that also covers the bottom and side surfaces of the opening 13 is formed.
[Figure 2b].
この後、プラズマエツチング法で酸化シリコン
膜１４を垂直方向にエツチングすることにより、
開口１３の底面にシリコン方面を露出させる。こ
の時開口１３の側面には酸化シリコン膜１４が残
る〔第２図ｃ〕。 Thereafter, by vertically etching the silicon oxide film 14 using a plasma etching method,
The silicon side is exposed at the bottom of the opening 13. At this time, the silicon oxide film 14 remains on the side surface of the opening 13 (FIG. 2c).
次に、表面全或に多結晶シリコン膜１５を形成
し、イオン注入法により多結晶シリコン膜１５の
中に砒素イオンAs+をイオン注入しさらに熱処理
を施すことによりエミツタ領域８を形成する。こ
の時エミツタの拡散の横広がりを開口窓１３の側
面の酸化シリコン膜１４の厚さより小さくする。
〔第２図ｄ〕。 Next, a polycrystalline silicon film 15 is formed over the entire surface, and arsenic ions As + are implanted into the polycrystalline silicon film 15 by an ion implantation method, followed by heat treatment to form an emitter region 8. At this time, the lateral spread of the emitter diffusion is made smaller than the thickness of the silicon oxide film 14 on the side surface of the opening window 13.
[Figure 2 d].
この後、エミツタ領域８の上の多結晶シリコン
膜１５のみ残し、他を全て除去する〔第２図ｅ〕。 Thereafter, only the polycrystalline silicon film 15 on the emitter region 8 is left and all the others are removed [FIG. 2e].
多結晶シリコン膜１１の上の酸化シリコン膜１
２を選択的に除去し、金属電極用のコンタクト窓
をあけ、この部分とエミツタ電極となる多結晶シ
リコン膜１５の双方の上に高純度のアルミニウム
Alあるいは重量比で１％のシリコンSiを含んだ
アルミニウムを用いて電極９を形成することによ
りトランジスタが形成される〔第２図ｆ〕。 Silicon oxide film 1 on polycrystalline silicon film 11
2 is selectively removed, a contact window for the metal electrode is opened, and high-purity aluminum is deposited on both this part and the polycrystalline silicon film 15 that will become the emitter electrode.
A transistor is formed by forming the electrode 9 using Al or aluminum containing 1% silicon by weight (FIG. 2f).
このように本発明のトランジスタの製造方法で
は、エミツタ形成用の開口窓の側面の酸化シリコ
ン膜の厚さが形成条件により自由にコントロール
できるため、ベース電極用多結晶シリコン膜をエ
ミツタ領域の0.1〜1μm以内の近傍にまで近づけ
ることができ、ベースコンタクト領域の抵抗がほ
とんど無視できベース抵抗を大幅に低減すること
ができる。 In this way, in the transistor manufacturing method of the present invention, the thickness of the silicon oxide film on the side surface of the opening window for emitter formation can be freely controlled depending on the formation conditions. It is possible to get as close as 1 μm or less, and the resistance of the base contact region can be almost ignored, making it possible to significantly reduce the base resistance.
発明の効果
以上説明したように本発明のトランジスタの製
造方法によれば、シリコンの結晶性を損なうこと
なくベース抵抗の低減を図ることができ、トラン
ジスタの雑音特性および高周波特性を改善するこ
とができる。Effects of the Invention As explained above, according to the method for manufacturing a transistor of the present invention, the base resistance can be reduced without impairing the crystallinity of silicon, and the noise characteristics and high frequency characteristics of the transistor can be improved. .
第１図は従来の高周波トランジスタの断面構造
図、第２図ａ〜ｆは本発明のベース抵抗低減のト
ランジスタの一実施例の断面図である。
１……ｎ形シリコン基板、２……ｎ形エピタキ
シヤル層、３……絶縁膜、４，７，１１，１５…
…多結晶シリコン膜、５……ベース領域、６，１
０，１２，１４……酸化シリコン膜、８……エミ
ツタ領域、９……電極、１３……開口窓。
FIG. 1 is a cross-sectional structural diagram of a conventional high-frequency transistor, and FIGS. 2 a to 2-f are cross-sectional diagrams of an embodiment of a transistor with reduced base resistance according to the present invention. 1... N-type silicon substrate, 2... N-type epitaxial layer, 3... Insulating film, 4, 7, 11, 15...
... Polycrystalline silicon film, 5 ... Base region, 6, 1
0, 12, 14...Silicon oxide film, 8...Emitter region, 9...Electrode, 13...Opening window.
Claims (1)
逆導電形の不純物をドープした第１多結晶半導体
層を選択的に形成し、同第１多結晶半導体層内の
不純物を前記半導体層へ拡散させベース領域を形
成すると同時に、前記第１多結晶半導体層の表面
を第１酸化物に変換する工程、前記ベース領域上
に選択的にエミツタ形成用の開口を形成し、前記
開口の底面および側面を第２酸化物に変換する工
程、垂直エツチング法により前記開口の底面の第
２酸化物を除去する工程、前記開口内に前記一導
電形の不純物をドープした第２多結晶半導体層を
選択的に形成し、同第２多結晶半導体層内の不純
物を前記ベース領域内に拡散させエミツタ領域を
形成する工程、前記第１多結晶半導体層と前記第
２多結晶半導体層上に電極を形成する工程を具備
することを特徴とするトランジスタの製造方法。1. A first polycrystalline semiconductor layer doped with impurities of the opposite conductivity type is selectively formed on a semiconductor layer of one conductivity type that will serve as a collector region, and the impurity in the first polycrystalline semiconductor layer is diffused into the semiconductor layer. a step of converting the surface of the first polycrystalline semiconductor layer into a first oxide at the same time as forming a base region; selectively forming an opening for forming an emitter on the base region; a step of converting the second oxide into a second oxide, a step of removing the second oxide at the bottom of the opening by a vertical etching method, and a step of selectively converting the second polycrystalline semiconductor layer doped with the impurity of one conductivity type into the opening. forming an emitter region by diffusing impurities in the second polycrystalline semiconductor layer into the base region, and forming electrodes on the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer. A method for manufacturing a transistor, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3065384A JPS60175452A (en) | 1984-02-20 | 1984-02-20 | Manufacture of transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3065384A JPS60175452A (en) | 1984-02-20 | 1984-02-20 | Manufacture of transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60175452A JPS60175452A (en) | 1985-09-09 |
| JPH0464179B2 true JPH0464179B2 (en) | 1992-10-14 |
Family
ID=12309747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3065384A Granted JPS60175452A (en) | 1984-02-20 | 1984-02-20 | Manufacture of transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60175452A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62150748A (en) * | 1985-12-24 | 1987-07-04 | Rohm Co Ltd | Wiring formation of semiconductor device |
| JPS62150746A (en) * | 1985-12-24 | 1987-07-04 | Rohm Co Ltd | Wiring formation of semiconductor device |
| JP2641856B2 (en) * | 1987-02-23 | 1997-08-20 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JPH03256332A (en) * | 1990-03-06 | 1991-11-15 | Sharp Corp | Vertical bipolar transistor element and bi-cmos inverter using the same element |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5427774A (en) * | 1977-08-03 | 1979-03-02 | Nec Corp | Semiconductor device |
| JPS5470776A (en) * | 1977-11-16 | 1979-06-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its manufacture |
| JPS57128063A (en) * | 1981-01-30 | 1982-08-09 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1984
- 1984-02-20 JP JP3065384A patent/JPS60175452A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5427774A (en) * | 1977-08-03 | 1979-03-02 | Nec Corp | Semiconductor device |
| JPS5470776A (en) * | 1977-11-16 | 1979-06-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its manufacture |
| JPS57128063A (en) * | 1981-01-30 | 1982-08-09 | Toshiba Corp | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60175452A (en) | 1985-09-09 |
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