JPH0464180B2 - - Google Patents
Info
- Publication number
- JPH0464180B2 JPH0464180B2 JP59036668A JP3666884A JPH0464180B2 JP H0464180 B2 JPH0464180 B2 JP H0464180B2 JP 59036668 A JP59036668 A JP 59036668A JP 3666884 A JP3666884 A JP 3666884A JP H0464180 B2 JPH0464180 B2 JP H0464180B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor layer
- emitter
- base
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000012535 impurity Substances 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
この発明は、ベース抵抗の低減をはかつたバイ
ポーラトランジスタおよびその製造方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a bipolar transistor with reduced base resistance and a method for manufacturing the same.
従来例の構成とその問題点
バイポーラトランジスタの低雑音化、高周波化
を図るために、一方法として例えばベース抵抗を
下げることが提案されている。Conventional Structures and Their Problems In order to reduce the noise and increase the frequency of bipolar transistors, it has been proposed to lower the base resistance, for example, as a method.
この方法の１つとして、たとえば、ベース領域
の不純物濃度を高くする方法があるが、この場
合、ベースコンタクト領域とともに活性ベース領
域の不純物濃度も高くなるためエミツタからのキ
ヤリアの注入効率が悪くなり電流増幅率hFEが低
下する欠点がある。 One method for this is, for example, to increase the impurity concentration in the base region, but in this case, the impurity concentration in the active base region as well as the base contact region becomes high, so the efficiency of carrier injection from the emitter deteriorates and the current There is a drawback that the amplification factor h FE decreases.
そこで、上記の問題点を解決す構造として活性
ベース領域は低不純物濃度で、ベースコンタクト
領域は高不純物濃度にするいわゆるグラフトベー
ス構造が提案されている。しかし、ブースコンタ
クト領域の不純物濃度を高くしすぎると格子欠陥
や転位などが発生し結晶の完全性が得られず１／
雑音が大きくなるという欠点が生じる。 Therefore, as a structure to solve the above problems, a so-called graft base structure has been proposed in which the active base region has a low impurity concentration and the base contact region has a high impurity concentration. However, if the impurity concentration in the booth contact region is too high, lattice defects and dislocations will occur, making it impossible to obtain crystal integrity and
This has the disadvantage of increased noise.
これらの欠点を克服してベース抵抗を下げる構
造として第１図に示すように、ベース電極に多結
晶シリコン層を使用しできるだけエミツタ領域に
近づけベースコンタクト領域でのベース抵抗を下
げる構造が取られている。 In order to overcome these drawbacks and lower the base resistance, as shown in Figure 1, a structure is adopted in which a polycrystalline silicon layer is used for the base electrode to lower the base resistance in the base contact region as close as possible to the emitter region. There is.
この構造のトランジスタは、高不純物濃度のｎ
形シリコン基板１の上に低不純物濃度のｎ形のエ
ピタキシヤル層２を成長させ、この上に絶縁膜３
（図示していないがエミツタ領域８となる上にも
ある）をマスクとしてｐ形の不純物がドープされ
たベース電極となる多結晶シリコン膜４を選択的
に形成し、イオン注入と多結晶シリコン膜４から
の不純物拡散によりベース領域５を作るとともに
多結晶シリコン膜４の表面とベース領域５の一部
のシリコン層を酸化シリコン膜６に変換し、次
に、エミツタ領域８となる上の絶縁膜（図示せ
ず）を除去し、酸化シリコン膜６をマスクとして
ｎ形不純物をドープした多結晶シリコン膜７を選
択的に形成し、多結晶シリコン膜７からの不純物
拡散によりエミツタ領域８を作り込み、最後に、
多結晶シリコン膜４と７に電極９を形成する過程
を経て形成される。 A transistor with this structure has a high impurity concentration
An n-type epitaxial layer 2 with a low impurity concentration is grown on a silicon substrate 1, and an insulating film 3 is formed on this.
A polycrystalline silicon film 4 doped with p-type impurities, which will become a base electrode, is selectively formed using the mask as a mask (not shown, but also on the emitter region 8), and ion implantation and polycrystalline silicon film 4 are doped with p-type impurities. A base region 5 is formed by impurity diffusion from 4, and the surface of the polycrystalline silicon film 4 and a part of the silicon layer of the base region 5 are converted into a silicon oxide film 6, and then an upper insulating film that becomes an emitter region 8 is formed. (not shown), selectively forms a polycrystalline silicon film 7 doped with n-type impurities using the silicon oxide film 6 as a mask, and forms an emitter region 8 by diffusing the impurities from the polycrystalline silicon film 7. ,lastly,
It is formed through a process of forming electrodes 9 on polycrystalline silicon films 4 and 7.
ところで、このトランジスタの構造では、マス
ク合せ精度により、エミツタ領域８の端からベー
ス電極用多結晶シリコン膜４の端までの距離Ａが
1μm以上離れるため十分に接近しておらずベース
抵抗が十分に低くならない不都合が生じるし、ま
た製造方法も非常に複雑である。 By the way, in the structure of this transistor, the distance A from the end of the emitter region 8 to the end of the base electrode polycrystalline silicon film 4 is determined by the precision of mask alignment.
Since they are separated by more than 1 μm, they are not close enough and the base resistance cannot be lowered sufficiently, and the manufacturing method is also very complicated.
発明の目的
本発明は上記の不都合を排除することができる
トランジスタ、すなわち、エミツタ領域の端から
ベース電極用多結晶シリコン膜までの距離を1μm
以内に近づけベース抵抗を十分に下げることがで
きるトランジスタとその簡単な製造方法を提供す
るものである。Purpose of the Invention The present invention provides a transistor that can eliminate the above-mentioned disadvantages, that is, the distance from the edge of the emitter region to the polycrystalline silicon film for the base electrode is 1 μm.
The purpose of the present invention is to provide a transistor that can sufficiently lower the base resistance by bringing the base resistance closer to the lower limit, and a simple manufacturing method thereof.
発明の構成
コレクタ領域となる一導電形の半導体層上に逆
導電形の不純物をドープした多結晶半導体層を選
択的に形成し、さらにこの上に窒化シリコン膜を
形成してから前記多結晶半導体層内の不純物を前
記半導体層内へ拡散させベース領域を形成する。Structure of the Invention A polycrystalline semiconductor layer doped with an impurity of an opposite conductivity type is selectively formed on a semiconductor layer of one conductivity type that becomes a collector region, and a silicon nitride film is further formed on the polycrystalline semiconductor layer. Impurities in the layer are diffused into the semiconductor layer to form a base region.
次にベース領域上に選択的にエミツタ形成用の
開口を形成して前記一導電形の不純物を拡散させ
前記エミツタ領域を形成する工程で、前記エミツ
タ領域の半導体層が露出した部分には絶縁膜を形
成すると同時に、前記多結晶半導体層を前記窒化
シリコン膜をマスクとして前記エミツタ形成用の
開口より酸化物に変換する過程を経ることによ
り、前記エミツタ領域上の少なくとも一部を覆う
絶縁膜が1μm以内の幅で前記エミツタ領域を包囲
する前記ベース領域上にまで延在し、前記ベース
領域の上には逆導電形の不純物をドープした多結
晶半導体層が前記絶縁膜と隣接して配置、エミツ
タ領域とベース領域に電極が形成された構造のト
ランジスタが形成される。したがつてこの構造に
よればベース電極用多結晶半導体層がエミツタ領
域に1μm以内と非常に接近したトランジスタが得
られベース抵抗を大きく下げることができる。 Next, in the step of selectively forming an opening for forming an emitter on the base region and diffusing the impurity of one conductivity type to form the emitter region, an insulating film is formed on the exposed portion of the semiconductor layer of the emitter region. At the same time, the polycrystalline semiconductor layer is converted into an oxide through the emitter formation opening using the silicon nitride film as a mask, so that the insulating film covering at least a portion of the emitter region becomes 1 μm thick. a polycrystalline semiconductor layer doped with an impurity of the opposite conductivity type is disposed adjacent to the insulating film on the base region, and a polycrystalline semiconductor layer doped with an impurity of an opposite conductivity type is disposed adjacent to the insulating film, and A transistor having a structure in which electrodes are formed in the region and the base region is formed. Therefore, according to this structure, a transistor can be obtained in which the base electrode polycrystalline semiconductor layer is very close to the emitter region within 1 μm, and the base resistance can be greatly reduced.
実施例の説明
本発明のトランジスタの構造を得るための製造
方法の一実施例を第２図ａ〜ｆの断面図を参照に
して説明する。DESCRIPTION OF THE EMBODIMENTS An embodiment of the manufacturing method for obtaining the transistor structure of the present invention will be described with reference to cross-sectional views of FIGS. 2a to 2f.
まず、コレクタ領域となる高不純物濃度のｎ形
のシリコン基板１を準備し、その上に低不純物濃
度のｎ形のエピタキシヤル層２を１〜20μmの厚
さに成長させる。この後に、表面に酸化シリコン
膜１０を形成し、周知の写真食刻法によりベース
領域となる部分の酸化シリコン膜１０を除去す
る。 First, an n-type silicon substrate 1 with a high impurity concentration that will become a collector region is prepared, and an n-type epitaxial layer 2 with a low impurity concentration is grown thereon to a thickness of 1 to 20 μm. Thereafter, a silicon oxide film 10 is formed on the surface, and a portion of the silicon oxide film 10 that will become the base region is removed by a well-known photolithography method.
次に、表面全域に多結晶シリコン膜１１を形成
し、イオン注入法により多結晶シリコン膜１１中
にボロンイオン（B+）を注入する〔第２図ａ〕。 Next, a polycrystalline silicon film 11 is formed over the entire surface, and boron ions (B + ) are implanted into the polycrystalline silicon film 11 by an ion implantation method [FIG. 2a].
この後、ベース領域を形成するべき部分上の多
結晶シリコン膜のみを残し、他を全て除去した
後、全面に窒化シリコン膜１２を形成する〔第２
図ｂ〕。 After this, only the polycrystalline silicon film on the part where the base region is to be formed is left, and everything else is removed, and then a silicon nitride film 12 is formed on the entire surface [second
Figure b].
次に、多結晶シリコン膜１１の中にドープされ
たボロンの不純物をｎ形エピタキシヤル層２中に
拡散させてベース領域５を形成する〔第２図ｃ〕。 Next, the boron impurity doped into the polycrystalline silicon film 11 is diffused into the n-type epitaxial layer 2 to form the base region 5 [FIG. 2c].
次に、写真食刻法により、ベース領域５内のエ
ミツタ領域を形成するべき部分上の窒化シリコン
膜１２と多結晶シリコン膜１１を選択的に除去し
開口部１３を設け砒素イオン（As+）をイオン注
入する〔第２図ｄ〕。 Next, by photolithography, the silicon nitride film 12 and polycrystalline silicon film 11 on the portion of the base region 5 where the emitter region is to be formed are selectively removed, an opening 13 is formed, and arsenic ions (As + ) are removed. ion implantation [Fig. 2d].
この後、酸化性雰囲気中で拡散することにより
エミツタ領域８を形成すると同時に、エミツタ形
成用開口１３のシリコンが露出した部分には酸化
シリコン膜１４を形成し、かつ、窒化シリコン膜
１２をマスクとしてエミツタ形成用開口１３に面
する多結晶シリコン膜１１も選択的に酸化シリコ
ン膜１５に変換する。この時、多結晶シリコン膜
１１中には不純物がドープされているためエミツ
タ領域の拡散による横広がりよりも酸化シリコン
膜１５の横方向の酸化速度が速く、酸化シリコン
膜１５がエミツタ領域より0.2〜0.8μm突出した構
造になる〔第２図ｅ〕。 Thereafter, the emitter region 8 is formed by diffusion in an oxidizing atmosphere, and at the same time, a silicon oxide film 14 is formed on the exposed silicon part of the emitter forming opening 13, and the silicon nitride film 12 is used as a mask. The polycrystalline silicon film 11 facing the emitter forming opening 13 is also selectively converted into a silicon oxide film 15. At this time, since the polycrystalline silicon film 11 is doped with impurities, the lateral oxidation rate of the silicon oxide film 15 is faster than the lateral spread due to diffusion of the emitter region, and the silicon oxide film 15 is 0.2 to 0.2 times larger than the emitter region. This results in a structure that protrudes by 0.8 μm [Figure 2 e].
エミツタ領域８およびベース領域５上の多結晶
シリコン膜１１および窒化シリコン膜１２を選択
的に除去し、電極を形成するためコンタクト部分
を露出させ、これらの部分に高純度のアルミニウ
ムAlあるいは重量比で１％のシリコン（Si）を
含んだアルミニウムを用いて電極を形成すること
によりトランジスタが形成される〔第２図ｆ〕。 The polycrystalline silicon film 11 and silicon nitride film 12 on the emitter region 8 and base region 5 are selectively removed to expose the contact portions for forming electrodes, and these portions are coated with high-purity aluminum (Al) or with a weight ratio. A transistor is formed by forming electrodes using aluminum containing 1% silicon (Si) [FIG. 2f].
このように本発明のトランジスタの構造では、
ベース電極がエミツタ領域の極く近傍にあるため
ベースコンタクト領域の抵抗がほとんど無視でき
ベース抵抗を大幅を低減することができる。 In this way, in the structure of the transistor of the present invention,
Since the base electrode is located very close to the emitter region, the resistance of the base contact region can be almost ignored, making it possible to significantly reduce the base resistance.
発明の効果
以上説明したように本発明のトランジスタの構
造および簡潔な製造方法によれば、シリコンの結
晶性を損わずしてベース抵抗の低減化を図ること
ができトランジスタの雑音および高周波特性を改
善することができる。Effects of the Invention As explained above, according to the transistor structure and simple manufacturing method of the present invention, the base resistance can be reduced without impairing the crystallinity of silicon, and the noise and high frequency characteristics of the transistor can be reduced. It can be improved.
第１図は従来の高周波トランジスタの断面構造
図、第２図ａ〜ｆは本発明のベース抵抗低減のト
ランジスタの工程断面図である。
１……ｎ形シリコン基板、２……ｎ形エピタキ
シヤル層、３……絶縁膜、４，７，１１……多結
晶シリコン膜、５……ベース領域、６，１０，１
４，１５……酸化シリコン膜、８……エミツタ領
域、９……電極、１２……窒化シリコン膜、１３
……開口。
FIG. 1 is a cross-sectional structural diagram of a conventional high frequency transistor, and FIGS. 2 a to 2 f are process cross-sectional diagrams of a transistor with reduced base resistance according to the present invention. DESCRIPTION OF SYMBOLS 1... N-type silicon substrate, 2... N-type epitaxial layer, 3... Insulating film, 4, 7, 11... Polycrystalline silicon film, 5... Base region, 6, 10, 1
4, 15... Silicon oxide film, 8... Emitter region, 9... Electrode, 12... Silicon nitride film, 13
...Opening.
Claims (1)
作り込まれたベース領域内に、さらに、エミツタ
領域が作り込まれ、前記エミツタ領域上の少なく
とも一部を覆う階段上の酸化膜が1μm以内の幅で
前記エミツタ領域を包囲する前記ベース領域上に
まで延在し、前記ベース領域の上には逆導電形の
不純物をドープした多結晶半導体層が前記酸化膜
と隣接して配置されるとともに、同多結晶半導体
層の表面が窒化シリコン膜で覆われ、前記ベース
領域上に金属電極が形成されていることを特徴と
するトランジスタ。 ２ コレクタ領域となる一導電形の半導体層上に
逆導電形の不純物をドープした多結晶半導体層を
選択的に形成し、さらにこの上に窒化シリコン膜
を形成する工程、前記多結晶半導体層内の不純物
を前記半導体層へ拡散させベース領域を形成する
工程、前記ベース領域上に選択的にエミツタ形成
用の開口を形成し、前記一導電形の不純物を拡散
させエミツタ領域を形成する工程で、前記エミツ
タ領域の半導体層が露出した部分に酸化膜を形成
すると同時に、前記多結晶半導体層を前記窒化シ
リコン膜をマスクとして前記エミツタ形成用の開
口より選択的に酸化物に変換することを特徴とす
るトランジスタの製造方法。[Scope of Claims] 1. An emitter region is further formed in a base region formed in a semiconductor layer of one conductivity type, which becomes a collector region, and a stairway on a step covering at least a part of the emitter region is formed. An oxide film with a width of 1 μm or less extends over the base region surrounding the emitter region, and on the base region, a polycrystalline semiconductor layer doped with an impurity of an opposite conductivity type is adjacent to the oxide film. 1. A transistor characterized in that the surface of the polycrystalline semiconductor layer is covered with a silicon nitride film, and a metal electrode is formed on the base region. 2. A step of selectively forming a polycrystalline semiconductor layer doped with an impurity of an opposite conductivity type on a semiconductor layer of one conductivity type that will serve as a collector region, and further forming a silicon nitride film on this; a step of diffusing an impurity into the semiconductor layer to form a base region, a step of selectively forming an opening for forming an emitter on the base region, and a step of diffusing the impurity of one conductivity type to form an emitter region, An oxide film is formed on the exposed portion of the semiconductor layer in the emitter region, and at the same time, the polycrystalline semiconductor layer is selectively converted into an oxide from the opening for forming the emitter using the silicon nitride film as a mask. A method for manufacturing transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3666884A JPS60182165A (en) | 1984-02-28 | 1984-02-28 | Transistor and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3666884A JPS60182165A (en) | 1984-02-28 | 1984-02-28 | Transistor and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60182165A JPS60182165A (en) | 1985-09-17 |
| JPH0464180B2 true JPH0464180B2 (en) | 1992-10-14 |
Family
ID=12476232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3666884A Granted JPS60182165A (en) | 1984-02-28 | 1984-02-28 | Transistor and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60182165A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57211775A (en) * | 1981-06-23 | 1982-12-25 | Nec Corp | Semiconductor device and manufacture thereof |
| JPS58102558A (en) * | 1981-12-14 | 1983-06-18 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPS58102559A (en) * | 1981-12-14 | 1983-06-18 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
-
1984
- 1984-02-28 JP JP3666884A patent/JPS60182165A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57211775A (en) * | 1981-06-23 | 1982-12-25 | Nec Corp | Semiconductor device and manufacture thereof |
| JPS58102558A (en) * | 1981-12-14 | 1983-06-18 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPS58102559A (en) * | 1981-12-14 | 1983-06-18 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60182165A (en) | 1985-09-17 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |