JP2546651B2 - Method of manufacturing bipolar transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a self-aligned ultra-high speed bipolar transistor.

2. Description of the Related Art In order to increase the speed of a bipolar transistor, it is important to reduce the element size and take out electrodes in a self-aligned manner to reduce parasitic capacitance and parasitic resistance. As one method to achieve this, a semiconductor single crystal region for forming a transistor is formed in a convex shape, an intrinsic base region is formed on its upper surface, and a graft base, a base contact, and a field insulating film are self-aligned on its side surface. Structures have been proposed. For example, there are structures and manufacturing methods proposed in Japanese Patent Laid-Open Nos. 56-1556 and 59-40571. With this structure, the parasitic capacitance and parasitic resistance generated in the graft base portion are considerably reduced, and the transistor can be speeded up.

However, in order to further increase the speed of the transistor, it is necessary to reduce the parasitic capacitance by the thick field insulating film and narrow the intrinsic base width to shorten the carrier transit time in the base. For that purpose, it is necessary to realize a thin base region including the graft base, but in order to realize this with the conventional structure, the base contact window provided on the side surface of the convex single crystal region must be made as small as possible. However, simply reducing the contact window would increase the base contact resistance, making it impossible to further speed up the transistor as a whole.

OBJECT OF THE INVENTION An object of the present invention is to provide a method for manufacturing a bipolar transistor which is even faster.

Configuration of the Invention The difference between the features of the invention and the prior art is that the bipolar transistor is formed in a fine convex silicon single crystal region surrounded by a thick field insulating film, and the base contact is formed in the convex single crystal region. The feature is that the pattern edges are formed in a predetermined fine width in a self-aligned manner on the upper surface and the side surface as starting points. With this feature, a thin base region including a contact can be formed with good reproducibility. As a result, the speed of the transistor can be increased.

[Embodiment 1] FIGS. 1 (a) to (m) are process diagrams of a manufacturing process according to a first embodiment of the present invention.

In FIGS. 1A to 1M, 1 is a silicon substrate,
Reference numeral 2 is an N type low resistance buried layer, 3 is an N type epitaxial layer, 4 is a low type resistance collector compensation layer, 5 is a silicon oxide film layer, 6 is a silicon nitride film layer, 7 is a polysilicon layer, 8
Is a silicon region forming an emitter and a base, 9 is a silicon region forming a collector, 12 is a P-type channel cut region, 13 is a silicon oxide film layer, 14 is an organic film such as a resist, and 15 is an organic film such as a resist. , 17 is a polysilicon layer, 18 is a P-type graft base region, 20 is a silicon oxide film layer, 21 is a boron-added polysilicon layer, 22 is an emitter contact region, 23 is a collector contact region, 24 is an intrinsic base region, 25 Is arsenic-added polysilicon, 26 is an emitter region, 27 is a silicon oxide film, 28 is a base electrode, 29 is an emitter electrode, 30 is a collector electrode, and 31 is a silicon oxide film.

FIG. 1 The contact window 18-1 of the graft base 18 of the transistor manufactured by the manufacturing method of the present invention is formed on the upper surface and the side surface of the convex single crystal region with an extremely fine width.
Moreover, according to the manufacturing method described below, the contact window is opened with the pattern edge 6-1 of the nitride film 6 as a reference, so that the contact window can be formed with extremely high controllability. As a result, the speed of the transistor can be increased.

The process steps will be described below according to the manufacturing process of the present invention.

In FIG. 1 (α), an N-type low-resistance buried layer 2, an N-type epitaxial layer 3, and an N-type low-resistance collector compensation layer 4 are formed on a silicon substrate 1 by an ordinary well-known method. rear,
The surface is thinly thermally oxidized to form a silicon oxide film layer 5, and a silicon nitride film layer 6, a polysilicon layer 7, and a silicon oxide film layer 31 are formed thereon by a vapor phase growth method.

In FIG. 1B, the N-type low resistance collector compensation region 4 is masked and the silicon oxide film 31 to the silicon oxide film layer 5 are first etched to remove the photoresist and then the silicon oxide film 31 and the like are masked. As a pattern, the silicon substrate 1 is etched by an anisotropic dry etching method to form convex regions 8 and 9 of silicon. Between the convex silicon regions 8 and 9, it is necessary to perform shallow etching so that the N-type low resistance buried layer 2 is connected, but this is between the convex silicon regions 8 and 9 during the etching of the silicon substrate 1. A resist mask is formed by rough mask alignment, and only this portion is shallowly etched. Next, boron is ion-implanted to form a P-type channel cut region 12.

A silicon oxide film 13 is formed on this by a vapor phase growth method. The silicon oxide film 13 is formed to be slightly thicker than the height of the convex silicon regions 8 and 9. The silicon substrate 1 may be thermally oxidized before the silicon oxide film is formed by vapor phase epitaxy to form the bottom surface of the silicon oxide film 13 as a thin thermal oxide film. Next, a resist layer (organic film) 14 is formed, rough photo-etching of the silicon oxide film layer 13 around the convex silicon regions 8 and 9 and surface flattening by forming a second resist layer (organic film) 15 are performed. The place where it was performed is shown in FIG. Needless to say, various organic films and inorganic films may be used as the film for flattening the substrate surface without being limited to the resist. Next, the flattened substrate is etched by a method such as an ion milling method in which the etching rate does not easily change depending on the material. At this time, since the silicon oxide film 13 is slightly thicker than the step height of the convex silicon region, the resist layer 14 is completely etched and the entire surface of the substrate is covered with the silicon oxide film 13.
Even after being flattened, the silicon oxide film 13 remains on the convex silicon regions 8 and 9 as shown in FIG. 1 (d). The determination of etching completion up to this point can be made by monitoring the intensity of the emission spectrum from the gas in the etching champer. Then, next, when the silicon oxide film 13 is etched with a mixed solution of hydrofluoric acid and ammonium fluoride, this portion becomes hydrophobic when the polysilicon layer 7 is exposed on the surface. Therefore, it is possible to reliably determine the end of etching. Since the thickness of the silicon oxide film 13 is considerably large, the etching end time varies on the surface of the silicon substrate 1, and the etching is continued until the surfaces of all the convex silicon regions become hydrophobic. Then, generally, the upper surface of the silicon oxide film 13 is slightly lower than the upper surface of the polysilicon 7 as shown in FIG.

FIG. 1 (f) shows that the polysilicon film 7 is removed by a potassium hydroxide aqueous solution, and this substrate is slightly etched with a mixed solution of hydrofluoric acid and ammonium fluoride. This etching is an etching method with little variation, and the silicon oxide film 5 is thin and has little variation in film thickness.
And the pattern end 6-1 of the silicon nitride film 6 is used as a starting point, so that the base contact window 18-1 having a very small variation in distance from the silicon upper surface can be reliably formed by this step.

Next, boron is ion-implanted on the entire surface of the substrate shown in FIG. It is desirable that the implantation condition is 1 × 10 ¹⁶ dose or more at a low acceleration voltage of about 5 kV to 15 kV. This substrate is slightly etched with a mixed solution of hydrofluoric acid and ammonium fluoride so that the highest concentration region of the implanted ion distribution appears on the surface of the oxide film 13. Next, Fig. 1 (g)
As described above, the polysilicon film 17 is formed on this substrate. When this substrate is heat-treated at a temperature of about 900 C to 950 C, due to the difference in the diffusion coefficient of boron in the oxide film and the nitride film, the polysilicon 17-1 on the oxide film 13 is not formed as shown in FIG. 1 (h). Boron is diffused in high concentration, and the polysilicon 17-2 on the silicon nitride film 6 remains non-dope. However, there is boron diffusion from the silicon oxide film 13 near the pattern edge of the silicon nitride film 6. This heat treatment also causes boron to diffuse into the single crystal from the base contact window P
A mold graft base region 18 is formed. When this substrate is etched with a caustic potash solution, only the non-dove polysilicon is selectively etched and the silicon nitride film 6 appears on the surface as shown in FIG. 1 (i). Since polysilicon grows like acicular crystals, boron diffuses at a very high speed in the vertical direction, but the diffusion in the horizontal direction is almost the same as the diffusion in a single crystal. Therefore, the lateral length of the P-type graft base region is approximately the same as the lateral length of the residual polysilicon.

Next, the convex silicon region 8 is protected by a resist pattern by rough mask alignment, and then polysilicon is etched by a dry etching method containing silicon tetrachloride as a main component. This polysilicon may be completely etched, or the silicon oxide film 20 formed in the next polysilicon oxidation step allows the boron-added polysilicon layer 21 to be separated from other boron-added polysilicon layers 21 on the same substrate. You may leave it to some extent. The state after completion of this oxidation step is shown in FIG. After that, the silicon nitride film 6 and the silicon oxide film 5 were etched using the silicon oxide film 20 as a mask.
It is a figure (k). Next, arsenic-doped polysilicon 25 is formed on the surface, and a pattern is formed by a normal photoetching process so that it remains only on the convex silicon regions 8 and 9. Alternatively, as shown in FIG. 1 (l), polysilicon may be selectively left only in the contact window by flattening and then etching back. Finally, as shown in FIG. 1 (m), a thin silicon oxide film 27 is formed and a contact window is opened to form a base electrode 28, an emitter electrode 29 and a collector electrode 30.

Through the above steps, the structure of the bipolar transistor according to the present invention is realized. As described above, the contact window 18-1 of the graft base region 18 of the transistor has an extremely fine width self-aligned on the upper surface and the side surface of the convex single crystal region with reference to the pattern edge 6-1 of the silicon nitride film layer 6. Will be the one. As a result, the speed of the transistor can be increased.

[Embodiment 2] FIGS. 2 (a) to 2 (d) are process diagrams of a manufacturing process of an integrated bipolar transistor according to a second embodiment of the present invention and a completed drawing thereof.

The numbers 1 to 30 in FIG. 2 are the same as those explained in FIG. 32 is polysilicon and 33 is a silicon oxide film.

The manufacturing method shown in FIG. 2 is different from that shown in FIG. 1 in that, as shown in FIGS. 2 (a) to 2 (c), the silicon oxide film 5 is side-etched and then the polysilicon 32 is grown by the vapor phase growth method. Form and fill holes, and then oxidize the entire surface to form an oxide film
In the step of forming 33 and leaving the polysilicon 32-1. As a subsequent step, the same steps as those of FIG. 1 (c) and thereafter are followed to complete the transistor structure of FIG. 2 (d).

The characteristic feature of the transistor manufactured in this example is that the contact window on the upper surface of the convex silicon region can be formed wider than the side contact window in a self-aligned manner. Reduced contact resistance, graft base
There is an advantage that the distance between 18 and the intrinsic base 24 can be freely set and the internal resistance of the base can be reduced. The reduction of the base-collector capacitance, which has been a problem in the related art, is realized in the same manner as in the first embodiment, and as a result, the speed of the transistor can be further increased. Further, in this structure, since the distance between the intrinsic transistor portion and the convex silicon region can be increased, the influence of stress exerted by the silicon oxide film 13 on the convex silicon region can be suppressed.

A silicide film can be formed on the polysilicon 21 by adding the following steps to the manufacturing methods of the above two embodiments. First
In FIG. 1 (i), a metal such as molybdenum or platinum that reacts with polysilicon to form a silicide film is deposited on the entire surface, and then a silicide film is formed by heat treatment, and the overlaid metal is selectively etched. A silicide film is formed only on silicon. As an etching solution for molybdenum, for example, a mixed solution of phosphoric acid, nitric acid and acetic acid can be used. Since the silicide film can be oxidized in the same manner as polysilicon, after this, FIG. 1 (j)
In the step (2), finally, a structure in which the silicide film is self-aligned on the polysilicon is realized. With this structure, the base resistance due to polysilicon can be reduced, and the transistor speed can be further increased.

Further, the steps of forming the flat isolation island layer described in the above-mentioned embodiments have shown typical examples. For example, the steps of FIGS. It is obvious that other well-known methods such as the isolated island layer forming method can be substituted by making slight changes.

As described above, according to the present invention, the bipolar transistor is separated by the thick field oxide film, and
It is characterized in that a fine base contact is formed on the upper surface and the side surface of the convex single crystal region with a predetermined width starting from the pattern edge. With this structure, it is possible to realize a base shape having a low base contact resistance, a narrow base contact matching a narrow intrinsic base width, and a shallow graft base. As a result, there is an advantage that a faster transistor can be easily realized than ever before.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to 1 (m) show a first method of manufacturing a bipolar transistor according to the present invention. FIGS. 2 (a) to 2 (d) are process diagrams of the manufacturing process of the integrated bipolar transistor according to the second embodiment of the present invention and their completion diagrams. In the figure, 1 is a silicon substrate, 2 is an N type low resistance buried layer, 3 is an N type epitaxial layer, 4 is an N type low resistance collector compensation layer, 5 is a silicon oxide film layer, and 6 is a silicon nitride film. Layer, 7 is a polysilicon layer, 8 is a silicon region forming an emitter and a base, 9 is a silicon region forming a collector, 12 is a P-type channel cut region, 13 is a silicon oxide film layer, 14 is a flat surface such as a resist. A film for chemical conversion, a film for planarizing a resist or the like, a polysilicon layer, a P-type graft base region for the P type, a silicon oxide film layer for the P type, a polysilicon layer for adding boron, a 22 for an emitter contact region, 23 is a collector contact region, 24 is an intrinsic base region, 25 is arsenic-doped polysilicon, 26 is an emitter region, 27 is a silicon oxide film, 28 is a base electrode, 29 is an emitter electrode, 30 is a collector. Pole, 31 oxide film, 32 is polysilicon, 33 is an oxide film.

Claims (1)

(57) [Claims] 1. A method of manufacturing a self-aligned bipolar transistor, wherein a convex silicon single crystal covered with a first silicon oxide film, a silicon nitride film, and a first polysilicon film on a main surface of a silicon semiconductor substrate. A region is formed, a second silicon oxide film is formed on a flat silicon single crystal film surface other than the convex silicon single crystal region, and the first polysilicon film is removed. A base contact window of a predetermined width is opened on the upper surface and side surface of the convex silicon single crystal region starting from the edge of the silicon single crystal region, then boron is introduced into the entire surface of the substrate, and then the entire surface of the substrate. A second polysilicon film is formed on the second polysilicon film, a heat treatment is performed to diffuse boron into the second polysilicon film and the graft base portion, and the second polysilicon film is formed after the heat treatment step. The silicon film is selectively etched to oxidize the surface of the second polysilicon film to form a third silicon oxide film, and the silicon nitride film and the first silicon oxide film are used as a mask with the third silicon oxide film as a mask. A method for manufacturing a bipolar transistor, characterized in that a silicon oxide film is etched to form an emitter contact window and an arsenic-doped third polysilicon film is formed on the emitter contact.