JPS58216462A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a manufacturing method for a hetero junction semiconductor device with less photoetching steps by growing an oxygen-doped polycrystalline or amorphous silicon layer on a base silicon wafer, then ion implanting or diffusing phosphorus on the part to form an emitter and boron on the part to form a base electrode contact. CONSTITUTION:A single crystal silicon wafer is used as a starting material, and a base 13 is formed by oxidizing, photoetching and boron diffusing. An oxidized film 14 on the surface of the wafer is removed, the wafer is heated at 660 deg.C in a reaction furnace, and a mixture gas is flowed to form an oxygen-doped polycrystalline or amorphous silicon layer 42. The surface of the wafer is oxidized, a window is opened by photoetching on the prescribed part of the film 15, and phosphorus is implanted to form an emitter 21. The surface of the wafer is again oxidized, a window is opened at the prescribed part of the film 16, and boron ions are implanted to form a low specific resistance boron-doped polycrystalline or amorphous silicon layer 22. An electrode material is deposited, and an emitter electrode 31, a base electrode 32 and a collector electrode 33 of the prescribed shape is formed by photoetching.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having an emitter made of a material with a wider forbidden band width than a base, and a method for manufacturing the same.

For example, by increasing the emitter injection efficiency of transistors, hF
One way to increase Z is to configure the emitter with a material that has a wider forbidden zone than the material that makes up the base6.
N wide gates/emitter heterojunction transistor (・
Hereinafter referred to as a heterojunction transistor) is known. In order for a heterojunction formed between different materials to operate effectively, it is important that the interface state density of the junction is small, and therefore it is necessary that the difference in lattice constant and thermal expansion coefficient between the different materials be small. be. Until now, GaAs and GaAtA
Many heterojunctions, such as combinations of s, are being considered.

However, semiconductor devices such as transistors and thyristors are mainly made of single crystal silicon, which has many advantages over devices made of Ge or other materials in terms of manufacturing and device characteristics. Therefore, even when applying a heterojunction, it is desirable to use single crystal silicon as the basis. As a heterojunction based on single-crystal silicon, a combination of polycrystalline or amorphous silicon containing all oxygen and single-crystal silicon is known so far. This conventional example will be explained in detail below with reference to the drawings.

FIG. 1 is a cross-sectional view of a conventional heterojunction transistor. In the figure, a transistor 100 includes an n-type high resistivity silicon 2 layer 11 that operates as a collector, an n-type low resistivity silicon 7 layer 12 that operates as a base. A single crystal silicon substrate 1 consisting of a p-type relatively low resistivity silicon layer 13, an n-type low resistivity oxygen-containing polycrystalline or amorphous silicon layer 21 acting as a vine, Electrodes 31, 32, 33 in low resistance contact with the emitter, base, and collector layers, respectively.
and a passivation film 41 such as U P 8 G S i Ot. The forbidden band width of the polycrystalline or amorphous silicon layer 21 containing oxygen is larger than that of single crystal silicon. Therefore, the pn junction between the emitter and the base becomes a heterojunction with an emitter wide gap, and as described above, the emitter injection efficiency is high and the current amplification factor hrt is high. Depending on the constituent material of the electrode 31, the polycrystalline or amorphous silicon 21 may have a two-layer structure, and the portion or layer in contact with the electrode 31 may be made of oxygen. It is also known that a layer that does not contain oxygen, a portion or a layer that is in contact with the p-base 13 is a layer that contains oxygen.

In this case as well, the limitations regarding the emitter-base pn junction are essentially the same as in the case where the entire layer 21 contains oxygen. Next, a method for manufacturing the device 100 will be described.

FIG. 2 shows a cross-sectional view of the device in the process of being manufactured.

Furthermore, Figure 3 shows the palanquin construction process. First, an n-type wafer with an n4 layer 12 is prepared by diffusing phosphorus into an n-type high resistivity silicon single crystal wafer or by epitaxial growth (see Figure 2(a)), and then thermally oxidizing the surface of the wafer with gold. Then, an oxide film (Slot film) 14, 14' is formed, and a window is formed in a predetermined portion of the film by photoetching S10 to diffuse boron to obtain a p-paste 13 (FIG. 2(b)). The wafer is oxidized again, a window is made in the part where the base electrode will be formed in the future, and boron is diffused to form a low resistance base 13'.The wafer is then oxidized to form the Niotsuta-base junction. I opened the window and then turned on the SIR.
A polycrystalline or amorphous silicon layer 21 doped with oxygen and phosphorus is grown by a vapor phase growth method using a mixed gas of Hs and NtO as a raw material gas (second factor (C)).

Thereafter, the phosphorus in the silicon layer 21 is heat-treated to activate it, and the remaining polycrystalline or amorphous silicon layer is completely removed by photo-etching, leaving only a portion to become an emitter. PEG S'0 on the wafer surface! A passivation film 41i like
(Fig. 2(d)). Next, a window is opened in a predetermined portion of the passivation film 41, and electrodes (for example, Cr-Au) 31, 32, 3 are formed on the emitter, base, and collector, respectively.
32 to complete the device 100 (FIG. 1). Note that, if necessary, it is also possible to further improve this rear mounting [10 (1-1) by heat treatment in a hydrogen stream.

The disadvantage of such conventional heterojunction transistors is that the manufacturing process is longer than that of ordinary transistors (homojunction transistors), especially the number of photo-etching steps that account for most of the manufacturing cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide an inexpensive heterojunction semiconductor device that eliminates all of the drawbacks of the prior art, requires fewer photoetching steps, and a method for creating the same.

The present invention provides that when the oxygen, phosphorus, doped polycrystalline or amorphous silicon which is the emitter of the above-mentioned heterojunction semiconductor device removes phosphorus, it becomes semi-insulating with a resistivity of 10' to 1010Ω.(1) or more. Focusing on the fact that a good passivation film can be obtained in the process, a method was devised to form an emitter and a passivation film at the same time, thereby reducing the number of photoetching steps. That is, conventionally, emitter formation was performed using s t■4
4. 1. Using pFIs and NIO as source gas. ψ element,
Although a phosphorus-doped polycrystalline or amorphous silicon layer is grown and photo-etched to form an emitter in a predetermined shape, in the present invention, an oxygen-doped polycrystalline or amorphous silicon layer is first grown on a base silicon wafer, and then By ion-implanting or diffusing phosphorus into a portion that will later become an emitter and boron into a portion which will become a base-contact contact portion, an emitter, a base contact, and a high-voltage, high-reliability passivation film are formed.

FIG. 4 is a cross-sectional view of a petrojunction transistor that is an embodiment of the present invention. The transistor 200 includes oxygen on a single crystal silicon substrate 1 consisting of an n-type high resistivity layer 11 that operates as a collector, an n-type low resistivity layer 12, and a p-type relatively low resistivity layer 13 that operates as a base. Polycrystalline or amorphous silicon acids 42, 21.22 containing polycrystalline or amorphous silicon acids 42, 21.22 are stacked, of which portions 21.22 are doped with phosphorus and boron, respectively, and 21 acts as an emitter. 42 is the base
It covers the end and vicinity of the pn junction between the collectors.

31, 32, and 33 are an emitter electrode, a base electrode, and a collector electrode, respectively.

Such a transistor is manufactured by the process shown in FIG. Further, FIG. 6 shows a cross-sectional view of the transistor 200 in the middle of the manufacturing process. Diffusion of phosphorus into n-type 4Ω・α single crystal silicon wafer 11 C surface concentration 1 x
i □! Oatorns /, yl, diffusion depth 140μ
ml low resistivity layer 12f: A single crystal silicon wafer formed with nn4 is used as a starting material, and this is oxidized, photoetched, and boron diffused by known means to form the base 13 (FIG. 6(a)). ).

The diffusion depth of the base 13 is approximately 10 μm. The oxide film 14 on the surface of the solid wafer was removed and heated to 660C in a reactor to produce S I H430 (-C/M, N!060).
”Cc/mm, N, 25t/
- Flow the mixed gas of about 1. Form an Oam oxygen-doped polycrystalline or amorphous silicon layer 42 (Figure 46(b))
. Next, the surface of the oxide film 15 is oxidized, a window is made in a predetermined part of the oxide film 15 by ice etching, and phosphorus is applied at 100 kV for 10 minutes.
"cm" implantation to form the emitter 21 (see Fig. 6).
C)). The Ueno surface is oxidized again, a window is opened in a predetermined portion of the oxide film 16, and boron is implanted to a depth of approximately 10 cm.
Low resistivity boron-doped polycrystalline or amorphous silicon layer 2
2 (Fig. 6(d)). After activating phosphorus and boron at 900 to 100C, the electrode material (Cr-A
u) is vapor-deposited and formed into predetermined shapes of an emitter electrode 31, a base electrode 32, and a collector electrode 331 by photoetching (FIG. 4). Hydrogen treatment is performed at 450C, and the transistor 200 is completed.

hFll of the completed transistor 200 was approximately 120, which was approximately 5 times higher than that of a conventional transistor (homojunction transistor) having the same base and collector layers.

Figure 7 shows the polycrystalline or amorphous silicon film 2 in Figure 4.
1.22 and 42 are oxygen-doped layers 211.221,
This is a case where it is composed of two layers: 421 and a layer 212, 222, 422 that is not doped with oxygen. In the case of electrode 31.3
Reference numeral 2 can be an electrode metal such as At or At-B1 that is normally used in transistors. When the emitter film has a two-layer structure as described above, problems arise in the photo-etching process of the emitter film in the conventional manufacturing process. That is, the layer 212 that is not doped with oxygen has an etch rate that is more than an order of magnitude faster than the layer that is doped with oxygen, so
2 is markedly side-etched. As a result, fine processing of the emitter becomes difficult. However, in the case of FIG. 7 of the present invention, etching of the S-shaped ivy is not necessary, so
This has the advantage of not causing any inconvenience.

As is clear from FIGS. 3 and 5, in the present invention, compared to the conventional manufacturing process of a heterojunction transistor, the number of photo-etch processes is reduced by two, making it possible to significantly reduce the cost.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional heterojunction transistor;
3 is a manufacturing process flowchart of the device shown in FIG. 1, FIG. 4 is a sectional view of a heterojunction transistor which is an embodiment of the present invention, and FIG.
6 is a sectional view of the transistor shown in FIG. 4 during manufacture, and FIG. 7 is a sectional view of a heterojunction transistor according to another embodiment of the present invention. 13... Single crystal silicon layer of first conductivity type, 1111
2... Second conductivity type single crystal silicon layer, 21°21
1.212...First region of polycrystalline or amorphous silicon layer, 22,221,222...Second region of polycrystalline or amorphous silicon layer, 31...First electrode means, 3
2...Second electrode means. °1 ・j-t' Harusuke/mouth lOθ 33 Sorrow 2 (2) /3 /4- 200 33 33 3θ0

Claims (1)

[Claims] 1. (a) At least one pn junction is fully included, and the end of the pn junction is exposed on one main surface, so that one main surface is a first conductive type. a single-crystalline silicon substrate comprising a silicon layer and a silicon layer of a second conductivity type surrounding the single-crystalline silicon layer; , a first region adjacent to the silicon layer of the first conductivity type of the single crystal silicon base and containing a second conductivity type determining impurity, and a first region of the first conductivity type of the single crystal silicon substrate separated from the first region; a polycrystalline or amorphous silicon layer in which a second region containing a first conductivity type determining impurity is formed adjacent to the silicon layer; (c) the first and second regions of the polycrystalline or amorphous silicon layer; 1. A semiconductor device comprising: first and second electrode means each in low resistance contact with a region of the semiconductor device. 2. The semiconductor device according to claim 1, characterized in that the raised polycrystalline or amorphous silicon layer contains oxygen. 3. A step of forming a pn junction on a single crystal silicon substrate, a step of laminating a polycrystalline or amorphous silicon layer on one main surface of the single crystal silicon substrate, and then a polycrystalline or amorphous silicon layer. first and second at locations apart from each other.
1. A retroactive fabrication method for a semiconductor device, comprising the steps of doping with a conductivity type determining impurity and providing electrode means.