JPS60170231A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS60170231A
JPS60170231A JP59024498A JP2449884A JPS60170231A JP S60170231 A JPS60170231 A JP S60170231A JP 59024498 A JP59024498 A JP 59024498A JP 2449884 A JP2449884 A JP 2449884A JP S60170231 A JPS60170231 A JP S60170231A
Authority
JP
Japan
Prior art keywords
silicon layer
recrystallized
insulator
sio2 film
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59024498A
Other languages
Japanese (ja)
Inventor
Osamu Hideshima
秀島　修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59024498A priority Critical patent/JPS60170231A/en
Publication of JPS60170231A publication Critical patent/JPS60170231A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To enable the formation of a region with impurity introduced therein on the insulator side of a recrystallized semiconductor formed on an insulator and thereby to enable the application thereof to the preparation of a device in an SOI technique, by introducing the impurity beforehand into the vicinity of the surface of the insulator. CONSTITUTION:A thermally-oxidized SiO2 film 2 is formed on the surface of a silicon semiconductor 1, a concavity is formed therein by etching, and arsenic ions are implanted in the concavity. A polycrystalline silicon layer 4 is deposited on the whole surface, and then the silicon layer is recrystallized (single-crystallized) by laser annealing. On the occasion of this annealing, the arsenic ions implanted in the vicinity 3 of the surface of the SiO2 film 2 are diffused into a recrystallized silicon layer 5 to form a high density on the SiO2 film 2 side, and thereby an n<+> type region 6 is formed. Then, the surface of the recrystallized silicon layer 5 is made flat and the top surface of the SiO2 film 2 is exposed. The island-shaped recrystallized silicon layer 5 becomes an element forming region insulated and separated by the SiO2 film 2.

Description

【発明の詳細な説明】 発明の技術分野 本発明は半導体装置の製造方法、特に８０Ｉ（Ｓｅｍ１
ｃｏｎｄｕｃｔｏｒ　Ｏｎ　Ｉｎ５ｕｌａｔｏｒ　）タ
イプの半導体装置の製造方法に係る。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, particularly a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing a conductor-on-inverter) type semiconductor device.

従来技術 絶縁体基板上に単結晶半導体層音形成し、その中に素子
−？回路全形成する８０Ｉ技術は、従来の半導体基板ケ
用いるものに比べてを性容蛍が非常に少なく、絶縁抵抗
が高くなるという利点を有している。代表的な絶縁体基
板としてはす７アイヤが用いられ、サファイヤ基板上に
シリコン単結晶層を気相エピタキシャル成長している。Prior Art A single crystal semiconductor layer is formed on an insulating substrate, and an element is formed within it. The 80I technology, in which the entire circuit is formed, has the advantage that it has very low thermal conductivity and high insulation resistance compared to conventional semiconductor substrates. A typical insulating substrate is Lotus 7-Ire, and a silicon single crystal layer is grown on the sapphire substrate by vapor phase epitaxial growth.

最近、二酸化シリコン（Ｓｔｏｗ）その他の絶縁体基板
上に多結晶シリコン層を形成し、それを例えばレーザー
ビームでアニールすることによって単結晶化する技術が
提出され、その応用研究が盛んである。このよりな８０
Ｉ技術においてシリコン単結晶層に不純物をドーピング
する方法として、アニール前の多結晶シリコン層自体に
不純物をドーピングしておく方法や、単結晶シリコン層
上に不純物をドーピングしたキャップ層ヲ形成してその
キャップ層から単結晶シリコン層中へ不純物を拡散する
方法などが知られている。Recently, a technique has been proposed in which a polycrystalline silicon layer is formed on an insulating substrate such as silicon dioxide (Stow) and made into a single crystal by annealing it with, for example, a laser beam, and research into its application is active. This way 80
In I technology, methods for doping impurities into a silicon single crystal layer include doping the polycrystalline silicon layer itself with impurities before annealing, and forming a cap layer doped with impurities on the single crystal silicon layer. A method of diffusing impurities from a cap layer into a single crystal silicon layer is known.

しかし、単結晶層の絶縁体基板側の領域に不純物を選択
的にドーピングする技術はまだ知られていない。However, a technique for selectively doping impurities into a region of a single crystal layer on the insulator substrate side is not yet known.

発明の目的 本発明は、以上の如き従来技術に鑑み、絶縁体上に形成
する単結晶半導体層の絶縁体側領域に不純物をドーピン
グすることを目的とする。OBJECTS OF THE INVENTION In view of the above-mentioned prior art, an object of the present invention is to dope an impurity into an insulator-side region of a single crystal semiconductor layer formed on an insulator.

発明の構成 本発明は、上記目的を達成するために、絶縁体上に多結
晶シリコン層を形成し、アニールして再結晶化を行なう
除、予め絶縁体表面付近に不純物を導入しておくことに
よってアニール時に絶縁体内の不純物を再結晶化半導体
層へ拡散させる。Structure of the Invention In order to achieve the above object, the present invention involves forming a polycrystalline silicon layer on an insulator, annealing it and recrystallizing it, and introducing impurities in advance near the surface of the insulator. During annealing, impurities in the insulator are diffused into the recrystallized semiconductor layer.

この方法は不純物の偏析現象を利用するもので、不純物
の拡散は絶縁体と半導体の材質、不純物の捜類と量、ア
ニールの条件等によって規定されるが、不純物か半導体
層の絶縁体側の領域（または層）に、絶縁体側を同濃度
にして拡散されるという特徴を有している。This method utilizes the segregation phenomenon of impurities, and the diffusion of impurities is determined by the materials of the insulator and semiconductor, the type and amount of impurities, the annealing conditions, etc. (or layer) has the characteristic that it is diffused with the same concentration on the insulator side.

発明の実施例 本発明の実施例としてバイポーラトランジスタを作成す
る工程を回向を参照して説明する。第１図を参照すると
、シリコン半導体基板１の表面に例えば熱酸化５１０２
膜２を形成し、大きさ数１０μｍ、深さ１〜Ｌ５μｍ程
度の逆台形断面にエツチングして５ｉ０２膜２内に凹所
を形成する。この凹所の形成は、凹所となるべき部分以
外の選択的酸化によって行なってもよい。次いで、８１
０２膜２の凹所内表面付近３に例えばヒ素を加速電圧４
０ＫｅＶでドーズ量５×１０１５ｃｔｎ−２程度イオン
打ち込む。Embodiments of the Invention As an embodiment of the present invention, a process for manufacturing a bipolar transistor will be described with reference to the present invention. Referring to FIG. 1, for example, thermal oxidation 5102 is formed on the surface of the silicon semiconductor substrate 1.
A film 2 is formed and etched into an inverted trapezoidal cross section with a size of several tens of micrometers and a depth of about 1 to L5 micrometers to form a recess in the 5i02 film 2. The formation of this recess may be performed by selectively oxidizing the portion other than the portion to become the recess. Then 81
02 For example, arsenic is applied near the inner surface 3 of the recess of the membrane 2 at an accelerating voltage of 4
Ion implantation is performed at a dose of about 5×10 15 ctn −2 at 0 KeV.

第２図を参照すると、全面に多結晶シリコン（ヒ素ドー
プ１０１６ｃｍ”）層４を厚さ１〜１．５μｍ程度堆積
する。Referring to FIG. 2, a polycrystalline silicon (arsenic doped 1016 cm") layer 4 is deposited on the entire surface to a thickness of about 1 to 1.5 .mu.m.

第３図を参照すると、例えば、出力６〜ＩＯＷのアルゴ
ンＣＷレーザーのビームを約５ｃｍ７秒の速度で多結晶
シリコン層４に走査してアニーリングし、シリコン層を
再結晶化（単結晶化）する。Referring to FIG. 3, for example, the polycrystalline silicon layer 4 is annealed by scanning an argon CW laser beam with an output of 6 to IOW at a speed of about 5 cm and 7 seconds to recrystallize the silicon layer (single crystallization). .

このレーザーアニールのために多結晶シリコン層４上に
ＰＳＧ膜（０，５μｍ）、ＳｉＮ膜（６５０′Ａ）等を
キャンプ層として設けてもよい。また、アニーリングは
レーザービームのほか、電子ビーム。For this laser annealing, a PSG film (0.5 μm), a SiN film (650'A), or the like may be provided as a camp layer on the polycrystalline silicon layer 4. In addition to laser beams, annealing can also be done using electron beams.

ランプフラッシュ等を用いて行なってもよい。こうして
アニーリングで再結晶化されたシリコンはいくらか体積
収縮するとともに８１０２膜２の凹所内（即ち低い位置
）に果まるが、再結晶シリコン層５の最も低い表面が５
ｉ０２膜２の上面より低くならないように体積計算して
おく。This may be done using a lamp flash or the like. In this way, the silicon recrystallized by annealing shrinks in volume somewhat and ends up in the recess (i.e., at a lower position) in the 8102 film 2, but the lowest surface of the recrystallized silicon layer 5
The volume is calculated so that it is not lower than the upper surface of the i02 film 2.

このレーザーアニールの際、多結晶シリコンが再結晶化
するとともに、５１０２膜２の表面近傍３に打ち込まれ
ていたヒ素イオンがレーザービームの熱で杓結晶シＩＪ
　）ン鳩５中へ拡散し、再結晶シリコン層５のＳ＋０２
膜２側に８ｉ０２膜２側を高濃度としてｎ十形領域６を
形成する。ｎ十形領域６のヒ。During this laser annealing, the polycrystalline silicon is recrystallized, and the arsenic ions implanted in the vicinity of the surface 3 of the 5102 film 2 are transferred to the ladle crystal IJ due to the heat of the laser beam.
) diffuses into the silicon layer 5 and S+02 of the recrystallized silicon layer 5.
An n-type region 6 is formed on the film 2 side with the 8i02 film 2 side having a high concentration. h of the n-decade region 6.

素濃度（絶縁体と８１の界面）は１０２０〜’１０”ｃ
ｍ−３程度、拡散幅は０．２〜０．５μｍ程農である。The elementary concentration (interface between insulator and 81) is 1020~'10"c
m-3, and the diffusion width is about 0.2 to 0.5 μm.

第４図を参照すると、例えば、ＧＴ、ＡＮＺＯＸ　３２
５０（商品名）等の研摩液を用いて再結晶シリコン層５
０表面を平坦化し、かつＳ！０２膜２の上面を露出させ
ることによって、再結晶シリコン層５管８１０２膜２の
凹所内の島として形成する。これによって島状再結晶シ
リコン層５は５１０２膜２で絶縁分離された素子形成領
域となる。Referring to FIG. 4, for example, GT, ANZOX 32
50 (trade name) using a polishing liquid such as
0 surface is flattened and S! By exposing the upper surface of the 02 film 2, the recrystallized silicon layer 5 tube 8102 is formed as an island within the recess of the 02 film 2. As a result, the island-shaped recrystallized silicon layer 5 becomes an element formation region insulated and isolated by the 5102 film 2.

ｋ５図を参照すると、以下、常法に従い、上記素子形成
領滅却ち島状再結晶シリコン層５内に、ペース拡散７、
エミッタ拡散８を行ない、そして電極９を形成すること
によって、バイポーラトランジスタを完成する。Referring to figure k5, below, according to a conventional method, a pace diffusion 7,
By performing emitter diffusion 8 and forming electrode 9, the bipolar transistor is completed.

このバイポーラトランジスタにおいてｎ十形領域６は従
来の埋込層の役割を果たすほか、コレクタ電極のコンタ
クト拡散を不要にする意味も持ちうる。In this bipolar transistor, the n+-type region 6 not only plays the role of a conventional buried layer, but also has the meaning of eliminating the need for contact diffusion of the collector electrode.

なお、本発明の応用がバイポーラトランジスタに限らな
いことは明らかであろう。また、再結晶イヒシリコン鳩
は平坦な絶縁体上に形成してもよいし、平坦な絶縁体上
に形成しなおかつ島状に形成することも可能である。例
えば、絶縁体上の多結晶シリコン層を島状にバターニン
グし、島状の多結晶シリコン層を絶縁体で完全に包囲し
てからアニーリングすれば、絶縁体囲繞体内に島状の再
結晶シリコン層が形成できる。また、用途によっては、
全面に形成した再結晶シリコンＪ―をバターニングして
島状にしたり、あるいは、それをバターニングせずに不
純物を打ち込んで絶縁分離してもよいであろう。更に、
本発明がシリコン以外の半導体、８１０２以外の絶縁体
にも応用可能でおることも明らかであろう。Note that it is clear that the application of the present invention is not limited to bipolar transistors. Further, the recrystallized silicon dome may be formed on a flat insulator, or it is also possible to form it on a flat insulator and form it in the form of an island. For example, if a polycrystalline silicon layer on an insulator is buttered into islands, the island-like polycrystalline silicon layer is completely surrounded by an insulator, and then annealing is performed. A layer can be formed. Also, depending on the application,
The recrystallized silicon J- formed over the entire surface may be patterned into an island shape, or impurities may be implanted into the island without patterning it for insulation and isolation. Furthermore,
It will also be clear that the present invention is applicable to semiconductors other than silicon and insulators other than 8102.

発明の効果 以北の説明から明らかなように、本発明により、絶縁体
上に多結晶半導体を再結晶化（単結晶化）して形成する
再結晶（単結晶）半導体の絶縁体側に不純物導入領域を
形成することが可能になり、５ＯＴ９術におけるデバイ
ス作成に応用できる。Effects of the Invention As is clear from the above explanation, the present invention makes it possible to introduce impurities into the insulator side of a recrystallized (single crystal) semiconductor formed by recrystallizing (single crystallization) a polycrystalline semiconductor on an insulator. It becomes possible to form a region, and it can be applied to device creation in 5OT9 surgery.

【図面の簡単な説明】[Brief explanation of drawings]

第１図〜第５図は本発明の詳細な説明するだめの半導体
装置の製作工程順の断面図である。 ２・・・５ｉＯｚ膜、　３・・・ヒ素打込領域、４・・
・多結晶シリコン層、５・・・再結晶シリコン層、６・
・ヒ素ドープｎ十形領域。 第１１］ ＪＪＪＪＪＪＪ＋ＪＪＪＪｌ 第２図 第３図1 to 5 are cross-sectional views showing the steps of manufacturing a semiconductor device for which the present invention will not be explained in detail. 2...5iOz film, 3...Arsenic implantation area, 4...
・Polycrystalline silicon layer, 5... Recrystallized silicon layer, 6.
-Arsenic-doped n-decade region. 11] JJJJJJJ+JJJJl Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 絶縁層の表面付近に不純物を導入し、該絶縁層上に多結
晶半導体層を形成し、そして、該多結晶半導体層に輻射
線を照射してアニーリングすることに五って、該多結晶
半導体層を再結晶化すると共に、生成した再結晶半導体
層の前記絶縁層に接触する領域に前記不純物をドープす
る工程を含むことを特徴とする半導体装置の製造方法。Introducing impurities near the surface of the insulating layer, forming a polycrystalline semiconductor layer on the insulating layer, and annealing the polycrystalline semiconductor layer by irradiating the polycrystalline semiconductor layer with radiation. A method for manufacturing a semiconductor device, comprising the steps of recrystallizing the layer and doping the impurity into a region of the produced recrystallized semiconductor layer that contacts the insulating layer.
JP59024498A 1984-02-14 1984-02-14 Manufacture of semiconductor device Pending JPS60170231A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59024498A JPS60170231A (en) 1984-02-14 1984-02-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59024498A JPS60170231A (en) 1984-02-14 1984-02-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60170231A true JPS60170231A (en) 1985-09-03

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP59024498A Pending JPS60170231A (en) 1984-02-14 1984-02-14 Manufacture of semiconductor device

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JP (1) JPS60170231A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62179715A (en) * 1986-02-04 1987-08-06 Nec Corp Manufacture of soi crystal
US4835113A (en) * 1986-09-26 1989-05-30 American Telephone And Telegraph Company, At&T Bell Laboratories Fabrication of dielectrically isolated devices with buried conductive layers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62179715A (en) * 1986-02-04 1987-08-06 Nec Corp Manufacture of soi crystal
US4835113A (en) * 1986-09-26 1989-05-30 American Telephone And Telegraph Company, At&T Bell Laboratories Fabrication of dielectrically isolated devices with buried conductive layers

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