JPH01135069A - Manufacture of heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE:To largely reduce a base-collector junction capacity, a base resistance, a base-collector parasitic capacity by restricting the junction region between a collector layer and a base layer in an intrinsic region by an insulation sidewall, and setting the thickness of the sidewall to a thin value. CONSTITUTION:After a collector layer 12 made of doner-doped N-type GaAs is grown 0.5-1.0mum thick by a molecular beam epitaxial growth method or an organic metal thermal decomposition vapor growth method, etc., on a semi- insulation substrate 1 made of GaAs, a mask 13 made of an insulator, such as SiO2, Si3N4, etc., and having an etching section substantially perpendicular to the substrate is formed. If the mask 13 is composed of the Si3N4 by a film growing method having preferable step coverage, such as a chemical vapor growth method, etc., an SiO2 film is grown on a whole substrate. Then, the SiO2, deposited on the flat part of the substrate is removed by selectively etching by an anisotropic etching method in an etching advancing direction, such as reactive ion etching, etc., in a CF4 gas atmosphere, thereby forming an insulation sidewall 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a heterojunction bipolar transistor using a heterojunction of a compound semiconductor or the like.

[Conventional technology]

In recent years, vigorous research and development has been carried out on semiconductor devices to achieve higher integration and higher speed. In particular, bipolar transistors (hereinafter referred to as H
BT) has high emitter injection efficiency, is expected to have high gain and high speed, and is attracting attention as a next-generation semiconductor device.

This HBT has become possible with the advancement of compound semiconductor thin film multilayer crystal growth technology using molecular beam epitaxial growth, organometallic pyrolysis vapor phase epitaxy, and the like.

In this HBT, the maximum oscillation frequency fwax, which is an index expressing high-speed and high-frequency characteristics, is calculated using the following formula (%) where fT is the current gain cutoff frequency, RB is the base resistance, and CBC is the base of the transistor's intrinsic region. - Collector junction capacitance, Cbo, is the base-collector parasitic capacitance of the external base region of the transistor.

As is clear from equation (1), one way to achieve high-speed operation of the HBT is to minimize the base-collector junction capacitance CBC, the base-collector parasitic capacitance CBC, or the base resistance RB. Conventionally, in order to achieve this high-speed operation, the intrinsic region of the transistor was miniaturized, the base-collector junction capacitance CBC was reduced, and the external base region of the substrate on which the transistor was constructed was selectively deposited from the surface side of the substrate. The base-collector parasitic capacitance Cbc was reduced by implanting oxygen ions at high energy and making the base-collector junction semi-insulating. Furthermore, in addition to these, a dopant that forms the same conductivity type as that of the base layer is ion-implanted into the external base region, and the dopant is activated by subsequent heat treatment to reduce the sheet resistance of the external base layer and to reduce the sheet resistance of the external base layer. The base resistance RB was reduced by reducing the contact resistance with the base electrode.

Figure 2 shows G a A s / A e as a heterojunction.
A cross-sectional view of a conventional HBT chip using GaAs is shown.

A collector layer 22 made of n-type GaAs, a base layer 26 made of p-type GaAs, and an n-type AeG are formed on a semi-insulating substrate 21.
An emitter layer 27 made of aAs is formed. The base layer 26 and collector layer 2 immediately below this emitter layer 27
2 constitutes the intrinsic region of the transistor and is responsible for actual transistor operation. In the region outside this intrinsic region, oxygen ions and p
By sequentially ion-implanting a dopant (for example, Mg) that forms the conductivity of the mold and heat-treating it, an ion-implanted insulating layer 211 and a base contact layer 2 made of p-type GaAs are formed.
12 are formed. This configuration reduces the base-collector parasitic capacitance Cb0 in the region outside the intrinsic region, simultaneously reduces the sheet resistance of the base contact layer 212 and the contact resistance with the two base electrodes, and reduces the base resistance RB. It was being reduced.

[Problem that the invention seeks to solve]

In such a conventional HBT, the intrinsic region of the transistor is defined by a mask provided on the emitter layer 27, so miniaturization of the intrinsic region is limited by the lithography technique used to form this mask. Ru. That is, in the current photolithography technology, 1 μm
Below, also in electron beam lithography technology, 0.5μ
It is difficult to form a fine mask of less than m with good reproducibility. Therefore, there is a limit to the reduction in base-collector junction capacitance in the intrinsic region.

Furthermore, the ion implantation process and accompanying heat treatment process for forming the ion implantation insulating layer 211 and the base contact layer 212 induce crystal defects in the base contact layer 212 and transfer impurities in each layer of the transistor to the adjacent layer. It was spreading. That is, the base contact layer 21
The crystal defects in No. 2 caused carrier traps and prevented a sufficient reduction in base resistance. Also, diffusion of impurities,
In particular, impurities in the base layer 26 diffuse into the emitter layer 27, resulting in an increase in recombination current and a significant reduction in emitter injection efficiency.

Furthermore, even with such ion implantation, the base contact layer 212 and the collector layer 22 are still configured to face each other, so the base-collector parasitic capacitance Cbc is at most 3
A reduction of only about 0% to 40% was possible.

An object of the present invention is to provide a heterojunction bipolar transistor that can significantly reduce base-collector junction capacitance, base resistance, and base-collector parasitic capacitance in the intrinsic region without requiring the ion implantation process that causes the above-mentioned problems. The purpose is to provide a manufacturing method.

[Means for solving problems]

The method for manufacturing a heterojunction bipolar transistor of the present invention includes the steps of forming a collector layer made of a first semiconductor material on a semi-insulating semiconductor substrate, a mask having a predetermined pattern on the collector layer, and a mask having a predetermined pattern on the side surface of the mask. forming an insulating sidewall; etching a part or all of the exposed portion of the collector layer using the mask and the insulating sidewall; and etching the etched surface from an insulating material or a semi-insulating semiconductor material. a step of sequentially epitaxially growing a base contact layer made of a second semiconductor material on the spacer layer; a step of etching the insulating sidewall to expose the collector layer; The method includes a step of sequentially epitaxially growing a base layer made of a third semiconductor material and an emitter layer made of a fourth semiconductor material on the exposed portion of the collector layer.

[Effect]

In the present invention, since the junction region between the collector layer and the base layer in the intrinsic region is defined by the insulating sidewall, by setting the thickness of this sidewall thin, the base-collector junction capacitance CaC can be significantly reduced.

Furthermore, in the present invention, the collector layer directly below the external base region is etched, and a spacer layer made of an insulating material or a semi-insulating semiconductor material is formed in this etched region by epitaxial growth. Depending on the thickness, base-collector parasitic capacitance cb
The base-collector parasitic capacitance Cbo can be made almost zero by significantly reducing c or by etching the entire collector layer and forming a spacer layer directly on the semi-insulating semiconductor substrate.

Furthermore, since the external base region has a base contact layer made of the second semiconductor material formed by epitaxial growth, the base resistance can be significantly reduced by adjusting the doping concentration or thickness of the base contact layer.

Moreover, since each of these layers is formed by epitaxial growth, an ion implantation process and an accompanying heat treatment process are not required, and the induction of crystal defects and the diffusion of impurities can be prevented.

〔Example〕

Hereinafter, the present invention will be described as npn type A e Ga As /
This will be explained using the drawings, taking GaAsHBT as an example.

FIG. 1(a) to FIG. 1(d) are device cross-sectional views for explaining one embodiment of the present invention in the order of manufacturing steps. first,
As shown in FIG. 1(a), a collector layer 12 made of n-type GaAs doped with a donor (for example, Si) is formed on a semi-insulating substrate 11 made of GaAs to a thickness of 0.5μ.
m to 1.0 μm using molecular beam epitaxial growth method or organometallic pyrolysis vapor phase growth method,
A mask 13 is formed of an insulator such as 5i02, Si3, N4, etc. and has an etched cross section substantially perpendicular to the substrate. This is because when Si3N4 is used as the mask 13, the sides of the mask 13 are made of a material different from that of the mask 13. An insulating side wall 14 is formed. Insulating side wall 1
4 is formed by the following procedure. First, a mask 13 is formed using a film forming method with good step coverage such as chemical vapor deposition.
If it is made of Si3N4, for example, 5i02 is deposited over the entire surface of the substrate. Next, using an etching method that is anisotropic in the direction of etching progress, such as reactive ion etching in a CF4 gas atmosphere, the 5i02 deposited on the flat part of the substrate is selectively etched away, and the insulating sidewalls are removed. 14 is formed.

Next, as shown in FIG. 1(b), the collector layer 12 is removed by etching using the mask 13 to expose the semi-insulating substrate 11. Suitable etching means include reactive ion etching using an atmospheric gas such as BCe3 gas or Ce2 gas, or reactive ion beam etching, which provides a substantially vertical etched cross section.

Next, as shown in FIG. 1(b), the collector layer 12 is etched using the mask 13 and the insulating sidewalls 14 as masks. In the case of this embodiment, the entire exposed portion of the collector layer 12 is removed by etching to expose the semi-insulating substrate 11. As an etching means, BCff can obtain a substantially vertical etching cross section.

Reactive ion etching using an atmospheric gas such as gas, CG2 gas, or reactive ion beam etching is suitable. After that, in the exposed area of the semi-insulating substrate 11,
The upper surface of the collector layer 12 is made of GaAs, which is made of the same material as the semi-insulating substrate 11 and has been made semi-insulating by doping with deep energy donor impurities (e.g. oxygen) or deep energy acceptor impurities (e.g. Cr, Fe). The spacer layer 15 is epitaxially grown until the spacer layer 15 is reached.
form. Further, on this spacer layer 15, an acceptor (for example, Be) is deposited at a high concentration (for example, 4×10”9 to 1
A base contact layer 16 of p-type GaAs doped to 0.times.10@19 cm@-3 is epitaxially grown. These spacer layer 15 and base contact layer 16
For epitaxial growth, highly selective growth methods such as metal organic pyrolysis vapor phase epitaxy are suitable.

Subsequently, as shown in FIG. 1C, the insulating sidewall 14 is selectively etched to expose the collector layer 12. This enchig has, for example, an insulating sidewall 14 of 5i02,
If the mask 13 is Si3N4, buffered hydrofluoric acid is suitable. Thereafter, a base layer 17 made of p-type GaAs doped with an acceptor (e.g., Be) is deposited on the collector layer 12 and the base contact layer 16 to a thickness of several tens of nanometers to several hundred nanometers, and a donor (e.g., S
An emitter layer 18 of n-type AffGaAs doped with i) is sequentially and selectively epitaxially grown to a thickness of several hundred nanometers.

Next, as shown in FIG. 1(d), the mask 13 and emitter layer 18 are partially etched using a well-known method to expose predetermined regions on the collector layer 12 and base layer 17 where electrodes are to be formed. However, emitter electrode 19 and collector electrode 110 are made of an ohmic contact metal (eg AuGe/Ni) for n-type GaAs, and an ohmic contact metal (eg AuZn) for p-type GaAs.

A base electrode 111 made of (AuCr, AuMn, etc.) is formed to complete the HBT.

In this embodiment, semi-insulating GaAs containing donor or acceptor impurities forming a deep energy level is used in the spacer layer 15, but GaAs made of an intrinsic semiconductor not doped with impurities may also be used. good.

This functions as a semi-insulating material exhibiting a specific resistance of about 10 8 [Ω·1] at room temperature. Further, an insulating material such as calcium fluoride that has a lattice match with GaAs and can be grown epitaxially may be used as the spacer layer.

〔Effect of the invention〕

As explained above, in the present invention, since the junction region between the collector layer and the base layer in the intrinsic region of the transistor is defined by the insulating sidewall, by setting the thickness of this sidewall thin, it is possible to Bonding regions on the order of microns can be easily formed. In addition, in the external base region, since a spacer layer made of an insulating material or a semi-insulating semiconductor material can be formed on the semi-insulating substrate, the base layer or the base contact layer and the collector layer do not directly contact or face each other. be able to. Further, since this base contact layer is formed by epitaxial growth, it can be set to a high concentration and a sufficient thickness.

Therefore, in the present invention, the base resistance, the base-collector parasitic capacitance, and the base-collector junction capacitance in the intrinsic region of the transistor can be significantly reduced.
(The operating frequency of BT can be greatly improved.

Furthermore, since ion implantation and accompanying heat treatment steps are not required, it is possible to prevent the emitter implantation efficiency from decreasing due to impurity diffusion.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are cross-sectional views of an element for explaining step-by-step an embodiment of the manufacturing method of the present invention, and FIG. 2 is a cross-sectional view showing an example of a conventional heterojunction bipolar transistor. It is. 11.21... Semi-insulating substrate, 12.22... Collector layer, 13... Mask, 14... Insulating side wall, 1
5... Spacer layer, 16,212... Base contact layer, 17.26... Base layer, 18.27...
Emitter layer, 19.28... Emitter electrode, 110.
210...Collector electrode, 111.29...Base electrode, 211...Ion-implanted insulating layer.

Claims (1)

[Claims] (1) forming a collector layer made of a first semiconductor material on a semi-insulating semiconductor substrate; forming a mask with a predetermined pattern on the collector layer; and forming an insulating sidewall on the side surface of the mask; etching a part or all of the exposed portion of the collector layer using a mask and the insulating sidewall; a spacer layer made of an insulating material or a semi-insulating semiconductor material on the etched surface; and a spacer layer made of an insulating material or a semi-insulating semiconductor material; a step of sequentially epitaxially growing a base contact layer made of a second semiconductor material; a step of etching the insulating sidewall to expose the collector layer;
Manufacturing a heterojunction bipolar transistor, comprising the step of sequentially epitaxially growing a base layer made of a third semiconductor material and an emitter layer made of a fourth semiconductor material on exposed portions of the base contact layer and the collector layer. Method.