JPH03256332A - Vertical bipolar transistor element and bi-cmos inverter using the same element - Google Patents

Abstract

PURPOSE:To reduce a lowest operating voltage by forming a base region of an n-type diffused layer in which n-type impurity is diffused from a base electrode, incorporating p-type impurity in an emitter electrode, and forming the emitter electrode of a p-type diffused layer in which p-type impurity is diffused from the emitter electrode. CONSTITUTION:An n<+> type diffused layer (base region) 5 which is operated as a function of a base is formed on an upper predetermined region of an epitaxial layer 3. A p<+> type diffused layer (emitter region) 6 which is operated as a function of an emitter is formed on an upper predetermined region of the base region 5. A base electrode 7 made of an n<+> type polycrystalline silicon layer and a polycrystalline silicon emitter (emitter electrode) 8 made of p<+> type polycrystalline silicon are formed on the layer 3, and respectively electrically connected to the base region 5 and the emitter region 6. The region 5 is formed by impurity diffusion from the electrode 7 of the silicon layer, and the region 6 is formed by impurity diffusion from the emitter made of the silicon layer in a self-alignment manner.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a vertical p'np bipolar transistor element suitable for high integration, and a bi-CMOS inverter equipped with the element.

(Prior art) bi-CMOS, which combines bipolar transistors and CMOS on the same chip, is a CMOS with low power consumption.
It is possible to combine the advantages of MOS and the advantage of bipolar transistors such as high driving power.

FIG. 3 shows a circuit diagram of a conventional BL-CMOS inverter.

The output stage of this bi-CMOS inverter includes an npn bipolar transistor 35 whose collector is connected to the power supply terminal 39, and an npn bipolar transistor 35 whose emitter is grounded and whose collector is connected to the emitter of the npn bipolar transistor 35.
It consists of a bipolar transistor element 36. The output section 38 is connected to the emitter of the npn bipolar transistor 35 and the collector of the npn bipolar transistor 36.

The input stage includes an n-type MOS transistor 31 whose source is connected to the power supply terminal 39 and whose drain is connected to the base of the npn bipolar transistor 35; type MOS transistor 32 and an n-type MOS transistor 32 whose drain is connected to the output section 38 and whose source is connected to the base of the npn bipolar transistor 36.
transistor 33, whose source is grounded and whose gate is npn
It has an n-type MOS transistor 34 connected to the base of a bipolar transistor 35 and whose drain is connected to the gate of an npn bipolar transistor 36.

. The input section 37 includes the gate of the n-type MOS transistor 31,
It is connected to the gate of the n-type MOS transistor 32 and the gate of the n-type MOS transistor 33.

Figure 4 shows the np of the above conventional bi-CMOS inverter.
FIG. 2 is a cross-sectional view showing an n-bipolar transistor.

Near the surface of the p-type silicon substrate 41, in a selected region where an npn bipolar transistor is to be formed,
An n++ buried diffusion layer 42 functioning as a collector is formed.

An epitaxial layer is formed on the upper surface of the substrate 41, and an n-type element region 43 and a p4 are formed in the epitaxial layer.
A type element isolation region 44 is formed.

The p++ element isolation region 44 has a planar pattern corresponding to an area on the substrate 41 other than the area where the elements are formed.

In a predetermined region above the n-type element region of the epitaxial layer,
p″ type diffusion layer (base region) 45 functioning as a base
is formed. Further, in a predetermined upper region of the p4 type diffusion layer 45, an n+ type scattering layer emitter region 46 which functions as an emitter is formed. Further, the n+ type scattering layer 52 is formed so as to be connected to the n1 type buried diffusion layer 42.

An oxide film 51 is formed on the substrate 41 to electrically isolate the base region 45 and the n+ type scattering layer 52 and to electrically isolate the element from other adjacent elements. ing.

On these oxide films 51 and epitaxial layers, the first
An interlayer insulating film 48 is formed. A polycrystalline silicon emitter (emitter electrode) 47 made of an n+ type polycrystalline silicon layer is formed on a predetermined region of the first interlayer insulating film 48. Electrical connection between the polycrystalline silicon emitter 47 and the epitaxial layer is made through a contact hole 50a formed in the first interlayer insulating film 48.

Emitter region 46 is formed by impurity diffusion from polycrystalline silicon emitter 47 in a self-aligned manner.

A second interlayer insulating film 49 is further formed on the first interlayer insulating film 48 so as to cover the upper surface of the first interlayer insulating film 48 and the polycrystalline silicon emitter 47 .

In predetermined areas of the first and second interlayer insulating films 48 and 49,
Contact holes 50b are provided, and a collector electrode 501, an emitter electrode 502, and a base electrode 503 made of metal are connected through these contact holes 50b.
are electrically connected to collector region 42, polycrystalline silicon emitter 47, and base region 45, respectively.

(Problems to be Solved by the Invention) However, the above-mentioned prior art has the following problems.

Since the two bipolar transistors constituting the output stage are both npn bipolar transistors, the input stage requires four MOS transistors. Therefore, the conventional bi-CMOS inverter occupies a large area on a chip, and it is difficult to reduce the area. Therefore, the conventional technology has the drawback of being unsuitable for high integration of bi-CMO8.

Furthermore, in the conventional example, the npn bipolar transistor 36
n-type M by the base-emitter voltage (V BE) of
Since the source potential of the OS transistor 33 is raised, there is a drawback that unless the operating voltage is increased accordingly, the gate voltage of the n-type MOS transistor 33 will be lowered and the drain current will be reduced.

A high minimum operating voltage is a major obstacle to improving the reliability of a gate insulating film of a MOS transistor.

The present invention has been made to solve the above problems, and its purpose is to provide a vertical pnp bipolar transistor element that occupies a reduced area on a chip, and a vertical pnp bipolar transistor element that is equipped with the element and has a minimum operating voltage. An object of the present invention is to provide a BL-CMOS inverter with low cost and improved reliability.

(Means for Solving the Problems) The vertical pnp bipolar transistor element of the present invention has p
a p-type semiconductor substrate, a p-type collector region formed in the p-type semiconductor substrate, an n-type base region formed on the collector region, and a p-type emitter region formed in the base region. a base electrode formed on the base region and electrically connected to the base region; and an emitter electrode formed on the emitter region and electrically connected to the base region. , the base electrode contains an n-type impurity, the base region is an n-type diffusion layer in which the n-type impurity is diffused from the base electrode, and the emitter electrode contains an n-type impurity, The emitter region is an n-type diffusion layer in which the n-type impurity is diffused from the emitter electrode, thereby achieving the above object.

The bi-CMOS inverter of the present invention includes the vertical pnp bipolar transistor element whose collector is grounded;
An npn bipolar transistor element whose collector is connected to the power supply, whose source is connected to the power supply, and whose drain is connected to the power supply.
an n-type MOS transistor connected to the base of the pn bipolar transistor element; an n-type MOS transistor whose source is grounded and whose drain is connected to the base of the vertical pnp bipolar transistor element and the base of the npn bipolar transistor element; , an input section connected to the gate of the p-type MOS transistor and the gate of the n-type MOS transistor, and an output section connected to the emitter of the vertical p n p bipolar transistor element and the emitter of the npn bipolar transistor element. and,
are provided on the same substrate, thereby achieving the above object.

(Example) The present invention will be described below with reference to Examples.

FIG. 1 is a sectional view showing a vertical pnp bipolar transistor element of this example.

Near the surface of a p-type silicon substrate l, a p+ diffusion layer (collector region) 2 functioning as a collector is formed in a region selected to form a vertical pnp bipolar element. On the upper surface of the substrate 1, an epitaxial layer 3 and an element isolation film 4 are formed. The element isolation film 4 is formed by thermally oxidizing a predetermined region of an epitaxial layer grown on the entire surface of the substrate 1.
It has a plane pattern corresponding to an area other than the area where the various elements above are formed.

In a predetermined upper region of the epitaxial layer 3, an n4 diffusion layer (base region) 5 that functions as a base is formed. Further, in a predetermined upper region of the base region 5, a p++ diffused layer (emitter region) 6 is formed which functions as an emitter. A base electrode 7 made of an n0 polycrystalline silicon layer and a polycrystalline silicon emitter (emitter electrode) 8 made of p0 polycrystalline silicon are formed on the epitaxial layer 3, and are electrically connected to the base region 5 and emitter region 6, respectively. is in contact with.

Further, an interlayer insulating film 9 is formed on the substrate 1 so as to cover the upper surface of the substrate 1. A contact hole 10a is provided in a predetermined region of the interlayer insulating film 9.

10b, the base electrode 7 and the metal wiring 11a are electrically connected through the contact hole 1a, and the polycrystalline silicon emitter 8 and the metal wiring 11b are connected through the contact hole 10b. It is electrically connected to the emitter region 6. Note that an electrode functioning as a collector electrode is formed on the back surface of the substrate (not shown).

The base region 5 is formed by impurity diffusion from the base electrode 7 made of an n+ polycrystalline silicon layer, and the emitter region 6 is formed by impurity diffusion from a polycrystalline silicon emitter made of a p" polycrystalline silicon layer. It is formed in a self-consistent manner.

Therefore, mutual alignment, which is necessary when forming the electrode and the diffusion layer in mutually independent steps, is not necessary in this embodiment. Therefore, the area of the base region 5 of this embodiment does not require a dimensional margin for alignment, and the area of the base region 5 can be reduced by that amount. Conventionally, this dimensional margin has ranged from 0.4μ to 0.4μ. It was about 6 μ-.

This also holds true for emitter region 6. In the configuration of this embodiment, the n0 polycrystalline silicon layer and the metal wiring 1
The position where the electrical connection with 1b is made is 5 on the base area.
However, the above electrical connection could be made on the element isolation insulating film 9. Therefore, the contact area of the connecting portion can be set to a required size without being limited by the area of the base region 5. Therefore, it is no longer necessary to provide an extra large area in the base region 5 for connection with the metal wiring 11a, making it possible to further reduce the area of the base region 5.

Furthermore, since the area of the junction between the base region 5 and the collector region 2 is reduced, the base-collector capacitance is reduced.

In this embodiment, since the electrode functioning as the collector electrode is formed on the back side of the substrate, there is no need to provide a collector electrode similar to the emitter electrode and base electrode on the front side of the substrate. Therefore, the proportion of the substrate occupied by one bipolar element is reduced.

In this way, the vertical pnp bipolar transistor of this example has a collector electrode formed on the back surface of the substrate, and a base region 5 and an emitter region 6 formed in a self-aligned manner using two polycrystalline silicon layers. As a result, the area occupied by one bipolar element on the substrate surface can be significantly reduced compared to the area occupied by one conventional lateral pnp bipolar transistor element.

Typically, the conventional 5 x 8 μm2 to 6 x 9 μl11
From the size of about 2 to about 3 x 5 μm2 to 4 in this example
The occupied area could be reduced to a size of approximately 6 μm2.

Furthermore, since the pnp bipolar transistor of this example has a vertical pnp structure, the pnp bipolar transistor of this example has a
There is no need for an n-type diffusion layer, which is necessary in a bihole transistor with a lateral pnp structure. Therefore, in the vertical pnp bipolar transistor of this embodiment, the latch-up problem that tends to occur due to the existence of the n-type diffusion layer that is in an electrically floating state is solved.

FIG. 2 shows a circuit diagram of the bl-CMOS inverter of this embodiment.

The bi-cMOS inverter of this embodiment includes the above-mentioned vertical pnp bipolar transistor element 24 whose collector is grounded, an npn bipolar transistor element 23 whose collector is connected to the power supply terminal 27, and whose source is the power supply terminal 27.
7 and whose drain is connected to the base of the npn bipolar transistor element 23; the source is grounded and the drain is connected to the base of the vertical pnp bipolar transistor element 24; and the base of the npn bipolar transistor element 23. n connected with
type MOS transistor 22, an input section 25 connected to the gate of the n-type MOS transistor 21 and the gate of the n-type MOS transistor 22, the emitter of the vertical pnp bipolar transistor element 24, and the emitter of the npn bipolar transistor element 23. output section 26
It is equipped with.

As can be seen from FIG. 2, the input stage of the BL-CMOS inverter of this embodiment consists of an n-type MOS transistor 21 and an
type MOS transistor 22 is connected in a complementary manner.
This is an OS circuit, and its output stage has a horizontal npn bipolar transistor 23 and a vertical pnp bipolar transistor 24 connected in a complementary manner.

In this way, by configuring the output stage in such a way that the horizontal npn bipolar transistor 24 and the vertical pnp bipolar transistor 23 are connected in a complementary manner, the input stage is
type MOS transistor 21 and n type MOS transistor 2
2 could be connected in a complementary manner. Therefore, the number of transistors forming the bf-CMOS inverter of this embodiment is reduced to four.

Furthermore, since the vertical pnp bipolar transistor 24 of this embodiment has an emitter-base self-aligned structure,
The area occupied by the bf-CMOS inverter on the chip is reduced, and latch-up is less likely to occur.

Typically, the area of a conventional bi-CMOS inverter is about 20 x 7 μm to about 22 x 8 μm2, but the area of the bl-CMOS inverter of this embodiment is about 15 μm.
The size was approximately 5 μm to 18×6 μm2.

Furthermore, in order to operate the bl-CMOS inverter of this embodiment, it is not necessary to increase the gate voltage of the n-type MOS transistor 22 by the VSE of the npn bipolar transistor. Therefore, the conventional bi-C
The minimum operating voltage could be lower than that of a MOS inverter. Typically, the lowest conventional operating voltage is 3.0
However, the minimum operating voltage of this example was 2.3■.

This lowering of the minimum operating voltage prevents deterioration of the thin gate oxide film of the MOS transistor, and
The reliability of the S inverter has improved.

This effect is particularly evident in bi-CMOS devices that have minute MOS transistors with a gate length of about 1 μm or less.
This was noticeable in inverters.

(Effects of the Invention) As described above, according to the present invention, 1) a vertical bipolar transistor in which the np bipolar transistor has an emitter-base self-aligned structure is provided.

This vertical bipolar transistor occupies a smaller area on the substrate, and moreover, latch-up is less likely to occur.

Furthermore, in the bi-CMOS inverter of the present invention, the output stage is composed of npn bipolar transistors and the above-mentioned vertical pn
By using a configuration in which p bipolar transistors are connected complementary to each other, the input stage has an n-type MOS transistor and n
It is possible to have a simple configuration in which the type transistors are connected in a complementary manner.

Therefore, the number of transistors required to configure the bi-CMOS inverter of this embodiment is reduced to four.

Further, according to the configuration of the present invention, the minimum operating voltage of the bi-CMOS inverter can be reduced, and the minimum operating voltage of the bi-CMOS inverter can be reduced.
The reliability of the S inverter is improved.

This effect is particularly evident in BL-CMOS, which has a fine MOS transistor with a gate length of about 1 μm or less.
This is noticeable in inverters.

4. Don't worry! 1. FIG. 1 is a cross-sectional view showing a vertical pnp bipolar transistor according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing a BL-CMOS inverter equipped with the bipolar transistor of FIG. 1, and FIG. A circuit configuration diagram showing a bf-CMOS inverter, and FIG. 4 is a sectional view showing an npn bipolar transistor used in the inverter of FIG. 3.

DESCRIPTION OF SYMBOLS 1...p-type substrate, 2...p+ diffusion layer (collector region), 3...epitaxial layer, 4...element isolation film,
5... N1 diffusion layer (base region), 6... P+ diffusion layer (emitter region), 7... Base electrode, 8... Polycrystalline silicon emitter, 9... Interlayer insulating film, 10a,
10b...contact hole, lla, llb...
Metal wiring, 21... p-type MOS l-transistor, 22
...n-type MOS transistor, 23...horizontal npn
Bipolar transistor, 24... Vertical pnp bipolar transistor, 25... Input section, 26... Output section, 27... Power supply terminal.

that's all

Claims (1)

[Claims] 1. A p-type semiconductor substrate, a p-type collector region formed within the p-type semiconductor substrate, an n-type base region formed on the collector region, and within the base region. a p-type emitter region formed on the base region, a base electrode formed on the base region and electrically connected to the base region, and a base electrode formed on the emitter region and electrically connected to the base region. an emitter electrode, the base electrode contains an n-type impurity, the base region is an n-type diffusion layer in which the n-type impurity is diffused from the base electrode, and the emitter electrode includes: , a p-type impurity, and the emitter region is a p-type diffusion layer in which the p-type impurity is diffused from the emitter electrode. 2. The vertical PNP according to claim 1, wherein the collector is grounded.
a bipolar transistor element; a npn bipolar transistor element whose collector is connected to a power supply; a p-type MOS transistor whose source is connected to the power supply and whose drain is connected to the base of the npn bipolar transistor element; is an n-type MOS transistor connected to the base of the vertical pnp bipolar transistor element and the base of the npn bipolar transistor element, and an input section connected to the gate of the p-type MOS transistor and the gate of the n-type MOS transistor. and an emitter of the vertical pnp bipolar transistor element,
and an output section connected to the emitter of the npn bipolar transistor element, on the same substrate.