CA1097408A - Inverter in an integrated injection logic structure - Google Patents
Inverter in an integrated injection logic structureInfo
- Publication number
- CA1097408A CA1097408A CA256,414A CA256414A CA1097408A CA 1097408 A CA1097408 A CA 1097408A CA 256414 A CA256414 A CA 256414A CA 1097408 A CA1097408 A CA 1097408A
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- Prior art keywords
- transistor
- base
- emitter
- doped
- collector
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0761—Vertical bipolar transistor in combination with diodes only
- H01L27/0766—Vertical bipolar transistor in combination with diodes only with Schottky diodes only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0821—Combination of lateral and vertical transistors only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/091—Integrated injection logic or merged transistor logic
Abstract
ABSTRACT OF THE DISCLOSURE
There is herein disclosed an inverter of an integrated logic structure which is formed in a semiconductor device. More particularly, an epitaxial layer is formed on a semiconductor substrate. This layer includes a laterally arranged transistor and a vertically arranged transistor in side by side relationship. The collector of the lateral transistor is connected integrally with the base of the vertical transistor. The base of the lateral transistor is connected integrally with the emitter of the vertical transistor.
Supply voltage terminals are provided, one of which is connected to the emitter of the lateral transistor and the other of which is connected to the base of the lateral transistor as well as to the emitter of the vertical transistor. Diodes corresponding in number to the number of collectors in the vertical transistor are connected respectively in parallel with each base-collector junction of the vertical transistor and poled the same as the base-collector junctions. The emitter of the vertical transistor is formed as a buried layer in the semiconductor device. The lead from the outer surface to this buried layer is a highly doped zone, preferably formed by ion implantation.
Each inverter is separated from an adjacent inverter in the same semiconductor chip by suitable isolation means, such, for example, by an insulating guard ring of SiO2 or by pn junction isolation. The output is taken from the collectors of the vertical transistor.
There is herein disclosed an inverter of an integrated logic structure which is formed in a semiconductor device. More particularly, an epitaxial layer is formed on a semiconductor substrate. This layer includes a laterally arranged transistor and a vertically arranged transistor in side by side relationship. The collector of the lateral transistor is connected integrally with the base of the vertical transistor. The base of the lateral transistor is connected integrally with the emitter of the vertical transistor.
Supply voltage terminals are provided, one of which is connected to the emitter of the lateral transistor and the other of which is connected to the base of the lateral transistor as well as to the emitter of the vertical transistor. Diodes corresponding in number to the number of collectors in the vertical transistor are connected respectively in parallel with each base-collector junction of the vertical transistor and poled the same as the base-collector junctions. The emitter of the vertical transistor is formed as a buried layer in the semiconductor device. The lead from the outer surface to this buried layer is a highly doped zone, preferably formed by ion implantation.
Each inverter is separated from an adjacent inverter in the same semiconductor chip by suitable isolation means, such, for example, by an insulating guard ring of SiO2 or by pn junction isolation. The output is taken from the collectors of the vertical transistor.
Description
~97~8 This invention relates to an inverter in an integrated injection loyic (,I L) structure which includes a bipolar lateral transistor and a vertical transistor. Inyerters of this type are kno~n. For example, in the publication of "N.C. Troye Integrated Injection Logic - Present and Future", IEEE ISSCC, 1974, an arrangement of this type is. described. An integrated injection logic of this type is a saturated logic. This means that the storage time i.n the determination of its speed is a decisive factor. The lessening o~ the storage time has the highest significance attached to it ins.ofar as it implies a :
higher speed which has: great.signi.fi.cance in large scale integxation (LSI).
A principal object of the present inYention consists accordingly in providing an inverte:r stage in ~hich the storage time is considerabl~ reduced as compared ~ith the inverter stages of the prior art.
Thi:s objecti.ve i.s accompli,shed by an inverter stage .:
structure h.erei,nafte~ to be des.cribed. In parti.cular, the inverter stage of the present inventiQn compri.ses a substrate, .
an epitaxial layer on the substrate, a lateral transi,stor h.aying emittexr base and collector regions and a yertical transistor formed s~ide b~ side in the epitaxial layer having an ~.
emitter region, a base region and at least two collector regions, a pair of supply voltage source terminals, the collector regi,on of the lateral transistor b.eing connected to the base region of the vertical transistor, the emitter region of the vertical transistor and the base region of the lateral transistor being connected to one of the terminals. of the supply voltage source, the emitter of the lateral transistor being connected to the other of the terminals of said supply voltage 7~08 source, and a diode connected in parallel to each base-collector junction of the vertical transistor, the diode being poled the same as the base-collector junctions.
An essential advantage of the invention consists in the fact that, as a result of the production of the base region of the vertical npn transistor of the inverter stage by means of ion implantation, a drift field is simultaneously produced which reduces the switching time of the inverter.
Advantageously the inverse current amplification is further increased by the greater collector surface of the additional collector area.
Advantageousl~r, no substantially greater surface requirement is necessary for the construction of the inventive inverter than for the construction of the in~erter of the prior art.
A further advantage of the invention consists in the fact that the production process need only be substantially altered by an add~tional standard process, and it is thus largely compatible with other circuits.
Advantageously, the inverter of this inyention can be applied in an~ desired logic circuit for inyersely operated transistors.
According to a broad aspect of the invention there is provided an inverter comprising a first transistor having an emitter, a base and a collector, a second transistor having an emitter, a base and at least two collectors, a pair of supply voltage terminals, said collector of said first transistor being connected to said base of said second transistor, said emitter of said second transis-tor being connected to the base of said first transistor and to one of said terminals, said ~7~
emitter of said first transistor bein~ connected to the other of said terminals, and diodes connected i.n parallel to the junctions between the bas-e and the collectors of said second transistor, said diodes being poled the same as said collector-base junctions.
The invention is explained in the following with the help of the Figures and the specification.
Figure 1 is a cireuit diagram of one preferred embodiment of an inverter stage having the features of the present invention; ~-~
Figure 2 is a partial secti.onal vie~ diagrammatically .
illustrating an inverter stage whose circuit diagram is formed in Figure l; and Figure 3 shows the transmi.ssion eharaeteri.stie of a eonventional inverter and also the transmission eharaeteristics ;
of an inverter aeeording to this invention.
The eleetrieal eireuit of an inverter stage in an integrated injeetion logie of this invention is shown in Figure 1. Th~s includes a lateral bipolar pnp junction transistor 1 and a verti.eal bipolar npn junction transistor 2.
Voltage supply source terminals 111 and 131 are provided, the : terminal 13I being the reference potential such as ground.
The emitter 11 of the lateral transistor 1 is connected to the voltage terminal 111, while the base 13 of this transistor is connected to the reference voltage terminal 131.
The collector 12 o~ the transistor 1 is directly connected to the base 24 of the vertical transistor 2. The emitter ~ of the transistor 2 is connected to the reference voltage terminal 131. The transistor 2 is provided with two or more collectors ~, 23, which are connected to output terminals 25. Schottky 4~8 diodes 31 and 33 are connected parallel to the base-collector junction of the transistor 2 and are poled the same as the base-collector junction. The output of the preceding stage is connected to terminal 241, which is connected to the base 24 of transistor 2.
The following considerations are attributed to the invention. A lowering of the storage time of the inverter can be achieved in that the over-excitation of the vertical npn-transistor 2, located in the saturation region, is either lessened or prevented. The over-excitation can be inventively reduced with the aid of a Schottky diode 31 to 33, which is, in each case, arranged parallel to a collector-base junction -~, 24, and 23, 24, respectively.
In Figure 2, the substrate on which the inventive circuit is constructed is des'ignated as 10. Pre~erably, the substrate involved here is a p doped silicon substrate. The inventive circuit can, however, be constructed in a ESFI ~ -(,SOS)-technique. ESFI stands for Epitaxial Silicon Films - on Insulators and SOS stands for Silicon on Sapphire. In this case, the substrate 10 would consist of sapphire or spinel.
On the substrate 10, an n~ conductive layer 132 ~hich will later become a buried layer, is arranged by means of diffusion.
On the layer 132, a layer 22 of n type conductivity is epitaxially deposited. By up diffusion, the thickness of the layer 132 is enlarged by causing the adjacent portion of the layer 22 to be changed from n type doping to n~ type doping.
With the aid of an ion implantation step, the p conductive areas 11 and 12, 24 are formed in the surface of layer 22 in the manner to be seen from Figure 2.
The zone 11 forms the emitter region 11 of the lateral J.lD974~l!3 pnp transistor 1, and the zone 12 forms the collector. The ;
base 13 of this transistor is a part of the epitaxial layer 22, which is left between the emitter 11 and the collector 12.
As seen in Figure 2, it will be noted that the collector 12 is, in effect, part of the diffused zone 24, which becomes the base of the vertical transistor 2, while the portion 22 lying below the base 24 forms the emitter of the transistor 2. Into the upper surface of the portion 24 of p type conductivity, an n type conductivity diffused zone 21/23 is formed to provide the collector 21 and 23 of the vertical transistor 2. In order to form an ohmic contact to the emitter 11, a p+ electrode 110 is formed in the upper surface of the emitter 11. In order to form an ohmic contact with -the collector 12 of transistor 1, a p+ zone 2~2 extends down from the outer surface into contact with the diffused region 24 which includes the upwardly rising n portion 12, which forms the collec:tor of the transistor 1.
n~ regions 250 provide ohmic contact.s to the diffused region 22, which provides the collectors of the vertical transistor 2.
An insulating layer 20 is applied to the device around the two transistors to provide isolation. This insulation may, for example, be silicon dioxide. The huried layer 132 extends out to one side of the vertical transistor 2, and then rises : to the surface where a metal contact, preferably aluminum is in contact wi.th. it. Aluminum contacts are also pro~ided for the areas 110, 250 and 242. Electrodes 110, 250 and 242 are connected, respectively, to terminals 111, 25 and 241.
The n type conductive layer or region 22 may also be produced by ion implantation.
Seen electrically, it will be noted that the base 13 is part of the layer 22, and is hence electrically connected to ~ .
1~74(~
the buried layer 132. Thus, the buried layer 132 represents the base connection regi.on for the lateral transistor 1, and i.s connected to the reference potential terminal 131. The collector area 12 of the lateral transistor 1 is, at the same time, connected to the base area 24 of the verti.cal transistor
higher speed which has: great.signi.fi.cance in large scale integxation (LSI).
A principal object of the present inYention consists accordingly in providing an inverte:r stage in ~hich the storage time is considerabl~ reduced as compared ~ith the inverter stages of the prior art.
Thi:s objecti.ve i.s accompli,shed by an inverter stage .:
structure h.erei,nafte~ to be des.cribed. In parti.cular, the inverter stage of the present inventiQn compri.ses a substrate, .
an epitaxial layer on the substrate, a lateral transi,stor h.aying emittexr base and collector regions and a yertical transistor formed s~ide b~ side in the epitaxial layer having an ~.
emitter region, a base region and at least two collector regions, a pair of supply voltage source terminals, the collector regi,on of the lateral transistor b.eing connected to the base region of the vertical transistor, the emitter region of the vertical transistor and the base region of the lateral transistor being connected to one of the terminals. of the supply voltage source, the emitter of the lateral transistor being connected to the other of the terminals of said supply voltage 7~08 source, and a diode connected in parallel to each base-collector junction of the vertical transistor, the diode being poled the same as the base-collector junctions.
An essential advantage of the invention consists in the fact that, as a result of the production of the base region of the vertical npn transistor of the inverter stage by means of ion implantation, a drift field is simultaneously produced which reduces the switching time of the inverter.
Advantageously the inverse current amplification is further increased by the greater collector surface of the additional collector area.
Advantageousl~r, no substantially greater surface requirement is necessary for the construction of the inventive inverter than for the construction of the in~erter of the prior art.
A further advantage of the invention consists in the fact that the production process need only be substantially altered by an add~tional standard process, and it is thus largely compatible with other circuits.
Advantageously, the inverter of this inyention can be applied in an~ desired logic circuit for inyersely operated transistors.
According to a broad aspect of the invention there is provided an inverter comprising a first transistor having an emitter, a base and a collector, a second transistor having an emitter, a base and at least two collectors, a pair of supply voltage terminals, said collector of said first transistor being connected to said base of said second transistor, said emitter of said second transis-tor being connected to the base of said first transistor and to one of said terminals, said ~7~
emitter of said first transistor bein~ connected to the other of said terminals, and diodes connected i.n parallel to the junctions between the bas-e and the collectors of said second transistor, said diodes being poled the same as said collector-base junctions.
The invention is explained in the following with the help of the Figures and the specification.
Figure 1 is a cireuit diagram of one preferred embodiment of an inverter stage having the features of the present invention; ~-~
Figure 2 is a partial secti.onal vie~ diagrammatically .
illustrating an inverter stage whose circuit diagram is formed in Figure l; and Figure 3 shows the transmi.ssion eharaeteri.stie of a eonventional inverter and also the transmission eharaeteristics ;
of an inverter aeeording to this invention.
The eleetrieal eireuit of an inverter stage in an integrated injeetion logie of this invention is shown in Figure 1. Th~s includes a lateral bipolar pnp junction transistor 1 and a verti.eal bipolar npn junction transistor 2.
Voltage supply source terminals 111 and 131 are provided, the : terminal 13I being the reference potential such as ground.
The emitter 11 of the lateral transistor 1 is connected to the voltage terminal 111, while the base 13 of this transistor is connected to the reference voltage terminal 131.
The collector 12 o~ the transistor 1 is directly connected to the base 24 of the vertical transistor 2. The emitter ~ of the transistor 2 is connected to the reference voltage terminal 131. The transistor 2 is provided with two or more collectors ~, 23, which are connected to output terminals 25. Schottky 4~8 diodes 31 and 33 are connected parallel to the base-collector junction of the transistor 2 and are poled the same as the base-collector junction. The output of the preceding stage is connected to terminal 241, which is connected to the base 24 of transistor 2.
The following considerations are attributed to the invention. A lowering of the storage time of the inverter can be achieved in that the over-excitation of the vertical npn-transistor 2, located in the saturation region, is either lessened or prevented. The over-excitation can be inventively reduced with the aid of a Schottky diode 31 to 33, which is, in each case, arranged parallel to a collector-base junction -~, 24, and 23, 24, respectively.
In Figure 2, the substrate on which the inventive circuit is constructed is des'ignated as 10. Pre~erably, the substrate involved here is a p doped silicon substrate. The inventive circuit can, however, be constructed in a ESFI ~ -(,SOS)-technique. ESFI stands for Epitaxial Silicon Films - on Insulators and SOS stands for Silicon on Sapphire. In this case, the substrate 10 would consist of sapphire or spinel.
On the substrate 10, an n~ conductive layer 132 ~hich will later become a buried layer, is arranged by means of diffusion.
On the layer 132, a layer 22 of n type conductivity is epitaxially deposited. By up diffusion, the thickness of the layer 132 is enlarged by causing the adjacent portion of the layer 22 to be changed from n type doping to n~ type doping.
With the aid of an ion implantation step, the p conductive areas 11 and 12, 24 are formed in the surface of layer 22 in the manner to be seen from Figure 2.
The zone 11 forms the emitter region 11 of the lateral J.lD974~l!3 pnp transistor 1, and the zone 12 forms the collector. The ;
base 13 of this transistor is a part of the epitaxial layer 22, which is left between the emitter 11 and the collector 12.
As seen in Figure 2, it will be noted that the collector 12 is, in effect, part of the diffused zone 24, which becomes the base of the vertical transistor 2, while the portion 22 lying below the base 24 forms the emitter of the transistor 2. Into the upper surface of the portion 24 of p type conductivity, an n type conductivity diffused zone 21/23 is formed to provide the collector 21 and 23 of the vertical transistor 2. In order to form an ohmic contact to the emitter 11, a p+ electrode 110 is formed in the upper surface of the emitter 11. In order to form an ohmic contact with -the collector 12 of transistor 1, a p+ zone 2~2 extends down from the outer surface into contact with the diffused region 24 which includes the upwardly rising n portion 12, which forms the collec:tor of the transistor 1.
n~ regions 250 provide ohmic contact.s to the diffused region 22, which provides the collectors of the vertical transistor 2.
An insulating layer 20 is applied to the device around the two transistors to provide isolation. This insulation may, for example, be silicon dioxide. The huried layer 132 extends out to one side of the vertical transistor 2, and then rises : to the surface where a metal contact, preferably aluminum is in contact wi.th. it. Aluminum contacts are also pro~ided for the areas 110, 250 and 242. Electrodes 110, 250 and 242 are connected, respectively, to terminals 111, 25 and 241.
The n type conductive layer or region 22 may also be produced by ion implantation.
Seen electrically, it will be noted that the base 13 is part of the layer 22, and is hence electrically connected to ~ .
1~74(~
the buried layer 132. Thus, the buried layer 132 represents the base connection regi.on for the lateral transistor 1, and i.s connected to the reference potential terminal 131. The collector area 12 of the lateral transistor 1 is, at the same time, connected to the base area 24 of the verti.cal transistor
2. Beneath the p doped base area 24, the n doped emitter area 22 i.s interfaced therewith, and thus provides the emitter of the inversely operated yerti.cal transistor 2. As hereinbefore stated, the emitter area ~ is connected directly to the buried layer 132, s~ince it is interfaced th:erewith..
It will also be observed that during the process of construction of the disclosed device, the p~ areas 110 and 242 may be produced at the same time.
. In the place of oxide insulation ~eing used for isolation, pn isolation may be used.
In arrangements in which only pure integrated injection logic structures are arranged on a substrate, the isolating ~ provided by insulation 20 may be dispensed w;.th, since there i the layer 132 is al~ays connected to the reference potential.
In this situation, it ~s preferable that the reference potential be ground.
Since only yerX small voltages occur with integrated injection loglcs, p doped protective rings, which, in Schottky junctions- in other logic arrangements, are provided in a blocking direction for improving the diode characteristics, are unnecessary-in th.e $chottky junctions.
In Figure 2, for the sake of simplicity, only the collector regions 21 and 23 are represented. In reality, many more collector regi.ons may be provided which together form the output 25.
740~ .
By means of the arrangement of the base connection electrode region 242 depicted in the Figure, it is achieved that areas 21 and 23 are insulated from one another.
The manner of functioning of the vertical npn trans-istor 2 with a Schottky clamp diode does not change statically in the active and in the blocking regions, since the Schottky diode is also biased in blocking direction. Then, only the capacitance of the diode is paralleI to the collector-base capacitance, and only has a disad~antageous influence on the rise times and deIa~ times as long as the charge exchange of the capacitances is decisive. In the saturation region, on the `~
other hand, not only the collector-base junction, but also the Schottky diode is biased in the flow direction. I~ the threshold voltage of the Schottky diode is smaller than that across the collector-base junction, then the back injection current flows for the most part through the Schottky diode.
Since the effect of the charge storage in the Schottky diode is smaller by several orders of magnitude, the storage time is considerabl~ reduced. The Schottk~ dioae has the further effect that, because of its smaller threshold voltage, the collector-emitter saturation voltage is increased. In this way, the yoltage difference between the logical states is reduced.
In Figure 3, this is depicted on th~ basis of the characteristic curves of an inverter of the prior art and of the inverter of the present invention, i.e. output voltage (at 25 in Figure l~ vs. input voltage (at 241 in Figure 1).
Therein, the characteristic curve of the prior art inverter is represented b~ a broken line, and the characteristic curve of the inventive inverter by an unbroken line. The voltage rise ~974i~8 change referred to amounts to U~SO-U~so~ The smaller voltage rise with the inventi~e circuit does: not h.ave a disadvantageous effect on the noise margin of the circuit, since, in this circuit, only the greater noise margin U'SO is reduced and not the critical s~aller noise margin Usl. This noise margin corresponds exactly to tl~e noise margin of the prior art circuits. The smaller voltage rise, on the other hand, has an advantageous effect on the decay and rise times, since the capacitances in the collector-base junction of the transistor 2 and other line capacitances having more rapid charge exchange.
Advantageously, the smaller voltage rise which has the above described effect on the rise and decay time, compensates against the effect, described further above, of the . additional capacitance of the Schottky diode.
By means of the inventive arran~ement of the base connection region 242, which connects directly to the collector regions 21 and 23, it is achieved that the ratio between the collector-base junction surface to the base-emitter junction surface becomes more favourable than this ratio is in the prior art arrangements. This ratio is more favourable there, since there the collector areas are separately diffused-in, whereas, in the present invention, they are ini.tiall~ diffused-in as one area, which i.s subsequently separated by the base connection area 242.
It will be apparent to those ski.lled in the art that many modifications and variati.ons may be effected without departing from the spirit and scope of the novel concepts of the present invention.
, :
It will also be observed that during the process of construction of the disclosed device, the p~ areas 110 and 242 may be produced at the same time.
. In the place of oxide insulation ~eing used for isolation, pn isolation may be used.
In arrangements in which only pure integrated injection logic structures are arranged on a substrate, the isolating ~ provided by insulation 20 may be dispensed w;.th, since there i the layer 132 is al~ays connected to the reference potential.
In this situation, it ~s preferable that the reference potential be ground.
Since only yerX small voltages occur with integrated injection loglcs, p doped protective rings, which, in Schottky junctions- in other logic arrangements, are provided in a blocking direction for improving the diode characteristics, are unnecessary-in th.e $chottky junctions.
In Figure 2, for the sake of simplicity, only the collector regions 21 and 23 are represented. In reality, many more collector regi.ons may be provided which together form the output 25.
740~ .
By means of the arrangement of the base connection electrode region 242 depicted in the Figure, it is achieved that areas 21 and 23 are insulated from one another.
The manner of functioning of the vertical npn trans-istor 2 with a Schottky clamp diode does not change statically in the active and in the blocking regions, since the Schottky diode is also biased in blocking direction. Then, only the capacitance of the diode is paralleI to the collector-base capacitance, and only has a disad~antageous influence on the rise times and deIa~ times as long as the charge exchange of the capacitances is decisive. In the saturation region, on the `~
other hand, not only the collector-base junction, but also the Schottky diode is biased in the flow direction. I~ the threshold voltage of the Schottky diode is smaller than that across the collector-base junction, then the back injection current flows for the most part through the Schottky diode.
Since the effect of the charge storage in the Schottky diode is smaller by several orders of magnitude, the storage time is considerabl~ reduced. The Schottk~ dioae has the further effect that, because of its smaller threshold voltage, the collector-emitter saturation voltage is increased. In this way, the yoltage difference between the logical states is reduced.
In Figure 3, this is depicted on th~ basis of the characteristic curves of an inverter of the prior art and of the inverter of the present invention, i.e. output voltage (at 25 in Figure l~ vs. input voltage (at 241 in Figure 1).
Therein, the characteristic curve of the prior art inverter is represented b~ a broken line, and the characteristic curve of the inventive inverter by an unbroken line. The voltage rise ~974i~8 change referred to amounts to U~SO-U~so~ The smaller voltage rise with the inventi~e circuit does: not h.ave a disadvantageous effect on the noise margin of the circuit, since, in this circuit, only the greater noise margin U'SO is reduced and not the critical s~aller noise margin Usl. This noise margin corresponds exactly to tl~e noise margin of the prior art circuits. The smaller voltage rise, on the other hand, has an advantageous effect on the decay and rise times, since the capacitances in the collector-base junction of the transistor 2 and other line capacitances having more rapid charge exchange.
Advantageously, the smaller voltage rise which has the above described effect on the rise and decay time, compensates against the effect, described further above, of the . additional capacitance of the Schottky diode.
By means of the inventive arran~ement of the base connection region 242, which connects directly to the collector regions 21 and 23, it is achieved that the ratio between the collector-base junction surface to the base-emitter junction surface becomes more favourable than this ratio is in the prior art arrangements. This ratio is more favourable there, since there the collector areas are separately diffused-in, whereas, in the present invention, they are ini.tiall~ diffused-in as one area, which i.s subsequently separated by the base connection area 242.
It will be apparent to those ski.lled in the art that many modifications and variati.ons may be effected without departing from the spirit and scope of the novel concepts of the present invention.
, :
Claims (12)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An inverter comprising a first transistor having an emitter, a base and a collector, a second transistor having an emitter, a base and at least two collectors, a pair of supply voltage terminals, said collector of said first transistor being connected to said base of said second transistor, said emitter of said second transistor being connected to the base of said first transistor and to one of said terminals, said emitter of said first transistor being connected to the other of said terminals, and diodes connected in parallel to the junctions between the base and the collectors of said second transistor, said diodes being poled the same as said collector-base junctions.
2. An inverter in an integrated injection logic structure comprising a substrate, an epitaxial layer on said substrate, a lateral transistor having emitter, base and collector regions, and a vertical transistor formed side by side in said epitaxial layer having an emitter region, a base region and at least two collector regions, a pair of supply voltage source terminals, said collector region of said lateral transistor being connected to said base region of said vertical transistor, said emitter region of said vertical transistor and said base region of said lateral transistor being connected to one of said terminals of the supply voltage source, said emitter of said lateral transistor being connected to the other of said terminals of said supply voltage source, and a diode connected in parallel to each base-collector junction of the vertical transistor, said diode being poled the same as said base-collector junctions.
3. An inverter stage in an integrated logic structure comprising a substrate, an n doped epitaxial layer on said substrate, a pair of p doped regions in the surface of said epitaxial layer spaced from each other, one of said p doped regions forming the emitter of a lateral transistor, the portion of said n type epitaxial layer lying between said p doped regions forming the base of said lateral transistor, the portion of the other of said pair of p doped regions which lies adjacent said base portion of said epi-taxial layer forming the collector of said lateral transistor, the remaining portion of said other of said pair of p doped regions forming the base of a vertical transistor, the portion of said epitaxial layer lying below said base of said vertical transistor forming the emitter of said vertical transis-tor, at least two n doped regions formed in the surface of said p doped base portion forming collectors, respectively of said vertical transistor, p+ doped contacts formed in the surface portion of said emitter of the lateral tran-sistor and said collectors of said lateral transistor, a p+ region between said collectors of said vertical transistor which extends down to said base of said vertical transistor which also forms pn junctions with said collectors, a metal electrode in contact with said collectors of said vertical transistor and also in contact with said p+ region leading to said base of said vertical transistor and thereby providing Schottky diodes with said collectors of said vertical transistor, a layer of insulating material surrounding said inverter stage, a buried n+ doped buried layer partially in said substrate and partially in said epitaxial layer which is interfaced with said n doped epi-taxial layer and which reaches out to the surface through said insulating layer, and an electrode on said p+ doped contact of the emitter of said lateral transistor connected to one terminal of an electric potential source, and an emitter electrode in contact with the surface portion of said buried layer connected to the other terminal of said electric potential source.
4. An inverter stage in an integrated logic structure comprising a substrate, a p doped epitaxial layer on said substrate, a pair of n doped regions in the surface of said epitaxial layer spaced from each other, one of said n doped regions forming the emitter of a lateral transistor, the portion of said p type epitaxial layer lying between said n doped regions forming the base of said lateral transistor, the portion of the other of said pair of n doped regions which lies adjacent said base portion of said epitaxial layer forming the collector of said lateral transistor, the re-maining portion of said other of said pair of n doped regions forming the base of a vertical transistor, the portion of said epitaxial layer lying below said base of said vertical transistor forming the emitter of said vertical transistor, at least two p doped regions formed in the surface of said n doped base portion forming collectors, respectively, of said vertical transistor, n+ doped contacts formed in the surface portion of said emitter and said collector of said lateral transistor, an n+ region between said collectors of said vertical transistor which extends down to said base of said vertical transistor which also forms pn junctions with said collector regions, a metal electrode in contact with said collectors of said vertical transistor and also in contact with said n region leading to said base of said vertical transistor and thereby providing Schottky diodes with said collector regions of said vertical transistor, a layer of insulating material surrounding each inverter stage, a buried p+ doped buried layer partially in said substrate and partially in said epitaxial layer which is interfaced with said p doped epitaxial layer and which reaches out to the surface through said insulating layer, and an electrode on said n+ doped contact of the emitter of said lateral transistor connected to one terminal of an electric potential source, and an emitter electrode in contact with the sur-face portion of said buried layer connected to the other terminal of said electric potential source.
5. An inverter stage according to claim 3, in which said substrate is of a p conductive type semiconductor material.
6. An inverter stage according to claim 4, in which said substrate is of an n conductive type semiconductor material.
7. An inverter stage according to claim 3, in which said substrate is formed of sapphire or spinel.
8. An inverter stage according to claim 4, in which said substrate is formed of sapphire or spinel.
9. An inverter stage according to claim 3, in which said buried layer and said n doped epitaxial layer consist of silicon.
10. An inverter stage according to claim 4, in which said buried layer and said p doped epitaxial layer consist of silicon.
11. An inverter stage according to claim 3, in which oxide insulations are provided for insulating in said inverter stage.
12. An inverter stage according to claim 4, in which pn junction isolation is provided for insulating in said inverter stage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP2530292.5 | 1975-07-07 | ||
| DE19752530292 DE2530292A1 (en) | 1975-07-07 | 1975-07-07 | INVERTER IN AN I HIGH 2 L STRUCTURE |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1097408A true CA1097408A (en) | 1981-03-10 |
Family
ID=5950888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA256,414A Expired CA1097408A (en) | 1975-07-07 | 1976-07-06 | Inverter in an integrated injection logic structure |
Country Status (6)
| Country | Link |
|---|---|
| CA (1) | CA1097408A (en) |
| CH (1) | CH609172A5 (en) |
| DE (1) | DE2530292A1 (en) |
| FR (1) | FR2317818A1 (en) |
| GB (1) | GB1551133A (en) |
| IT (1) | IT1067525B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4542331A (en) * | 1983-08-01 | 1985-09-17 | Signetics Corporation | Low-impedance voltage reference |
| US4871686A (en) * | 1988-03-28 | 1989-10-03 | Motorola, Inc. | Integrated Schottky diode and transistor |
-
1975
- 1975-07-07 DE DE19752530292 patent/DE2530292A1/en not_active Withdrawn
-
1976
- 1976-06-01 CH CH683376A patent/CH609172A5/en not_active IP Right Cessation
- 1976-06-23 FR FR7619141A patent/FR2317818A1/en active Granted
- 1976-07-02 IT IT2496076A patent/IT1067525B/en active
- 1976-07-06 CA CA256,414A patent/CA1097408A/en not_active Expired
- 1976-07-06 GB GB2800376A patent/GB1551133A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CH609172A5 (en) | 1979-02-15 |
| FR2317818A1 (en) | 1977-02-04 |
| DE2530292A1 (en) | 1977-01-20 |
| FR2317818B1 (en) | 1981-09-25 |
| GB1551133A (en) | 1979-08-22 |
| IT1067525B (en) | 1985-03-16 |
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| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |