JPS6156624B2 - - Google Patents
Info
- Publication number
- JPS6156624B2 JPS6156624B2 JP51129199A JP12919976A JPS6156624B2 JP S6156624 B2 JPS6156624 B2 JP S6156624B2 JP 51129199 A JP51129199 A JP 51129199A JP 12919976 A JP12919976 A JP 12919976A JP S6156624 B2 JPS6156624 B2 JP S6156624B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- transistor
- type
- conductivity type
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims 2
- 238000002955 isolation Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 238000009413 insulation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0244—I2L structures integrated in combination with analog structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体集積回路、特にI2L（インテグ
レイテツド・インジエクシヨン・ロジツク）とア
ナログ回路が同一チツプ上に共存しているバイポ
ーラ集積回路に関すするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and particularly to a bipolar integrated circuit in which an I 2 L (Integrated Injection Logic) and an analog circuit coexist on the same chip.
I2Lの特長の一つに、同一チツプ上にデイジタ
ル回路とアナログ回路を同時に実現できることが
上げられる。しかしデイジタル回路に高速が要求
され、しかもアナログ回路の信号レベルが高いよ
うな場合には、同一チツプ上に両者を共存させる
ことは困難である。第１図に従来のI2Lとアナロ
グ回路が同一チツプ上に形成された半導体集積回
路の断面図を示す。１はｐ型半導体基板、２は
n+埋込層、３はｎ型エピタキシヤル層、４はｐ
型絶縁分離層、５はn+カラー領域、６はｐ型
層、７はn+層で、Ａ部にアナログ回路、Ｂ部に
I2Lによるデイジタル回路が形成されている。第
１図の構造でデイジタル回路を高速にしようとす
ると、エピタキシヤル層３の濃度を上げかつ厚さ
を薄くしてn+埋込層２とベース領域であるｐ型
層６の距離をできるだけ短かくする必要がある。
一方これはトランジスタのベース・コレクタ間耐
圧を低くすることにつながるから、I2Lを高速化
しようとすればアナログ回路の電源電圧を高くす
ることができなくなつてしまう。I2Lは通常１ボ
ルト以下で動作するが、一方アナログ回路は数ボ
ルトから30ボルトの電源電圧で動作するのが普通
である。従つてトランジスタ耐圧もI2Lでは数ボ
ルトあればよく、アナログ回路ではその約十倍も
の耐圧が必要になる。この様に要求されるトラン
ジスタの特性が全く異なる二つの回路を、第１図
に示した同一のn+埋込層２を有する構造で実現
することには自ずから限界が生ずる。 One of the features of I2L is that it can simultaneously implement digital and analog circuits on the same chip. However, if high speed is required for the digital circuit and the signal level of the analog circuit is high, it is difficult to coexist on the same chip. FIG. 1 shows a cross-sectional view of a conventional semiconductor integrated circuit in which I 2 L and analog circuits are formed on the same chip. 1 is a p-type semiconductor substrate, 2 is
n + buried layer, 3 is n type epitaxial layer, 4 is p
Type insulation separation layer, 5 is n + color region, 6 is p-type layer, 7 is n + layer, analog circuit in A part, B part
A digital circuit is formed using I 2 L. In order to increase the speed of a digital circuit with the structure shown in Figure 1, the concentration of the epitaxial layer 3 is increased and the thickness is decreased to shorten the distance between the n + buried layer 2 and the p-type layer 6, which is the base region, as much as possible. It is necessary to do so.
On the other hand, this leads to lowering the transistor's base-collector breakdown voltage, so if you try to speed up I 2 L, you will not be able to increase the power supply voltage of the analog circuit. I 2 L typically operates at less than 1 volt, whereas analog circuits typically operate at supply voltages ranging from a few volts to 30 volts. Therefore, the transistor breakdown voltage only needs to be a few volts for I 2 L, whereas an analog circuit requires about ten times that voltage. There is a natural limit to realizing two circuits having completely different required transistor characteristics with the structure having the same n + buried layer 2 shown in FIG. 1.
本発明の目的は、デイジタル回路とアナログ回
路のトランジスタの特性を各々最適化して同一チ
ツプ上に形成できる半導体集積回路を提供するこ
とにある。 An object of the present invention is to provide a semiconductor integrated circuit that can be formed on the same chip by optimizing the characteristics of transistors in a digital circuit and an analog circuit.
本発明は高速デイジタル回路と比較的高耐圧な
アナログ回路を、ｐ型基板上に形成したｎ型井戸
と薄いエピタキシヤル層の組み合せで実現しよう
とするものである。以下実施例に従つて詳細を説
明する。 The present invention attempts to realize a high-speed digital circuit and a relatively high voltage analog circuit by combining an n-type well formed on a p-type substrate and a thin epitaxial layer. Details will be explained below according to examples.
第２図は本発明の一実施例を示す断面図であ
る。ｐ型基板１上の高耐圧が必要なトランジスタ
が作製されるべき部分に、トランジスタの耐圧に
見合つた濃度のｎ型井戸８が形成され、I2Lデバ
イスが作製されるべき部分に高濃度のアンチモン
或いはヒ素を拡散してなるn+埋込層２が形成さ
れている。また、厚さ１μｍないし５μｍ程度の
エピタキシヤル層３は上記ｎ型井戸８及びn+埋
込層２を含むｐ型基板上に形成されている。この
エピタキシヤル層の濃度はI2Lのスピートとアナ
ログ回路の電源電圧とのかね合いから決定され
る。通常1016cm-3前後の濃度が選ばれる。アナロ
グ回路の部分に絶縁分離用のｐ型領域４、I2Lの
部分にN+カラー領域５がそれぞれ形成されてい
る。このN+カラー領域５はアナログ回路のトラ
ンジスタのコレクタ取り出し用としても用いる。
ｐ型層６はI2L回路及びアナログ回路のnpnトラ
ンジスタのベース領域である。n+層７はI2Lの
npnトランジスタのコレクタ及びアナログ回路の
トランジスタのエミツタである。なお、通常のコ
ンタクト窓、金属配線等は図示していない。 FIG. 2 is a sectional view showing an embodiment of the present invention. An n-type well 8 with a concentration commensurate with the transistor's breakdown voltage is formed in a portion of the p-type substrate 1 where a transistor that requires a high breakdown voltage is to be fabricated, and a high-concentration well 8 is formed in a portion where an I 2 L device is to be fabricated. An n + buried layer 2 is formed by diffusing antimony or arsenic. Further, an epitaxial layer 3 having a thickness of approximately 1 μm to 5 μm is formed on the p-type substrate including the n-type well 8 and the n + buried layer 2 . The concentration of this epitaxial layer is determined by the balance between the speed of I 2 L and the power supply voltage of the analog circuit. Usually a concentration around 10 16 cm -3 is chosen. A p-type region 4 for insulation isolation is formed in the analog circuit portion, and an N + color region 5 is formed in the I 2 L portion. This N + color area 5 is also used for extracting the collector of a transistor in an analog circuit.
The p-type layer 6 is the base region of the npn transistor of the I 2 L circuit and the analog circuit. n + layer 7 is I 2 L
It is the collector of an npn transistor and the emitter of a transistor in an analog circuit. Note that normal contact windows, metal wiring, etc. are not shown.
本発明の主な効果は次の通りである。 The main effects of the present invention are as follows.
(1) 比較的濃度が高くかつ薄いエピタキシヤル層
を用いることができるので、I2Lのスピード及
び性能指数を改善することができる。(1) Relatively dense and thin epitaxial layers can be used, improving I 2 L speed and figures of merit.
(2) ｎ型井戸をｐ型基板上に設けることにより、
薄いエピタキシヤル層にもかかわらず、アナロ
グ回路の耐圧を増加できる。(2) By providing an n-type well on a p-type substrate,
Despite the thin epitaxial layer, the breakdown voltage of analog circuits can be increased.
(3) アナログ回路の絶縁分離領域に深いｐ型拡散
を行う必要がない。従つて横方向拡散の量が少
なく集積密度を上げるのに有利である。(3) There is no need to perform deep p-type diffusion in the isolation region of analog circuits. Therefore, the amount of lateral diffusion is small, which is advantageous for increasing the integration density.
(4) 薄いエピタキシヤル層が使えるから、エピタ
キシヤル成長時に発生するマウンド等の欠陥を
少なくすることができる。その結果歩留が増加
する。(4) Since a thin epitaxial layer can be used, defects such as mounds that occur during epitaxial growth can be reduced. As a result, yield increases.
(5) (3)に関連して、ｐ型絶縁層の代りに酸化物分
離を行うことが容易であり、集積密度を一層増
加させることができる。(5) Related to (3), it is easy to use oxide isolation instead of the p-type insulating layer, and the integration density can be further increased.
第３図は本発明の他の実施例を示す断面図で、
先きに説明した実施例で用いられているｐ型絶縁
分離層４の代りに、選択酸化による酸化シリコン
分離層９を用いたものである。本発明の方法では
薄いエピタキシヤル層を用いることができるか
ら、選択酸化で絶縁分離を行うことに製造上の困
難はない。 FIG. 3 is a sectional view showing another embodiment of the present invention,
In place of the p-type insulating isolation layer 4 used in the previously described embodiment, a silicon oxide isolation layer 9 formed by selective oxidation is used. Since the method of the present invention allows the use of thin epitaxial layers, there are no manufacturing difficulties in performing insulation isolation by selective oxidation.
第４図は更に他の実施例を示す断面図で、この
実施例はアナログ回路のｐ型絶縁分離層４をI2L
の不活性ベース領域及びラテラルpnpトランジス
タのエミツタ及びコレクタに用いるものである。
I2Lの不活性ベース領域に濃度を高くしたp+層を
n+埋込領域２に達する様に形成することは、少
数キヤリアの蓄積を減少させ、スイツチング・ス
ピードを上げることに効果がある。同時に不活性
ベースに流れるベース電流が減るため、I2Lトラ
ンジスタのβが増加し、最大フアン・アウト数が
増加する。 FIG. 4 is a sectional view showing still another embodiment, in which the p-type isolation layer 4 of the analog circuit is
It is used for the inactive base region of the transistor and the emitter and collector of the lateral PNP transistor.
A highly concentrated p + layer in the inactive base region of I2L
Forming it so as to reach the n + buried region 2 is effective in reducing the accumulation of minority carriers and increasing the switching speed. At the same time, the base current flowing through the inactive base is reduced, which increases the β of the I 2 L transistor and increases the maximum fan-out number.
以上詳細に説明したように、本発明によれば、
同一チツプ上にそれぞれ高性能のデイジタル回路
とアナログ回路を設けることができるので半導体
集積回路に用いると非常に大きな効果がある。 As explained in detail above, according to the present invention,
Since high-performance digital circuits and analog circuits can be provided on the same chip, it is extremely effective when used in semiconductor integrated circuits.
第１図は従来のI2Lとアナログ回路が同一チツ
プ上に形成された半導体集積回路の断面図、第２
図ないし第４図はそれぞれ本発明の実施例の断面
図である。
１……ｐ型半導体基板、２……n+埋込層、３
……ｎ型エピタキシヤル層、４……ｐ型絶縁分離
層、５……n+カラー領域、６……ｐ型層、７…
…n+層、８……ｎ型井戸、９……酸化シリコン
分離層。
Figure 1 is a cross-sectional view of a conventional semiconductor integrated circuit in which I 2 L and analog circuits are formed on the same chip.
4 through 4 are sectional views of embodiments of the present invention, respectively. 1...p-type semiconductor substrate, 2...n + buried layer, 3
... n-type epitaxial layer, 4 ... p-type insulating separation layer, 5 ... n + color region, 6 ... p-type layer, 7 ...
. . . n + layer, 8 . . . n-type well, 9 . . . silicon oxide isolation layer.
Claims (1)
横型トランジスタとの組み合せ構造を含んでデイ
ジタル動作をするデイジタル動作部とバイポーラ
トランジスタを含んでアナログ動作をするアナロ
グ動作部とが形成された半導体集積回路におい
て、前記デイジタル動作部と前記アナログ動作部
とをそれぞれ構成する各トランジスタは一導電型
の前記半導体基板上に実質的に均一な厚さに形成
された他の導電型の半導体層に形成されており、
前記組み合せ構造下の前記半導体基板の表面部に
は前記他の導電型で高不純物濃度の第１の埋め込
み層を有し、前記バイポーラトランジスタの下の
前記半導体基板の表面部には前記他の導電型で低
不純物濃度の第２の埋め込み層が前記第１の埋め
込み層の厚さより厚く形成されていることを特徴
とする半導体集積回路。1. In a semiconductor integrated circuit in which a digital operation section that includes a combination structure of a reverse operation transistor and a lateral transistor and performs digital operation, and an analog operation section that includes bipolar transistors and performs analog operation are formed on a single semiconductor substrate. , each transistor constituting the digital operation section and the analog operation section is formed in a semiconductor layer of another conductivity type formed on the semiconductor substrate of one conductivity type to a substantially uniform thickness; ,
A surface portion of the semiconductor substrate under the combination structure has a first buried layer of the other conductivity type and a high impurity concentration, and a surface portion of the semiconductor substrate under the bipolar transistor has the other conductivity type. A semiconductor integrated circuit characterized in that a second buried layer having a low impurity concentration is formed thicker than the first buried layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12919976A JPS5353988A (en) | 1976-10-26 | 1976-10-26 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12919976A JPS5353988A (en) | 1976-10-26 | 1976-10-26 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5353988A JPS5353988A (en) | 1978-05-16 |
| JPS6156624B2 true JPS6156624B2 (en) | 1986-12-03 |
Family
ID=15003581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12919976A Granted JPS5353988A (en) | 1976-10-26 | 1976-10-26 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5353988A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5690554A (en) * | 1979-12-22 | 1981-07-22 | Toshiba Corp | Semiconductor device |
| JPH10340965A (en) * | 1997-06-10 | 1998-12-22 | Sony Corp | Semiconductor device and its manufacture |
-
1976
- 1976-10-26 JP JP12919976A patent/JPS5353988A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5353988A (en) | 1978-05-16 |
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