JPS6132823B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bipolar semiconductor device, particularly to a structure in which a PNP type transistor and an NPN type transistor are integrated.

More specifically, the present invention provides a first semiconductor region of one conductivity type serving as a base region (hereinafter referred to as base) and a base serving as a collector region (hereinafter referred to as collector) in at least one vertical transistor operating in the opposite direction. a second semiconductor region of an opposite conductivity type with a low impurity concentration, and at least one vertical transistor operating in the forward direction ( The present invention relates to a semiconductor device provided with a normal transistor (hereinafter referred to as NTR).

In addition, the present invention provides a shotgun type electrode on the top or top surface of the second semiconductor region or a similar region.

Conventionally, IIL (Integrated Injection
Logic) is known. This IIL has a PNP-type lateral transistor and a vertical transistor (hereinafter referred to as an inverted transistor, ITR) structure that operates in the opposite direction.
It is said to be an integrated combination of NPN transistors. This IIL is shown as a monolithic integrated circuit in, for example, Japanese Patent Publication No. 49-35030. Furthermore, for example, the English literature IEEE
Journal of Solid-State Circuits, Oct1973 332
An example of applying IIL to static bipolar memory is shown on page 337. In both of these, the constant current source is obtained using a PNP type lateral transistor. For this reason, the current amplification factor alpha α for a grounded base is small, and it was found that this IIL, despite having many features, has a serious drawback in that it does not function as a sufficient constant current source. This is especially true if the base width is the same as the diffusion depth (generally 1
It was found that the base length is determined not only by the width of the photoetching of the photomask, but also by the length of 3-10μ.

At the same time, although conventional IIL is generally said to have low power and delay time, its frequency response speed is slow, which is considered a major drawback in practical use. The present invention has discovered that such a drawback is caused not only by the structure of the current source described above, but also by the parasitic capacitance between the collector and base of the ITR and the fact that it takes time for fractional carriers in the collector region to disappear.

The present invention aims to eliminate these drawbacks at the same time, and by providing a sufficient margin for the current source of the PNP transistor, the frequency response speed can be increased, and the manufacturing process can be easily controlled. The structure of the present invention will be explained below with reference to the drawings and its manufacturing process.

FIG. 1 is a circuit diagram showing the configuration of the basic operation aimed at by the present invention. FIG. 1A shows an example of a general complementary transistor, and the transistor 2 as a constant current source has, for example, a PNP type, and the emitter is connected to terminal 4, the base is connected to terminal 7, and the collector is connected to terminal 1. ing. The collector 1 is connected to the base of another complementary transistor, that is, an NPN transistor 3, and also has a signal input terminal 5. This NPN transistor has a terminal 8 at its emitter and, for example, two collectors, which are connected to terminals 6 and 6'.

Figure 1B shows the base of PNP transistor 2 and
The emitters of the NPN transistors 3 have a common ground structure. In addition, two Schottky type diodes 10, 10' are equivalently provided by forming a Schottky type electrode on the collector of the transistor 3, and the diode 1
It is connected to output terminals 6 and 6' via terminals 0 and 10'. This circuit configuration is an example of a typical circuit having a so-called IIL structure and a shot collector.

FIG. 1C shows emitter input terminals 4 and 2 for a plurality of, for example, two PNP transistors 2 and 2'.
4', and these emitters are shot-type,
Alternatively, it is provided by a P ⁺ type semiconductor layer integrated on the base by a vapor phase method. For this reason, symbols are provided at the bases of transistors 2 and 2'. In this circuit, a common input terminal 5 is provided for each collector, and a collector is provided independently for each of the NPN transistors 3 and 3', and a shot-type electrode is provided for the collector, thereby equivalently forming a shot-type transistor. This is what formed a diode. Of course, the circuit shown in Fig. C may be designed in consideration of practicality, and the number of input terminals 5, injector input terminals 4, 4', and output terminals 6, 6', and the circuit configuration thereof may be modified according to the needs of the design. In this way, the present invention allows the emitter, base and collector of an NPN transistor to
In addition, the emitter, base ^{, and collector of a PNP transistor have not only a P + NP structure} but also an MNP structure. be. Of course, M means a Schottky type electrode, which essentially means here a state in which a junction corresponding to the P ⁺ semiconductor layer is formed.

In the above circuit configuration of FIG. 1, one feature is that the collector of at least one PNP transistor 2 is connected to at least one other NPN transistor 3.
is connected to the base of Furthermore, in a transistor of this complementary configuration, for example, an IIL structure, a collector region or emitter is always provided on the base of the transistor 3 as an ITR or NTR. The structure of the present invention has succeeded in making the previously known IIL structure easier to manufacture and reducing its frequency response speed in such a circuit configuration. An example manufacturing method and structure will be described.

FIG. 2 shows one embodiment of the present invention.
This is an example of fabricating a so-called IIL structure in which the terminals 7 and 8 in FIG. 1A are commonly connected and grounded as shown in FIG. 1B among the circuit configurations shown in the figures. However, of course, the structure of the present invention may also be applied as is to other circuits shown in FIG. 1 or to circuits to which they are applied.

In FIG. 2A, a semiconductor substrate 10 of one conductivity type
For example, in contrast to P or P ^- type, an N ⁺ type buried layer 11 with a high impurity concentration of semiconductor is selectively formed to a size required for the design by a thermal diffusion method. In addition, adjacent regions or TTL (Tranststor Transistor
A channel cut 32 was formed by implanting a P ⁺ type impurity into a region under the field insulator 13 between the region of the same semiconductor substrate required for Logic) by ion implantation or thermal diffusion. Thereafter, a single crystal first semiconductor region 12 having a P-type conductivity type and an impurity concentration of 10 ¹⁴ to 10 ¹⁸ cm ^-3 is epitaxially grown on these substrates to a thickness of 0.2 to 3 μm. , the first semiconductor region 12 has an N-type conductivity type and its impurity concentration is 10 ¹³ to 10 ¹⁷ cm ^-3
A single crystal second semiconductor region 26 is formed to have a thickness of 0.2 to 3 μm. This N or N ^- type second semiconductor region may be formed by implanting or diffusing impurities into the upper part of the first semiconductor region 12 by ion implantation or other methods. However, in order to more effectively achieve the main object of the present invention, the impurity concentration in the first semiconductor region 12 should be 10 ¹⁶ to 10 ¹⁸ cm ^-3
and the second semiconductor region 26 is 10 ¹⁴ to 10 ¹⁶ cm ^-3
It was hot. Thereafter, a film made of a composite film of an oxide film or a nitride film and having a masking effect against oxidizing gas or oxide is selectively formed on the second semiconductor region 26 to perform selective oxidation (local oxidation). conduct. As a result, a portion of the semiconductor regions 12 and 26 is converted into an insulator, and a partially buried field insulator 13 is formed. The step of forming this field insulator is, for example, Japanese Patent Application No. 45-88430 (Japanese Patent Publication No. 55-20381) or Japanese Patent Application No. 45-113252 (Japanese Patent Publication No. 51-36989) filed by the present inventor. Details are given in the official gazette).

Furthermore, the extraction layer 14 in contact with the recessed layer 11 was formed by selective diffusion. Of course, the buried insulator may also be selectively provided at the boundary between the lead layer 14 and the semiconductor regions 12 and 26 surrounded by the buried insulator 13.
A process for making the upper layer of the field insulator 13 and the upper layer of the second semiconductor region 26 substantially on the same plane may be performed as necessary. Through the above steps, the first
The structure shown in Figure A was obtained.

Furthermore, a P ⁺ semiconductor region 2 is formed in a part of the second semiconductor region 26 by the fourth photorinography.
4 and 24' are provided, and the bottom surfaces of these semiconductor regions 24 and 24' are brought into close contact with the semiconductor region 12. Thus, the second semiconductor region 26 includes at least two (in this case three) semiconductor regions 17, 26, 2
The structure is such that it is electrically isolated from 6'. In drawing B, the second semiconductor region 26,2
6' constitutes a region that functions as a collector of a transistor that operates as an ITR. Of course, the recessed layer 11 acts on the emitter region (hereinafter referred to as emitter) of this transistor. In addition, another region of the second semiconductor region 26, that is, the region 17 having substantially the same impurity concentration and the same conductivity type, can be operated as the base of the NTR. Of course, the first semiconductor region 12 acts as the collector of this NTR.

Furthermore, in ^FIG .
The emitter 19 was formed by forming a semiconductor region with an impurity concentration of 10 ¹⁷ to ^{10 20} cm ^-3 . In addition, an N ⁺
Create a fourth area of the mold and call it collector 1 of the ITR
It was set to 6,16'. Finally these areas 19,2
Electrodes/leads 20, 20', 22, 21 made of aluminum or the like were formed to make ohmic contact with 4, 16, 24', 16' and the lead-out layer 14, thereby obtaining the structure shown in FIG. 2C.

As is clear from the above manufacturing process, the present invention
NPN type ITR is provided at emitter 11, base 12, collector 26, 26', 16, 16', and PNP type NTR is installed at emitter 19 and base 17.
By providing the collector 12 and the collector 12, the circuit shown in FIG. 1 can be realized in an extremely small area by using various semiconductor regions in combination. In particular, by adding an NTR structure to the PNP transistor instead of a lateral type, which had previously been considered impossible, and forming the base with a low impurity concentration, the frequency response speed of this transistor is extremely high. A very important feature is that it has a structure that is easy to manufacture. Further, in the present invention, by providing second semiconductor regions 26 and 26' with low impurity concentration on the base 12 of the NPN transistor, parasitic capacitance can be reduced and high frequency operation can be achieved. As is clear from FIG. 2C, the input terminals 23 and 23'
4 and 24', and a reduction in contact resistance is required. At the same time, the semiconductor region 17 and the extraction layer 1
Although the terminals 7 and 8 in FIG. 1A are connected to each other by bringing the interface 30 with 4 into close contact with each other, this structure may be separated by embedding a field insulator at this boundary; Any method suitable for design may be used. This point is one of the most significant advantages, considering that in conventional IIL structures, such as Japanese Patent Publication No. 49-35030, the lateral transistor system has no such degree of freedom.

By having the structure of the present invention as described above,
The base of a PNP transistor is a lateral PNP
The thickness of the base 17 is 1/10 compared to the transistor.
It has become possible to reduce the thickness to 0.01 to 1μ, which is 0 to 1/3. In addition, the area of the base 17 and the emitter 19 can be uniquely determined by photorinography, which provides a greater degree of freedom in design than in the past. Therefore, it is possible to improve the current capacity and frequency response speed of NTR used as a constant current region, and the base grounding amplification factor α (alpha) is lower than the previous 0.4.
It became possible to increase it to 0.9-0.99.

Furthermore, as is clear from the drawing, this PNP type
The NTR collector 12 has a buried layer 1 on its bottom surface.
Since the input terminals 24 and 2 are in contact with 1 in a large area,
The input signal from 4' makes it possible to easily drain the current to ground. Additionally, in this embodiment, semiconductor regions 26, 26', 1
Since 7 is made by separating the same semiconductor layer from each other by 24 and 24', the types of photolithography patterns required to form this structure are 6 to 7.
It can be seen that it has an extremely simple structure, considering that only seven pieces are required, whereas conventionally eight to nine pieces were required.

In Figure 2C, the base 12 of the NPN type ITR
The upper collector 26, 16 or 26', 16' has a lightly doped semiconductor region 26, 26' which helps eliminate parasitic capacitance between the collector and the base, especially when used as an ITR. This made it possible to respond to high frequencies.

When a ring oscillator was made using the structure shown in Fig. 2C and the propagation delay time per gate was investigated, it was found to be 0.3 to 3 nS. Also, the power delay time is
We were able to obtain 0.1 to 0.01 PJ, and in all cases, we were able to obtain performance that is 10 to 1000 times higher than that of conventional IILs, even though the structure has become simpler. The integration degree of this structure was 500 inverters/mm ² in the prototype, but with advances in peripheral technology, it will become possible to increase the integration density to 1000 to 3000 inverters/mm 2 .

FIG. 3 is a modification of the structure of FIG. 2C. That is, the structure shown in Figure 3A is NPN
The collector 26 on the base 12 of a transistor of type
A plurality of Schottky diodes 33, 33' in this case, two in this case, are provided, which is the so-called collector 26 electrode provided with a Schottky type electrode. This equivalent circuit is 10,1 in Figure 1B.
0' corresponds. At the same time, this shotgun type electrode 3
3 is also provided over the upper surface of the field insulator 13 in an effort to improve manufacturing yield when forming electrode holes. In FIG. 3A, a semiconductor region 1 of a different conductivity type above a semiconductor region 12
Points 7 and 26 have a relatively high impurity concentration compared to point 12, and points 17 and 26 are selectively formed by ion implantation to simplify the manufacturing process.

In FIG. 3B, shotgun type collectors 33 and 33' are provided for the NPN type transistor, but at the same time, for the PNP type NTR, the emitter is located above the semiconductor region 17 as shown in FIG. 2C.
Rather than fabricating the P ⁺ layer by diffusion or implantation, polycrystalline silicon 19 mixed with P ⁺ type impurities was provided using a vapor phase method, and this structure enabled even finer processing. Figure 1C
One example of this is the structure that spans the emitter of a PNP transistor.

FIG. 3C shows a structure corresponding to FIG. 1C. That is, the eleven collectors 26 of the NPN transistors are provided with a Schottky type electrode 33, and equivalently correspond to the transistor 3 and the Schottky type diode 10 in FIG. 1C. However, although the collector 26' in FIG. 3C is provided with a shotgun type electrode 33', this electrode 33' is provided over the upper surface of the adjacent P ⁺ type semiconductor layer 24'. Since 24' constitutes a part of the base, it constitutes a shotgun transistor having a so-called shotgun type collector. Of course, this shotgun type transistor structure may also be fabricated as shown in FIGS. 3B and 3A. At the same time, metal emitters 19, 19' corresponding to P ⁺ are provided on the bases 17, 17' of the PNP type transistors in C, promoting the function as a constant current source. In either case, the emitter base collector has an MNP structure.

In the embodiments of the present invention, the transistor that operates as an ITR is an NPN transistor, and the transistor that operates as an NTR is an NPN transistor.
It was a PNP type transistor. However, of course, the former may be of the PNP type and the latter may be of the NPN type. They are the same technical concept as long as they have complementary structures of the present invention.

As is clear from the above, the present invention not only improves the characteristics of the conventionally known IIL to create a more practical structure, but also a more advanced concept.
Practical structures for complementary combinations of PNP and NPN transistors are shown; they simply
In addition to the one-to-one combination of transistors, it is also possible to monolithically integrate a plurality of transistors on the same substrate in the same area or in different areas according to the practical circuit configuration. It is judged to be extremely important for the development of microelectronics.

[Brief explanation of the drawing]

FIG. 1 is an example of a basic circuit configuration for showing the structure of the present invention. FIG. 2 shows a manufacturing process for carrying out the structure of the present invention, and FIG. 3 shows another embodiment of the present invention.

Claims (1)

[Scope of Claims] 1. A buried layer of one conductivity type with high impurity concentration is formed on a semiconductor substrate, a first semiconductor region of a conductivity type opposite to that of the buried layer is provided on the buried layer, and a first semiconductor region of a conductivity type opposite to that of the buried layer is provided on the buried layer. By forming at least two low impurity concentration second semiconductor regions having the same conductivity type as the recessed layer on the first semiconductor region, the recessed layer is used as an emitter and the first semiconductor region is used as a base. One of the second semiconductor regions constitutes a reverse transistor that acts as a collector, and the other one of the second semiconductor regions has a third semiconductor region or metal of a conductivity type opposite to that of the second semiconductor region. 1. A semiconductor device comprising: a forward-direction transistor including a layer formed on the other one of the second semiconductor regions as a base and the third semiconductor region or the metal layer as an emitter. 2. The semiconductor device according to claim 1, wherein the second semiconductor region functioning as a collector is provided with a shotgun type electrode.