JPH06104459A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form a monolithic IC so that a parasitic transistor does not occur when forming a diode in a PN junction separating region. CONSTITUTION:An insular region of a PN junction separation surrounded by a P-type semiconductor substrate 11, a P-type region 14 and a P<+>-type region is formed. An N-type cathode region comprising an N<++>-type region 23 and an N<->-type region 16 is formed in the insular region. A P-type anode region comprising a P-type region 15 and a P<+>-type region 20 is formed so as to surround the cathode region. An N<+>-type region 13 and an N<+>-type region 18 are formed so as to surround the anode region. A cathode electrode 36 is connected to the N<++>-type region 23. An anode electrode 35 is connected to the P<+>-type region 20 and the N<+>-type region 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a PN junction diode is formed by suppressing the operation of a parasitic transistor in a region separated from a PN junction.

[0002]

2. Description of the Related Art A PN junction separation method is known as a means for separating elements of an integrated circuit. FIG. 11 shows a monolithic IC chip using this PN junction separation. Here, a semiconductor substrate including a P-type semiconductor region 1 as a starting base material and an N ⁻ -type semiconductor region 2 formed by epitaxial growth on the P-type semiconductor region 1 is provided, and the N ⁻ -type semiconductor region 2 serving as an element forming region is a P-type semiconductor region. It is divided into a large number of regions by the diffusion separation region 3. In FIG. 11, the N ^{+ type} region 4 is the emitter, the P type region 5 is the base,
An NPN transistor structure is constructed with the ^{+ type} region 6 and the N ^{− type} region 2 as collectors. Where N ^{+ type} region 6
Are adjacent to electrode 7, and N ^{+ type} region 4 and P type region 5 are adjacent to common electrode 8. As a result, the NPN transistor of FIG. 11 operates as a collector-base PN junction diode with a shorted base-emitter.

[0003]

By the way, in the device structure shown in FIG. 11, the P-type semiconductor region 5 is used as an emitter and N ⁺
A PNP transistor structure is formed parasitically in the vertical and horizontal directions of the device, with the P-type region 6, the N ⁻ -type region 2 as the base, and the P ^{+ -type} region 3 and the P-type region 1 as the collector. Therefore, when a voltage that increases the potential on the electrode 8 side is applied between the electrodes 8 and 7 to operate the PN junction diode in the forward direction, hfe of the parasitic PNP transistor is 0.1
The transistor operates as described above, and a collector current flows through the electrode 9 and becomes a leak current. This leakage current causes a large power loss when the potential difference between the electrode 9 and the electrodes 7 and 8 is large, which is a problem.

Therefore, an object of the present invention is to provide a PN junction diode structure in which such a parasitic transistor is not formed.

[0005]

The present invention for achieving the above object will be described with reference to the reference numerals of FIG. 10 which shows an embodiment. First semiconductor regions 11, 14 of the first conductivity type,
Second semiconductor regions 16 and 23 of the second conductivity type, one main surface of which is exposed at the upper surface of the substrate, in the element formation region separated by the island-shaped PN junction by 19, and the second semiconductor region 1
The third semiconductor regions 15 and 20 of the first conductivity type, which have a portion that surrounds 6 and 23 excluding one main surface thereof and that is exposed to the upper surface of the substrate, and the third semiconductor regions 15 and 20 are The fourth semiconductor regions 13 and 18 of the second conductivity type having a portion which is surrounded except the one main surface and is exposed to the upper surface of the substrate.
And a first electrode 36, which is connected to one main surface of the second semiconductor regions 16 and 23, and one main surface of the third and fourth semiconductor regions 15, 20, 13, and 18. And a second electrode 35 connected to the semiconductor device. The correspondence between the present invention and the embodiment will be described. The first semiconductor region is a P-type semiconductor substrate 11
, P-type region 14 and P ^{+ -type} region 19, the second semiconductor region is N ⁻ -type region 16 and N ⁺⁺ -type region 23, and the third semiconductor region is P-type region 15 and P ^{+ -type} region. 20, the fourth semiconductor region is the N ^{+ -type} region 13 and the N ^{+ -type} region 18, the first electrode is the cathode electrode 36, and the second electrode is the anode electrode 35.

[0006]

According to the present invention, a PN junction is formed between the second semiconductor region 23 and the third semiconductor regions 15 and 20, and both semiconductor regions form a PN junction diode. Here, the third semiconductor regions 15 and 20 are connected to the third semiconductor regions 15 and 20 and are connected to the second electrode 35.
Is surrounded by the semiconductor regions 13 and 18. For this reason,
Second semiconductor region 23 or third semiconductor region 15, 20
The leakage current is suppressed from flowing between the first semiconductor region 11, 14, and 19. That is, the leakage current due to the parasitic transistor can be prevented even though the diode is formed in the region where the PN junction is separated.

[0007]

1 to 10, a monolithic IC according to an embodiment of the present invention and a manufacturing process thereof will be described. When manufacturing the monolithic IC of this embodiment, first, the P-type semiconductor substrate 11 made of silicon shown in FIG. 1 is prepared as a starting base material. The substrate 11 has a region 11a in which a transistor element will be formed later (hereinafter referred to as a first element forming region) 11a and a region 11b in which a diode element will be formed later (hereinafter referred to as a second element forming region) 11b. ing. In an actual monolithic IC, these virtual areas 11
Although a and 11b have a structure in which a plurality of a and 11b are spaced apart from each other in a plane and are arranged in an island shape, only the region related to the essence of the present invention is shown and described in this embodiment.

Next, N type impurities are introduced into the substrate 11 of FIG. 1 from one main surface thereof to form N ^{+ type} regions 12 and 13 in the regions 11a and 11b, respectively. Area 1
When forming 2 and 13, an oxide film is formed on one main surface of the base 11, but the illustration is omitted in this embodiment. Similarly, in the following steps, the oxide film is not shown.

Next, as shown in FIG. 3, P-type impurities are introduced from one main surface of the substrate 11 so that P is introduced between the adjacent element forming regions 11a and 11b and the N ^{+ -type} region 13, respectively.
The shaped regions 14 and 15 are selectively formed. Since the N ^{+ type} region 13 has a high impurity concentration, the region 15 in which the P type impurity is selectively diffused is actually the N type region or N ^−.
Although it can be considered that it can be called a shape region, in this embodiment, it is a P-shaped region for convenience of explanation.

Next, as shown in FIG.
^The -shaped region 16 is formed by epitaxial growth. This N
^{When the} -shaped region 16 is formed, two N ⁺ -shaped regions 12 and 13 and two P-shaped regions 14 and 15 are formed as shown in FIG.
Impurities diffuse into the N ⁻ -type region 16 side, and these regions expand.

Next, as shown in FIG. 5, N-type impurities are selectively introduced from one main surface of the semiconductor substrate after the epitaxial layer is formed, and N ^{+ -type} regions 12 and N ^{+ -type} regions 13 are continuously formed. N ^{+ type} regions 17 and 18 are formed. The N ^{+ type} region 18 is formed in a plane annular shape so as to surround the N ^{− type} region 16.

Next, as shown in FIG. 6, P-type impurities are selectively introduced from one main surface of the substrate to form a P-type region 14.
To form a P ^{+ -type} region 19 and a P ^{+ -type} region 20 continuous to the P-type region 15. The P-type region 14 and the P ^{+ -type} region 19 are located between two adjacent element forming regions 11a and 11b and function as regions for separating the two regions by PN junction, and are continuous with the P-type region 11. The first and second element forming regions 11a and 11b are separated from each other in an island shape.

Next, a P-type impurity is selectively introduced into the N ^--type region 16 of the first element forming region 11a to form a P-type region 21 as shown in FIG.

Next, as shown in FIG. 7, N is formed on one main surface of the substrate.
Type impurity is introduced to form an N ^{++ type} region 22 in the P type region 21 of the first element forming region 11a as shown in FIG. In addition, the N ⁻ -type region 16 of the second element formation region 11b
An N ^{+ + type} region 23 is formed at

Next, as shown in FIG. 9, an insulating film 24 made of a silicon oxide film formed in the above diffusion process.
Six openings 25 to 31 are formed in the. The N ^{+ -type} region 22, the P ^{+ -type} region 21, and the N ^{+ -type} region 17 are exposed from the three openings 25, 26, and 27 provided in the first element formation region 11a, respectively. In addition, the second element formation region 11b
The N ^{+ -type} region 18, the P ^{+ -type} region 20, and the N ⁺⁺ -type region 23 are exposed from the three openings 28, 29, and 30 provided in, respectively. Further, the P ^{+ -type} region 19 is exposed from the opening 31 provided between the two regions 11a and 11b.

Next, aluminum is vacuum-deposited on the entire upper surface of the substrate and then etched into a desired pattern to form six electrodes 32, 33, which are electrically separated from each other, as shown in FIG. 34, 35, 36, 37
To form. By the above, a monolithic IC chip is completed.

In the monolithic IC chip shown in FIG. 10, the N ^{+ type} region 1 is formed in the first element forming region 11a.
2, 17 and an NPN transistor having the N ^{− type} region 16 as a collector region, the P type region 21 as a base region, and the N ^{++ type} region 22 as an emitter region are formed, and three electrodes 3 are formed.
2, 33 and 34 are an emitter electrode, a base electrode,
Functions as a collector electrode. The structure and operation of this NPN transistor are no different from those of the transistor formed in the conventional monolithic IC. Second element formation region 11
In b, N ^{+ type} regions 18, 13 and N ^{− type} region 1
6 as a collector region, P ^{+ type} region 20 and P type region 1
5 as a base region, N ^{++ type} region 23 and N ^{− type} region 1
An NPN transistor having 6 as an emitter region is constructed. Here, the NPN transistor has its base and collector electrically short-circuited by the electrode 35, and consequently operates as a PN junction diode having the base region and the emitter region as the anode region and the cathode region, respectively. Therefore, the electrodes 35 and 36 can be called an anode electrode and a cathode electrode, respectively.

According to the element structure of this embodiment, the parasitic PNP transistor as described in the prior art is not formed between the second element forming region 11b and the diffusion-isolated P + type region 19. That is, according to the structure of this embodiment, the P + type region 20 and the P type region 1 which become the emitters of the parasitic transistors are formed.
5 and an N + type region 1 which is a base that surrounds the island 5
3 and 18 are connected to the same electrode 35,
The base is electrically short-circuited. Therefore, carriers do not move between the P + type region 20 and P type region 15 and the diffusion isolation region and further between the substrate 11 and the parasitic transistor, and the operation of the parasitic transistor is completely prevented. As a result, a voltage that raises the potential on the side of the anode electrode 35 is applied between the anode electrode 35 and the cathode electrode 36, and the PN junction diode in the second element formation region 11b is operated to cause a current to flow from the electrodes 35 to 36. When a current is passed through, part of the current does not flow into the electrode 37. Therefore, even when a large potential difference occurs between the electrode 37 and the electrodes 35 and 36 during conduction of the PN junction diode in the region 11b, the power loss can be significantly reduced as compared with the conventional example.

The advantages of the monolithic IC chip structure of this embodiment are summarized as follows. (1) Since the emitter and base of the parasitic PNP transistor are short-circuited, the parasitic transistor does not substantially operate even when a forward current is passed through the diode. Therefore, the leakage current to the ground is significantly smaller than that of the conventional structure, and the power loss is sufficiently reduced. (2) The diode of this structure is an emitter-base PN junction diode in which the collector-base of the NPN transistor is short-circuited. For this reason, the total amount of accumulated charges when conducting is small and the junction capacitance is small, which is superior to the conventional structure in switching characteristics. (3) It can be manufactured without adding a process to the conventional manufacturing process. (4) The impurity concentration of the N ^{− type} region 16 and the P ^{+ type} region 19, the impurity concentration of the diffusion region forming the transistor, the diffusion depth, etc. are determined by the required characteristics of other elements incorporated in the monolithic IC. In the conventional structure, it was difficult to improve the breakdown voltage between the anode and the ground.
In this structure, the breakdown voltage between the anode and the ground can be controlled by slightly changing the diffusion depth of the N ^{+ type} region 13. In this case, other element characteristics are hardly changed.

[0020]

MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible. (1) Electrodes are individually formed in the P ^{+ -type} region 20 as the third semiconductor region and the N + -type region 18 as the fourth semiconductor region, and these are externally connected to have substantially the same potential. You may (2) between the N ⁺ form region 18 and the P ⁺ region 20 N ^-
The electrode 35 may also be in contact with the shaped region 16. However, in that the forward voltage of the diode does not increase, it is desirable to leave the oxide film 24 on the N ^{− type} region 16 as in the embodiment. (3) In FIG. 10, it can be formed so that an N ^{− type} region surrounding the N ^{+ type} region 23 does not occur. Also, N ⁺
It may be formed such that the N ^- shaped regions 16 on one or both sides of the shaped region 18 do not occur.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor substrate used for manufacturing an IC according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a state in which an N + type region is formed on the base body of FIG.

3 is a cross-sectional view showing a state where a P-type region is formed on the base body of FIG.

4 is a cross-sectional view showing a semiconductor substrate in which an epitaxial layer is formed on the substrate of FIG.

5 is a cross-sectional view showing a state where an N ^{+ type} region is formed on the semiconductor substrate of FIG.

6 is a cross-sectional view showing a state where a P ^{+ type} region is formed on the semiconductor substrate of FIG.

7 is a cross-sectional view showing a state where a P-type region is formed on the semiconductor substrate of FIG.

FIG. 8 is a cross-sectional view showing a state where an N ^{+ type} region is formed on the semiconductor substrate of FIG.

FIG. 9 is a cross-sectional view showing a state in which an opening is formed in an oxide film.

FIG. 10 is a cross-sectional view showing a state in which electrodes are formed.

FIG. 11 is a sectional view showing a part of a conventional IC.

[Explanation of symbols]

20 P ^{+ type} region 23 N ^{+ type} region 35 Anode electrode 36 Cathode electrode

Claims (1)

[Claims] 1. A first semiconductor region (1) of a first conductivity type.
1) Second semiconductor regions (16) (23) of the second conductivity type, one main surface of which is exposed on the upper surface of the substrate, in the element formation region separated by island-shaped PN junctions by (14) (19). When,
A third semiconductor region (15) (20) of the first conductivity type which has a portion which surrounds the second semiconductor region (16) (23) except for one main surface thereof and is exposed to the upper surface of the substrate; ,
A fourth semiconductor region (13) (18) of the second conductivity type which has a portion which surrounds the third semiconductor region (15) (20) except for one main surface thereof and which is exposed on the upper surface of the substrate; A first electrode (36) connected to one main surface of the second semiconductor region (16) (23), and the third and fourth semiconductor regions (15) (20) (13). And a second electrode (35) connected to one main surface of the semiconductor device (18).