WO1995019647A1 - Diode and production method thereof - Google Patents

Diode and production method thereof Download PDF

Info

Publication number
WO1995019647A1
WO1995019647A1 PCT/KR1995/000003 KR9500003W WO9519647A1 WO 1995019647 A1 WO1995019647 A1 WO 1995019647A1 KR 9500003 W KR9500003 W KR 9500003W WO 9519647 A1 WO9519647 A1 WO 9519647A1
Authority
WO
WIPO (PCT)
Prior art keywords
type
conductivity
conductivity type
semiconductor substrate
layer
Prior art date
Application number
PCT/KR1995/000003
Other languages
French (fr)
Japanese (ja)
Inventor
Kyung Hwa Cho
Jin Sook Choi
Original Assignee
Daewoo Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Daewoo Corporation filed Critical Daewoo Corporation
Publication of WO1995019647A1 publication Critical patent/WO1995019647A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions

Definitions

  • the present invention relates to a die for a non-contact relay device and a method of manufacturing the same, and particularly, when a switch is turned off, a semiconductor substrate is opened to electrically separate the devices.
  • the present invention relates to a die for a non-contact relay element capable of preventing a latch-up generated due to a power supply voltage, and a method of manufacturing the same.
  • Figure 1 is a sectional view of a conventional diode.
  • the diode has a p-type layer 17 formed at a predetermined portion of an n-type epitaxial layer 15 crystal-grown on a p-type semiconductor substrate 11.
  • an ⁇ + -type buried layer 13 is formed between the P-type semiconductor substrate 11 and the ⁇ -type epitaxial layer 15, to prevent the generation of parasitic transistors, and the ⁇ -type ⁇ -type E-bi 7 toward evening Kusharu layer 1 5 of the predetermined portion to the connecting diode from the proximal of the isolation region 1-9 [rho + -type element for partial flame is a substrate 1 1 of ⁇ -type semiconductor It is formed to be. Further, electrodes 25 and 27 are formed on the surface of the ⁇ -type metal 17 and the ⁇ -type well 21, and an oxide film 23 is formed on the remaining part.
  • the diode performs a rectifying action by the forward connection between the ⁇ -type well 17 and the ⁇ -meter ⁇ 21, but when the ⁇ -type semiconductor substrate 11 is grounded, the ⁇ -type The elements are electrically separated by the element isolation region 19.
  • this diode when the switch is turned off, the substrate 11 of the ⁇ -type semiconductor is floated to the potential of the power supply voltage and electrically isolated. Not done. Therefore, the die had a ⁇ ⁇ ⁇ ⁇ thyristor structure, and had a problem of causing a latch-up and destroying the element.
  • an object of the present invention is to prevent a device from being damaged by a latch-up when a switch is turned off and a semiconductor substrate is formed even when a semiconductor substrate is floated.
  • Another object of the present invention is to provide a method for manufacturing a die for a contactless relay as described above.
  • Figure 1 is a cross-sectional view of a conventional die die.
  • FIG. 2 is a sectional view of a diode according to the present invention.
  • FIG. 3 is a process chart for manufacturing a diode according to the present invention.
  • FIG. 2 is a sectional view of a contactless relay diode according to an embodiment of the present invention.
  • This diode is located on the ⁇ -type epitaxial layer 35 grown on the p-type semiconductor substrate 31.
  • a P-type layer 37 is formed in a predetermined portion, and an n-type layer 43 is formed in the p-type layer 37, forming a pn junction with the p-type layer 37.
  • the n-type epitaxial layer 35 is doped with n-type impurities such as sapphire (p), antimony (Sb), or arsenic (As) to have a thickness of about 1D to 15 ⁇ m. The crystal grows.
  • the depth of the P-type ⁇ I le 3 Ryo is p-type impurity Boron (Boron) et al 3. 5 x 1 0 '4 ⁇ 5.
  • O xl O' 4 Zcm 2 -position 6 ⁇ 8 ⁇ ⁇ position is injected into, the ⁇ -type ⁇ Weru 4 3 are formed by diffusion until ⁇ -type impurity is 1 X 1 0 14 ⁇ 5 x 1 0 '4 / cm 2 of force ⁇ 1 ⁇ 5 ⁇ 2 ⁇ m-position of the depth .
  • ⁇ -type impurities are doped so that the sheet resistance becomes 10 to 25 ⁇ ⁇ over the p-type semiconductor substrate 31 and the n-type epitaxial layer 35.
  • a ⁇ + type buried layer 33 having a thickness of about 3 to 4 ⁇ m is formed as shown in FIG. Also, is Kenkan only ⁇ type ⁇ El 3 Ryo a predetermined distance, impurities in ⁇ -type E peak evening Kusha Le layer 35 around 1 X 1 0 of '8 ⁇ 5 X 1 0 2 ' / cm 3
  • a diffused ⁇ + type sink (Sink) 41 is formed. The ⁇ + -type sink 41 is connected to the n + -type buried layer 33, and electrically separates the p-type semiconductor substrate 31 from the p-type semiconductor 37.
  • the n-type epitaxial layer 35 near the ⁇ + -type sink 41 has p-type impurities in a concentration of 1 ⁇ 10 2 ° to 1 ⁇ 10 2 ′ / OT 3 in a P + -type element layer.
  • the layer 39 is formed so as to be connected to the p-type semiconductor substrate 31.
  • Electrodes 51 and 53 made of a conductive metal such as aluminum (AI) are formed on predetermined portions of the surface of the p-type and n-type wells 37 and 43 such as the above-described p-type and n-type wells. Thus, an oxide film 45 is formed.
  • P + -type and n + -type regions 47, 49 are formed at predetermined portions of the ⁇ -type and ⁇ -type wells 37, 43 which are in contact with the electrodes 51, 53.
  • P-type and n-type ⁇ 3 The connection resistance between the electrodes 37, 43 and the respective electrodes 51, 53 is reduced.
  • the switch When the switch is turned on, the p-type semiconductor substrate 31 is grounded, and the p-type semiconductor 37 and the n-type semiconductor 43 have the same direction as the above. Is applied to perform rectification. At this time, the P-type semiconductor substrate 31 and the p + element isolation region 45 are grounded, and the diode is exposed from a nearby element or the like. However, when the switch is “off”, the p-type semiconductor 37 and the n-type semiconductor 43 are grounded, and the p-type semiconductor substrate 31 is in a floating state. Therefore, the voltage of the p-type semiconductor substrate 31 rises to the potential of the power supply voltage, and the diode forms a pnpn thyristor structure together with the p-type semiconductor substrate 31. By being electrically separated from the p-type semiconductor substrate 31 by 33 and the sink 41, it is possible to prevent a latch-up from occurring.
  • FIGS. 3 (A) to 3 (C) are manufacturing process diagrams of a die for contactless relay according to an embodiment of the present invention.
  • a predetermined portion of a p-type semiconductor substrate 31 as a starting material is doped with n-type impurities such as arsenic or antimony, and has a sheet resistance of 10 to 2.
  • An n + type buried layer 33 of about 5 ⁇ is formed to a thickness of about 3 to 4 m.
  • an ⁇ -type epitaxial layer 35 having a non-resistance of about 3 to 5 ⁇ ⁇ cm , for example, It is grown to a thickness of about 10 to 15 ym by a normal crystal growth method such as the chemical vapor deposition (CVD) method. Thereafter, an oxide film 36 is formed on the upper surface of the ⁇ -type epitaxial layer 35, and the ⁇ of the portion corresponding to the middle of the ⁇ + -type buried layer 33 is formed by photolithography. The exposing layer 35 is exposed.
  • ⁇ -type epitaxial layer 35 was implanted into the exposed portion of the ⁇ -type epitaxial layer 35 at a dose of 3.5 ⁇ 10 14 to 5.0 ⁇ 10 14 / cm 2 and 60 to 100 ⁇ . Ion implantation with keV energy is performed, and heat treatment is performed for 60 to 80 minutes in a water vapor state of 100 to diffuse impurities. P-type with a depth of 6 to 8 ⁇ m: ⁇ : To form 37. At this time, an oxide film is formed on the exposed portions of the n-type epitaxial layer 35 during the heat treatment. During ion implantation, a buffer oxide film with a thickness of about 500 to 150 A was formed on the exposed portion of the n-type epitaxial layer 35 to prevent surface damage due to high energy. Later, ion implantation can also be performed.
  • Figure 3 (B) shows that the oxide film grown during heat treatment passes
  • the surroundings of the n + -type buried layer 33 and the corresponding portion of the oxide film 36 are removed by a usual photolithography method, and the n-type epitaxial layer 35 is exposed.
  • the p-type impurities such as pol- lones are deposited on the exposed portions, they are brought into contact with the p-type semiconductor substrate 31 in a water vapor state of about 100 ° C to reach 60 to 80 ° C.
  • n + type sink 4 1 that is cm 3 .
  • the ⁇ + type sink 41 together with the n + type buried layer 33, completely electrically connects the p type ⁇ : i: 37 and the p type semiconductor substrate 31.
  • the p + -type element isolation region 39 and the n + -type sink 41 were formed, respectively, and after the p-type impurity and the n-type impurity were respectively deposited, they were formed simultaneously by drive-in. You can also.
  • FIG. 3 (C) shows that the p-type: I: oxidation on a predetermined portion of Preventing film 3 6, to ion-implanted at 4 0 to 6 0 e in E Nerugi first and 1 x 1 0 injection amount of '4 ⁇ 5 x 1 0' 4 / cm 2 to ⁇ -type impurity such as ⁇ . Further, the implanted impurities are subjected to heat treatment for 115 to 25 minutes in a steam state of 115 to 125 ° C. for 15 to 25 minutes, and for 20 to 40 minutes in a green state at the same temperature. It diffuses to a depth of 5 to 2 ⁇ to form ⁇ -type 1 43. Thereafter, the oxide film 36 is removed.
  • an oxide film 45 is formed again on the entire surface of the above structure. Also, the oxide film 45 on the ⁇ -type well 37 is selectively etched, and the ⁇ -type impurities of Polon et al. Are mixed with the energy of 40 to 60 keV and 5 ⁇ 10 ' 4 to 8 to enter the ion Note in implantation of x 1 0 '4 Zcm. After that, it is heat-treated for 70 to 110 minutes in a room temperature of 110 to 120 ° C and for 40 to 60 minutes in a steam state of 950 to 115 ° C. Then, the implanted impurities are diffused to form p + -type regions 47.
  • the p + -type region 47 described above is for preventing a leakage current of the diode, and the impurity on the surface of the p-type well 37 and the diffused impurity are combined to have a high concentration. At this time, an oxide film is formed on the p-type well 37 during the heat treatment.
  • the oxide film 4 5 on the n-type ⁇ El 4 3 was deposited 1 5-2 5 minutes P0C1 3 at 9 5 0 ⁇ 1 1 5 0 ° C, 9 5 0 ⁇ 1 Heat treatment is carried out for 15 to 25 minutes at the same temperature in the water vapor state at 150 ° C for 20 to 40 minutes, and the heat is diffused to form n + type regions 49, which ⁇ The + type region 49 forms an ohmic contact.
  • the impurity on the surface of the n-type well 43 and the diffused impurity are combined to have a high concentration.
  • electrodes 51 and 53 are formed on the exposed surfaces of the P + type and n + type regions 47 and 49 with a conductive metal such as aluminum.
  • the present invention prevents the latch-up from occurring by preventing the p-type semiconductor substrate and the p-type well from being electrically separated by the n + -type buried layer and the sink, thereby preventing diode breakdown.
  • a p-type semiconductor substrate is used as a starting material, but an n-type semiconductor substrate may be used.
  • each region and the like have opposite conductivity.

Abstract

A diode including an n+ buried layer for preventing the formation of a parasitic transistor at a predetermined portion of an n epitaxial layer grown on a p semiconductor substrate, and a p+ element isolation region formed on an n epitaxial layer close to the n+ buried layer and connected to the semiconductor substrate. The diode has a diode structure formed in the n epitaxial layer on the n+ buried layer, in which the junction of a p well and an n well is formed. An n+ sink formed in the n epitaxial layer close to the p well and connected to the n+ buried layer isolates electrically completely the p semiconductor substrate from the p well. Thus the n+ buried layer and the sink isolate electrically the p semiconductor substrate from the p well, latch-up is prevented, and breakdown of the diode is prevented.

Description

明 細 書  Specification
ダイ才ー ドおよびその製法  Die seed and its manufacturing method
[発明の分野] .  [Field of the Invention]
本発明は無接点リ レー素子用ダイ才ー ドおよびその製法に 関し、 と く に、 スィ ッチ 「オフ」 の際、 半導体の基板がフ口 一ティ ングされて素子が電気的に分離されなく、 電源電圧の 電位になるため発生されるラ ッチアップを防止しうる無接点 リ レ一素子用ダイ才ー ドおよびその製法に関する。  The present invention relates to a die for a non-contact relay device and a method of manufacturing the same, and particularly, when a switch is turned off, a semiconductor substrate is opened to electrically separate the devices. The present invention relates to a die for a non-contact relay element capable of preventing a latch-up generated due to a power supply voltage, and a method of manufacturing the same.
[従来の技術]  [Prior art]
最近、 回路の設計および半導体の製造工程技術の向上によ つて個別素子などからなる回路などを集積回路化するために 多く の研究が行われておリ、 実際に多く の回路などが集積回 路化されている。 かかる個別素子などからなる回路などを集 積回路化することによって寿命延長、 小型軽量化、 動作特性 向上および原価節減などの特長がある。  In recent years, much research has been conducted on the integration of circuits composed of individual elements, etc., due to improvements in circuit design and semiconductor manufacturing process technology, and many circuits, etc., have actually been integrated circuits. Has been By integrating such individual circuits and other circuits into integrated circuits, there are features such as longer life, smaller size and lighter weight, improved operating characteristics, and reduced cost.
かかる傾向に応じて、 ダイ才ー ドを整流器で用いる無接点 リ レー素子を集積回路で製造するための研究が続けられてい In response to this trend, research has been continued to manufacture a non-contact relay element using a die diode as a rectifier in an integrated circuit.
-© o -© o
図 1 は従来のダイオー ドの断面図である。  Figure 1 is a sectional view of a conventional diode.
前記ダイオー ドは p型半導体の基板 1 1 に結晶成長された n型のェピ夕ク シャル層 1 5の所定の部分に p型のゥ Iル 1 7が形成されて、 この p型ゥ ヱル 1 7内に π型ゥ： I：ル 2 1 が 形成されて P型ゥ ： ル 1 7 と p n接合をなしている。 また、 P型半導体の基板 1 1 と π型ェピ夕ク シャル層 1 5 とのあい だに寄生 トラジス夕の生成を防ぐための η + 型埋設層 1 3が 形成されており、 ρ型ゥ エル 1 7寄りの π型ェビ夕クシャル 層 1 5の所定の部分に前記ダイオー ドを近位の素子から分難 するための Ρ + 型素子の分離領域 1 9が ρ型半導体の基板 1 1 と連結されるように形成されている。 また、 ρ型ゥ Xル 1 7 と η型ゥ エル 2 1 との表面に電極 2 5 , 2 7が形成されて おり、 残りの部分に酸化膜 2 3が形成されている。 The diode has a p-type layer 17 formed at a predetermined portion of an n-type epitaxial layer 15 crystal-grown on a p-type semiconductor substrate 11. A π-type ゥ: I: le 21 is formed in 17 and a P-type ゥ: le 17 forms a pn junction. Also, Between the P-type semiconductor substrate 11 and the π-type epitaxial layer 15, an η + -type buried layer 13 is formed to prevent the generation of parasitic transistors, and the ρ-type π-type E-bi 7 toward evening Kusharu layer 1 5 of the predetermined portion to the connecting diode from the proximal of the isolation region 1-9 [rho + -type element for partial flame is a substrate 1 1 of ρ-type semiconductor It is formed to be. Further, electrodes 25 and 27 are formed on the surface of the ρ-type metal 17 and the η-type well 21, and an oxide film 23 is formed on the remaining part.
ダイオー ドは Ρ型ゥ エル 1 7 と η計ゥ ヱル 2 1 が順方向へ接 合をな して整流作用を行うが、 Ρ型半導体の基板 1 1 が接地 状態であるばあい、 Ρ型の素子分離領域 1 9 により素子が電 気的に分離される。 The diode performs a rectifying action by the forward connection between the Ρ-type well 17 and the η-meter ゥ 21, but when the Ρ-type semiconductor substrate 11 is grounded, the Ρ-type The elements are electrically separated by the element isolation region 19.
しかし、 このダイ才ー ドが無接点リ レーに用いられるばあ い、 スィ ッチ 「オフ」 の際、 ρ型半導体の基板 1 1 は電源電 圧の電位にフローティ ングされて電気的に絶縁されない。 し たがって、 そのダイ才一 ドは ρ η ρ ηサイ リ スター（thy r i s t o r ) の構造になって、 ラ ッチアップを発生せしめて、 素子を 破壊する問題点があった。  However, if this diode is used for a contactless relay, when the switch is turned off, the substrate 11 of the ρ-type semiconductor is floated to the potential of the power supply voltage and electrically isolated. Not done. Therefore, the die had a ρ η ρ η thyristor structure, and had a problem of causing a latch-up and destroying the element.
[発明の概要]  [Summary of the Invention]
したがって、 本発明の目的は、 スィ ッチ 「オフ」 の際に、 半導体の基板がフローティ ングされてもサイ リ ス夕ー搆造が 形成されてラツチアップによ り素子が破壊されることを防止 しうる、 無接点リ レー用ダイオー ドを提供するにある。 本発明の他の目的は、 前記のような無接点リ レー用ダイ才 一 ドの製法を提供するにある。 Therefore, an object of the present invention is to prevent a device from being damaged by a latch-up when a switch is turned off and a semiconductor substrate is formed even when a semiconductor substrate is floated. To provide a contactless relay diode. Another object of the present invention is to provide a method for manufacturing a die for a contactless relay as described above.
[図面の簡単な説明]  [Brief description of drawings]
図 1 は、 従来のダイ才ー ドの断面図である。 Figure 1 is a cross-sectional view of a conventional die die.
図 2 は、 本発明によるダイオー ドの断面図である。 FIG. 2 is a sectional view of a diode according to the present invention.
図 3は、 本発明によるダイ オー ドの製造工程図である。 FIG. 3 is a process chart for manufacturing a diode according to the present invention.
[符号の説明]  [Explanation of symbols]
3 1 p型半導体の基板  3 1 p-type semiconductor substrate
3 3 n ÷ 型埋設層 3 3 n ÷ type buried layer
3 5 n型ェピ夕ク シャル層  3 5 n-type epitaxial layer
3 6 , 4 5 酸化膜  3 6, 4 5 Oxide film
3 7， 4 3 p型および π型ゥ エル  3 7, 4 3 p-type and π-type
3 9 P + 型の素子分離領域 3 9 P + type element isolation region
4 1 π + 型シンク 4 1 π + type sink
4 7 , 4 9 P + 型および π + 型領域 4 7, 49 P + type and π + type region
5 1 ， 5 3 電極 5 1, 5 3 electrode
[発明の詳細な説明]  [Detailed description of the invention]
以下、 本発明のダイオー ドおよびその製法について図面を 参照しながらよ り詳しく説明する。  Hereinafter, the diode of the present invention and its manufacturing method will be described in more detail with reference to the drawings.
[実施例]  [Example]
図 2 には、 本発明の実施例による無接点リ レー用ダイォ一 ドの断面図が示されている。 このダイオー ドは、 p型半導体 の基板 3 1 に結晶成長され'た π型ェピ夕ク シャル層 3 5の所 定の部分に P型ゥ ヱル 3 7が形成されて、 この p型ゥ ヱル 3 7内に n型ゥ Iル 4 3が形成されて、 p型ゥ Iル 3 7 との p n接合をなす。 その n型ェピ夕ク シャル層 3 5 は憐 ( p ) 、 アンチモン （ S b ) またはヒ素 （A s ) などの n型の不純物 が ドーピングされて 1 D〜 1 5 μ m 位の厚さに結晶成長され る。 また、 P型ゥ Iル 3 了 はボロ ン （Boron)らの p型不純物 が 3. 5 x 1 0 ' 4〜 5. O x l O ' 4Zcm 2 位が 6〜 8 μ πι 位 の深さに注入され、 η型ゥ ヱル 4 3 は π型不純物が 1 X 1 0 14〜 5 x 1 0 ' 4/cm 2 位力 < 1 · 5〜 2 μ m 位の深さまで拡散 されて形成される。 FIG. 2 is a sectional view of a contactless relay diode according to an embodiment of the present invention. This diode is located on the π-type epitaxial layer 35 grown on the p-type semiconductor substrate 31. A P-type layer 37 is formed in a predetermined portion, and an n-type layer 43 is formed in the p-type layer 37, forming a pn junction with the p-type layer 37. The n-type epitaxial layer 35 is doped with n-type impurities such as sapphire (p), antimony (Sb), or arsenic (As) to have a thickness of about 1D to 15 μm. The crystal grows. The depth of the P-type © I le 3 Ryo is p-type impurity Boron (Boron) et al 3. 5 x 1 0 '4 ~ 5. O xl O' 4 Zcm 2 -position 6~ 8 μ πι position is injected into, the η-type © Weru 4 3 are formed by diffusion until π-type impurity is 1 X 1 0 14 ~ 5 x 1 0 '4 / cm 2 of force <1 · 5~ 2 μ m-position of the depth .
P型ゥヱル 3 7の下部には、 p型半導体の基板 3 1 と n型 ェピ夕クシャル層 3 5 に渡って面抵抗が 1 0〜 2 5 Ω □に なるように、 π型不純物が ドーピングのような 3〜 4 μ m 位 の厚さの π + 型埋設層 3 3が形成される。 また、 ρ型ゥ エル 3 了 と所定の間隔だけ建間されて、 周囲の η型ェピ夕クシャ ル層 3 5 に不純物が 1 X 1 0 ' 8〜 5 X 1 0 2 ' /cm 3 の拡散さ れた π + 型シンク （Sink) 4 1 が形成される。 この π + 型シ ンク 4 1 は n + 型埋設層 3 3 と連結されて、 p型半導体の基 板 3 1 と p型ゥ ヱル 3 7を電気的に分難させる。 Under the P-type transistor 37, π-type impurities are doped so that the sheet resistance becomes 10 to 25Ω □ over the p-type semiconductor substrate 31 and the n-type epitaxial layer 35. A π + type buried layer 33 having a thickness of about 3 to 4 μm is formed as shown in FIG. Also, is Kenkan only ρ type © El 3 Ryo a predetermined distance, impurities in η-type E peak evening Kusha Le layer 35 around 1 X 1 0 of '8 ~ 5 X 1 0 2 ' / cm 3 A diffused π + type sink (Sink) 41 is formed. The π + -type sink 41 is connected to the n + -type buried layer 33, and electrically separates the p-type semiconductor substrate 31 from the p-type semiconductor 37.
また、 π + 型シンク 4 1 寄りの n型ェピ夕クシャル層 3 5 に p型不純物が 1 X 1 0 2°〜 1 X 1 0 2'/OT 3 の拡散された P + 型素子分罄層 3 9が p型半導体の基板 3 1 と連結される ように形成される。 また、 上記の p型および n型ゥ エルなど 3 7， 4 3の表面 の所定の部分に、 アルミニウム （AI) などの導電性金属から なる電極 5 1 , 5 3が形成され、 その他残りの部分に酸化膜 4 5が形成される。 上記において、 ρ型および π型のゥ エル 3 7， 4 3の電極 5 1 , 5 3 と接触される所定の部分には、 P + 型および n + 型領域 4 7 , 4 9が形成されて、 p型およ び n型ゥ 3：ル 3 7， 4 3 と各々の電極 5 1 ， 5 3間の接続抵 抗を減少せしめる。 In addition, the n-type epitaxial layer 35 near the π + -type sink 41 has p-type impurities in a concentration of 1 × 10 2 ° to 1 × 10 2 ′ / OT 3 in a P + -type element layer. The layer 39 is formed so as to be connected to the p-type semiconductor substrate 31. Electrodes 51 and 53 made of a conductive metal such as aluminum (AI) are formed on predetermined portions of the surface of the p-type and n-type wells 37 and 43 such as the above-described p-type and n-type wells. Thus, an oxide film 45 is formed. In the above, P + -type and n + -type regions 47, 49 are formed at predetermined portions of the ρ-type and π-type wells 37, 43 which are in contact with the electrodes 51, 53. , P-type and n-type ゥ 3: The connection resistance between the electrodes 37, 43 and the respective electrodes 51, 53 is reduced.
上記の無接点リ レー用ダイオー ドは、 スィ ッチ 「オン」 の 際、 p型半導体の基扳 3 1 は接地され、 p型ゥ ヱル 3 7 と n 型ゥ エル 4 3 には、 噸方向のバイ アスが印加されて整流作用 を行う。 このとき、 P型半導体の基板 3 1 と p + 素子分離領 域 4 5が接地されて、 前記ダイォ一 ドは近位の素子などから 艳緣される。 しかし、 スィ ッチ 「オフ」 の際、 p型ゥ： rル 3 7 と n型ゥ Iル 4 3が接地され、 また、 p型半導体の基板 3 1 はフ ローティ ング状態になる。 したがって、 p型半導体の 基板 3 1 の電圧は電源電圧の電位まで上昇することになつて そのダイォー ドは p型半導体の基板 3 1 と共に p n p nサイ リ スターの構造を成すが、 π + 型埋設層 3 3 とシンク 4 1 に よ り p型半導体の基板 3 1 と電気的に分離されることによつ て、 ラ ッチアップが発生しうることを防止しうる。  When the switch is turned on, the p-type semiconductor substrate 31 is grounded, and the p-type semiconductor 37 and the n-type semiconductor 43 have the same direction as the above. Is applied to perform rectification. At this time, the P-type semiconductor substrate 31 and the p + element isolation region 45 are grounded, and the diode is exposed from a nearby element or the like. However, when the switch is “off”, the p-type semiconductor 37 and the n-type semiconductor 43 are grounded, and the p-type semiconductor substrate 31 is in a floating state. Therefore, the voltage of the p-type semiconductor substrate 31 rises to the potential of the power supply voltage, and the diode forms a pnpn thyristor structure together with the p-type semiconductor substrate 31. By being electrically separated from the p-type semiconductor substrate 31 by 33 and the sink 41, it is possible to prevent a latch-up from occurring.
図 3 (A ) 〜図 3 ( C ) は、 本発明の一実施例による無接 点リ レー用ダイ才ー ドの製造工程図である。 図 3 (A) を参照すれば、 出発物質である p型半導体の基 板 3 1 の所定部分に憐、 ヒ素またはアンチモンなどの n型の 不純物が ドーピングされており、 面抵抗が 1 0〜 2 5 Ω 位の n + 型埋設層 3 3を 3〜 4 m 位の厚さに形成される。 また、 n + 型埋設層 3 3 を含む p型半導体の基板 3 1 の表面 に非抵抗が 3〜 5 Ω · cm位の η型ェピ夕ク シャル層 3 5を、 例えば、 ィ匕学蒸着法 （Chemical Vapor Depos iti on： CVD)のよ うな通常の結晶成長方法によ り 1 0〜 1 5 y m 位の厚さに成 長せしめる。 しかるのち、 η型ェピ夕ク シャル層 3 5の上部 に酸化膜 3 6を形成し、 フ ォ ト リ ソグラフィ一方法によリ、 η + 型埋設層 3 3の中間と対応する部分の η型ェピタク シャ ル層 3 5を露光させる。 また、 η型ェピタクシャル層 3 5の 露光された部分にボ口 ンらの ρ型不純物を 3. 5 x 1 0 14~ 5. 0 x 1 0 14 / cm 2 の注入量と 6 0〜 1 O O keV のェネル ギ一でイオン注入し、 1 0 0 0での水蒸気状態で 6 0〜 8 0 分のあいだ熱処理して不純物を拡散せしめて、 6〜 8 μ m の 深さの P型ゥ： ι:ル 3 7を形成する。 この時、 熱処理のあいだ. n型ェピタク シャル層 3 5の露光された部分に酸化膜が形成 される。 イオン注入の際、 高いエネルギーによる表面損傷を 防ぐために、 n型ェピ夕ク シャル層 3 5の露光された部分に 5 0 0〜 1 5 0 0 A位の厚さの緩衝酸化膜を形成したのち、 イオン注入することもできる。 FIGS. 3 (A) to 3 (C) are manufacturing process diagrams of a die for contactless relay according to an embodiment of the present invention. Referring to FIG. 3A, a predetermined portion of a p-type semiconductor substrate 31 as a starting material is doped with n-type impurities such as arsenic or antimony, and has a sheet resistance of 10 to 2. An n + type buried layer 33 of about 5 Ω is formed to a thickness of about 3 to 4 m. Further, on the surface of the p-type semiconductor substrate 31 including the n + -type buried layer 33, an η-type epitaxial layer 35 having a non-resistance of about 3 to 5 Ω · cm , for example, It is grown to a thickness of about 10 to 15 ym by a normal crystal growth method such as the chemical vapor deposition (CVD) method. Thereafter, an oxide film 36 is formed on the upper surface of the η-type epitaxial layer 35, and the η of the portion corresponding to the middle of the η + -type buried layer 33 is formed by photolithography. The exposing layer 35 is exposed. In addition, the ρ-type impurity of Boguchi et al. Was implanted into the exposed portion of the η-type epitaxial layer 35 at a dose of 3.5 × 10 14 to 5.0 × 10 14 / cm 2 and 60 to 100 Ω. Ion implantation with keV energy is performed, and heat treatment is performed for 60 to 80 minutes in a water vapor state of 100 to diffuse impurities. P-type with a depth of 6 to 8 μm: ι : To form 37. At this time, an oxide film is formed on the exposed portions of the n-type epitaxial layer 35 during the heat treatment. During ion implantation, a buffer oxide film with a thickness of about 500 to 150 A was formed on the exposed portion of the n-type epitaxial layer 35 to prevent surface damage due to high energy. Later, ion implantation can also be performed.
図 3 ( B ) には、 熱処理のあいだ、 成長された酸化膜に通 常のフ ォ ト リ ソグラフィ ー方法によ り n + 型埋設層 3 3の周 囲とその相応する部分の酸化膜 3 6を除去して、 n型ェピ夕 クシャル層 3 5を露光せしめる。 また、 その露光された部分 にポロ ンらの p型不純物を沈積させたのち、 p型半導体の基 板 3 1 と接するように、 1 0 0 0 °C位の水蒸気状態で 6 0〜 8 0分のあいだ熱処理不純物を拡散せしめて、 1 x 1 02°〜 1 1 0 2 1 /cm 3 位の p + 型の素子分離領域 3 9を形成する < したがって、 π型ェピ夕ク シャル領域 3 5 は p型の半導体の 基板 3 1 と P + 型の素子 領域 3 P によ リ完全に取り囲ま れるようになり、 しかるのち、 再び n + 型埋設層 3 3のエツ ジ部分とその相応する部分の酸化膜 3 6を除去して n型ェピ 夕ク シャル層 3 5を露光せしめる。 また、 n型ェピ夕クシャ ル層 3 5の露光された部分に 9 0 0〜 1 1 0 0でで 2 0〜 3 0分間 P0C13 を沈積せしめたあと、 1 1 5 0 ~ 1 2 5 0 °Cの 水蒸気状態で 1 5〜 2 5分間同じ温度の室素状態で 2 0 0〜 3 0 0分間熱処理して燐を拡散せしめて、 1 x 1 0 'e〜 5 x 1 0 21 / cm 3 である n + 型シンク 4 1 を形成する。 この π + 型シンク 4 1 は n + 型埋設層 3 3 と共に p型ゥ： i:ル 3 7 と p 型半導体の基板 3 1 を電気的に完全に分陲せしめる。 また、 p + 型の素子分離領域 3 9 と n + 型シンク 4 1 を各々形成し たが、 各々 p型不純物と n型不純物とを沈積させたのち、 同 時に ドライブ一イ ンさせて形成することもできる。 Figure 3 (B) shows that the oxide film grown during heat treatment passes The surroundings of the n + -type buried layer 33 and the corresponding portion of the oxide film 36 are removed by a usual photolithography method, and the n-type epitaxial layer 35 is exposed. After the p-type impurities such as pol- lones are deposited on the exposed portions, they are brought into contact with the p-type semiconductor substrate 31 in a water vapor state of about 100 ° C to reach 60 to 80 ° C. and allowed diffused min during heat treatment impurities, 1 x 1 0 2 ° ~ 1 1 0 2 1 / cm 3 position of forming the p + -type element isolation region 3 9 <Therefore, [pi type E peak evening click interstitial region 3 5 is completely surrounded by the p-type semiconductor substrate 31 and the P + -type element region 3 P, after which the edge portion of the n + -type buried layer 33 and the corresponding portion again A portion of the oxide film 36 is removed and the n-type epitaxial layer 35 is exposed. Also, after depositing P0C13 on the exposed portion of the n-type epitaxial layer 35 at 90 to 110 for 20 to 30 minutes, 1150 to 12.5 Heat treatment at 0 ° C steam for 15 to 25 minutes at the same room temperature for 200 to 300 minutes to diffuse phosphorus, and 1 x 10 ' e to 5 x 10 21 / Form an n + type sink 4 1 that is cm 3 . The π + type sink 41, together with the n + type buried layer 33, completely electrically connects the p type ゥ: i: 37 and the p type semiconductor substrate 31. In addition, the p + -type element isolation region 39 and the n + -type sink 41 were formed, respectively, and after the p-type impurity and the n-type impurity were respectively deposited, they were formed simultaneously by drive-in. You can also.
図 3 ( C ) には、 前記 p型ゥ ： I：ル 3 7の所定部分上の酸化 膜 3 6 を防止し、 烧などの π型不純物を 4 0〜 6 0 e のェ ネルギ一と 1 x 1 0 '4〜 5 x 1 0 ' 4 / cm 2 の注入量でイ オン 注入する。 また、 前記注入された不純物を 1 1 5 0〜 1 2 5 0 °Cの水蒸気状態で 1 5〜 2 5分、 同じ温度の室素状態で 2 0〜 4 0分間の熱処理を行って 1 . 5〜 2 μ Γπ の深さに拡散 させて、 η型ゥ 1ル 4 3を形成する。 しかるのち、 その酸化 膜 3 6 を除する。 次いで、 上述の構造の全表面に再び酸化膜 4 5を形成する。 また、 ρ型ゥ エル 3 7上の酸化膜 4 5を選 択的に食刻し、 ポロ ンらの ρ型不純物を 4 0〜 6 0 keV のェ ネルギ一と 5 X 1 0 '4〜 8 x 1 0 ' 4Zcmの注入量でイオン注 入する。 そののち、 1 1 0 0〜 1 2 0 0 °Cの室素状態で 7 0 〜 1 1 0分間、 9 5 0 ~ 1 1 5 0 °Cの水蒸気状態で 4 0 ~ 6 0分間熱処理して、 その注入された不純物を拡散せしめて p + 型領域 4 7を形成する。 上述においての p + 型領域 4 7は ダイオー ドの漏れ電流を防止するためのものであって、 p型 ゥエル 3 7表面の不純物と前記拡散された不純物が合わせら れて高濃度になる。 このとき、 熱処理のあいだ前記 p型ゥェ ル 3 7上に酸化膜が形成される。 しかるのち、 n型ゥ エル 4 3上の酸化膜 4 5を選択食刻し、 P0C13 を 9 5 0 ~ 1 1 5 0 °Cで 1 5〜 2 5分間沈積したのち、 9 5 0 ~ 1 1 5 0 °Cの水 蒸気状態で 1 5〜 2 5分間同じ温度の室素状態で 2 0〜 4 0 分間熱処理して、 憐を拡散させて n + 型領域 4 9を形成する, この π + 型領域 4 9 はオーム接点（ohm ic contact) をなすた めのものであって、 その p + 型領域 4 7 と同様に、 n型ゥ ェ ル 4 3表面の不純物と拡散された不純物とが合わせられて高 濃度になる。 次いで、 露光された P + 型および n + 型領域 4 7， 4 9の表面にアルミニウムなどの導電性金属で電極 5 1 , 5 3を形成する。 FIG. 3 (C) shows that the p-type: I: oxidation on a predetermined portion of Preventing film 3 6, to ion-implanted at 4 0 to 6 0 e in E Nerugi first and 1 x 1 0 injection amount of '4 ~ 5 x 1 0' 4 / cm 2 to π-type impurity such as烧. Further, the implanted impurities are subjected to heat treatment for 115 to 25 minutes in a steam state of 115 to 125 ° C. for 15 to 25 minutes, and for 20 to 40 minutes in a green state at the same temperature. It diffuses to a depth of 5 to 2 μΓπ to form η-type 1 43. Thereafter, the oxide film 36 is removed. Next, an oxide film 45 is formed again on the entire surface of the above structure. Also, the oxide film 45 on the ρ-type well 37 is selectively etched, and the ρ-type impurities of Polon et al. Are mixed with the energy of 40 to 60 keV and 5 × 10 ' 4 to 8 to enter the ion Note in implantation of x 1 0 '4 Zcm. After that, it is heat-treated for 70 to 110 minutes in a room temperature of 110 to 120 ° C and for 40 to 60 minutes in a steam state of 950 to 115 ° C. Then, the implanted impurities are diffused to form p + -type regions 47. The p + -type region 47 described above is for preventing a leakage current of the diode, and the impurity on the surface of the p-type well 37 and the diffused impurity are combined to have a high concentration. At this time, an oxide film is formed on the p-type well 37 during the heat treatment. After accordingly, after selecting etch the oxide film 4 5 on the n-type © El 4 3, was deposited 1 5-2 5 minutes P0C1 3 at 9 5 0 ~ 1 1 5 0 ° C, 9 5 0 ~ 1 Heat treatment is carried out for 15 to 25 minutes at the same temperature in the water vapor state at 150 ° C for 20 to 40 minutes, and the heat is diffused to form n + type regions 49, which π The + type region 49 forms an ohmic contact. As in the case of the p + -type region 47, the impurity on the surface of the n-type well 43 and the diffused impurity are combined to have a high concentration. Next, electrodes 51 and 53 are formed on the exposed surfaces of the P + type and n + type regions 47 and 49 with a conductive metal such as aluminum.
したがって、 本発明は n + 型埋設層およびシンクによ り p 型半導体の基板と p型ゥ エルを電気的に分離させることによ つてラ ッチアップの発生を防止し、 ダイ オー ドの破壊を防止 しうる特長がある。 前述したように、 本発明はこの実施例に ついて説明したが、 本発明の S囲を逸脱することなく、 当業 者は種々の改変をなし得るであろう。  Therefore, the present invention prevents the latch-up from occurring by preventing the p-type semiconductor substrate and the p-type well from being electrically separated by the n + -type buried layer and the sink, thereby preventing diode breakdown. There are features that can be done. As described above, the present invention has been described with respect to this embodiment. However, those skilled in the art can make various modifications without departing from the scope of the present invention.
即ち、 本発明の実施例においては、 出発物質と して p型半 導体の基板を用いたが、 n型半導体の基板を用いることもで き、 このばあいには各領域などは反対導電性にならなければ ならない。  That is, in the embodiment of the present invention, a p-type semiconductor substrate is used as a starting material, but an n-type semiconductor substrate may be used. In this case, each region and the like have opposite conductivity. Have to become

Claims

特許請求の範囲 Claims
1 . 第 1 導電型の半導体の基板と、  1. a semiconductor substrate of the first conductivity type;
前記半導体の基板の上部に形成された第 1 導電型と他の導 電型である第 2導電型のェピ夕ク シャ ル層と、  An epitaxial layer of a first conductivity type and another conductivity type of a second conductivity type formed on the semiconductor substrate;
前記第 2導電型のェピ夕クシャル層の所定の部分に拡散さ れた第 1 導電型ゥ Iルと、  A first conductive type layer diffused into a predetermined portion of the second conductive type epitaxial layer;
前記第 1 導電型ゥ エルの所定の部分に拡散されて、 p n接 合をなす第 2導電型ゥ エルと、  A second conductivity type well diffused into a predetermined portion of the first conductivity type well to form a pn junction;
前記第 1 導電型ゥ エルの下部の前記第 1 導電型の半導体の 基板と前記第 2導電型のェピタク シャ ル層にわたつて形成さ れた、 高濃度の第 2導電型の埋設層と、  A high-concentration second-conductivity-type buried layer formed over the first-conductivity-type semiconductor substrate below the first-conductivity-type well and the second-conductivity-type epitaxial layer;
前記第 2導電型の埋設層寄りの前記第 2ェピタクシャル層 に、 前記第 1 導電型の半導体の基板と連結されるように形成 された高濃度の第 1 導電型の素子分離領域と、  A high-concentration first-conductivity-type element isolation region formed so as to be connected to the first-conductivity-type semiconductor substrate in the second epitaxial layer near the second-conductivity-type buried layer;
前記高濃度の第 2導電型の埋設層と連結されるように前記 第 1 導電型のゥ ェル寄リ前記第 2導電型のェピ夕クシャル層 に形成されて、 前記高濃度の第 2導電型の埋設層と共に前記 第 1 導電型の半導体の基板と、 前記第 1 導電型ゥ zルを電気 的に分難する高濃度の第 2導電型シンク  The second conductive type epi layer is formed on the second conductive type epitaxial layer so as to be connected to the high-concentration second conductive type buried layer. A semiconductor substrate of the first conductivity type together with a buried layer of the conductivity type; and a high-concentration second conductivity type sink for electrically dividing the first conductivity type element.
とを含むことを特長とするダイオー ド。 A diode characterized by including:
2 . 前記第 1 導電型が P型であり、 第 2導電型が n型である 請求項 1 記載のダイオー ド。  2. The diode according to claim 1, wherein the first conductivity type is a P-type, and the second conductivity type is an n-type.
3 . 前記第 1 導電型ゥ エルの表面に、 第 1 導電型の不純物が 高濃度で ドーピングされた請求項 1 記載のダイオー ド。 3. An impurity of the first conductivity type is present on the surface of the first conductivity type well. 2. The diode according to claim 1, which is heavily doped.
4 . 前記第 2導電型ゥエルの表面の所定の部分に、 第 2導電 型の不純物が高濃度で ド一ピングされた請求項 1 記載のダイ オー ド。  4. The diode according to claim 1, wherein a predetermined portion of the surface of the second conductivity type well is doped with a second conductivity type impurity at a high concentration.
5 . 前記第 1 導電型の半導体の基板に、 第 2導電型のェピタ クシャル層を結晶成長する工程と、  5. crystal growing a second conductivity type epitaxial layer on the first conductivity type semiconductor substrate;
前記第 1 導電型の半導体基板と前記第 2導電型のェピタク シャル層の所定部分にわたって高濃度の第 2導電型の埋設層 を形成する工程と、  Forming a high-concentration buried layer of the second conductivity type over predetermined portions of the first conductivity type semiconductor substrate and the second conductivity type epitaxial layer;
前記第 2導電型の埋設層寄りの前記第 2導電型のェピタク シャ ル層に、 前記第 1 導電型の半導体の基板と連結される高 濃度の第 1 導電型の素子分難領域を形成する工程と、  A high-concentration first conductivity type element isolation region connected to the first conductivity type semiconductor substrate is formed in the second conductivity type epitaxial layer near the second conductivity type buried layer. Process and
前記第 2導電型のェピタクシャ ル層の所定部分に、 前記埋 設層と連結される高濃度の第 2導電型のシンクを形成するェ 程と、  Forming a high-concentration second-conductivity-type sink connected to the buried layer at a predetermined portion of the second-conductivity-type epitaxial layer;
前記高濃度の第 2導電型の埋設層の上部の前記第 2導電型 のェピタクシ ャ ル層に第 1 導電型のゥ Iルを形成する工程と 前記第 1 導電型ゥ ル内に第 2導電型ゥエルを形成するェ とを含むことを特長とするダイ才ー ドの製法。  Forming a first conductive type element in the second conductive type epitaxy layer above the high concentration second conductive type buried layer; and forming a second conductive type in the first conductive type layer. A method for producing die die, characterized in that the method includes forming a die.
6 . 前記第 1 導電型ゥ ルの表面に、 第 1 導電型の不純物を 高濃度で注入する工程をさらに備える請求項 5記載のダイ才 ー ドの製法。 6. The method for producing a die seed according to claim 5, further comprising a step of injecting impurities of the first conductivity type into the surface of the first conductivity type mold at a high concentration.
7 . 前記第 2導電型ゥ エルの表面の所定の部分に、 第 2導電 型の不純物を高濃度で注入する工程をさらに備える請求項 6 記載のダイ才ー ドの製法。 7. The method according to claim 6, further comprising a step of implanting a second conductive type impurity at a high concentration into a predetermined portion of the surface of the second conductive type well.
PCT/KR1995/000003 1994-01-12 1995-01-12 Diode and production method thereof WO1995019647A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019940000406A KR0132022B1 (en) 1994-01-12 1994-01-12 Diode and its fabrication method
KR1994/406 1994-01-12

Publications (1)

Publication Number Publication Date
WO1995019647A1 true WO1995019647A1 (en) 1995-07-20

Family

ID=19375515

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR1995/000003 WO1995019647A1 (en) 1994-01-12 1995-01-12 Diode and production method thereof

Country Status (2)

Country Link
KR (1) KR0132022B1 (en)
WO (1) WO1995019647A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6527801B1 (en) 2000-04-13 2003-03-04 Advanced Cardiovascular Systems, Inc. Biodegradable drug delivery material for stent
CN103367461A (en) * 2012-04-03 2013-10-23 台湾积体电路制造股份有限公司 Triple well isolated diode and method of making

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5076988A (en) * 1973-11-05 1975-06-24
JPS6014450A (en) * 1983-07-05 1985-01-25 Sanyo Electric Co Ltd Semiconductor integrated circuit
JPH06104459A (en) * 1992-09-21 1994-04-15 Sanken Electric Co Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5076988A (en) * 1973-11-05 1975-06-24
JPS6014450A (en) * 1983-07-05 1985-01-25 Sanyo Electric Co Ltd Semiconductor integrated circuit
JPH06104459A (en) * 1992-09-21 1994-04-15 Sanken Electric Co Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6527801B1 (en) 2000-04-13 2003-03-04 Advanced Cardiovascular Systems, Inc. Biodegradable drug delivery material for stent
CN103367461A (en) * 2012-04-03 2013-10-23 台湾积体电路制造股份有限公司 Triple well isolated diode and method of making

Also Published As

Publication number Publication date
KR950024282A (en) 1995-08-21
KR0132022B1 (en) 1998-04-14

Similar Documents

Publication Publication Date Title
US5119162A (en) Integrated power DMOS circuit with protection diode
EP0708482B1 (en) BiCDMOS process technology.
US7285475B2 (en) Integrated circuit having a device wafer with a diffused doped backside layer
US5081517A (en) Mixed technology integrated circuit comprising CMOS structures and efficient lateral bipolar transistors with a high early voltage and fabrication thereof
US5679587A (en) Method of fabricating an integrated circuit with vertical bipolar power transistors and isolated lateral bipolar control transistors
KR20010012906A (en) Integrated circuit, components thereof and manufacturing method
JPS63199463A (en) Manufacture of bipolar transistor
JP2503733B2 (en) Method for manufacturing semiconductor device
EP0029552A2 (en) Method for producing a semiconductor device
CN106233439B (en) High breakdown n-type buried layer
GB1599954A (en) Semiconductor devices and their fabrication
US4660278A (en) Process of making IC isolation structure
EP0118102A2 (en) Method for manufacturing a semiconductor device
WO1995019647A1 (en) Diode and production method thereof
WO1994016461A1 (en) Cmos locos isolation for self-aligned npn bjt in a bicmos process
GB1593937A (en) I2l integrated circuitry
US6806159B2 (en) Method for manufacturing a semiconductor device with sinker contact region
US6790736B2 (en) Method for manufacturing and structure of semiconductor device with polysilicon definition structure
US7164186B2 (en) Structure of semiconductor device with sinker contact region
EP0281032B1 (en) Semiconductor device comprising a field effect transistor
JP3257523B2 (en) Method for manufacturing semiconductor device
JPH11233796A (en) Manufacture of schottky diode
KR940007454B1 (en) Manufacturing method of semiconductor device
De La Moneda Semiconductor devices and their fabrication
JPS60105265A (en) Manufacture of complementary type semiconductor device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP US