JPH0474478A - Diode - Google Patents

Diode

Info

Publication number
JPH0474478A
JPH0474478A JP18911190A JP18911190A JPH0474478A JP H0474478 A JPH0474478 A JP H0474478A JP 18911190 A JP18911190 A JP 18911190A JP 18911190 A JP18911190 A JP 18911190A JP H0474478 A JPH0474478 A JP H0474478A
Authority
JP
Japan
Prior art keywords
type
diffusion region
epitaxial layer
region
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18911190A
Other languages
Japanese (ja)
Inventor
Masayoshi Achinami
阿知波 正義
Koichi Kanezaki
金崎 孝一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP18911190A priority Critical patent/JPH0474478A/en
Publication of JPH0474478A publication Critical patent/JPH0474478A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To increase dielectric strength in the reverse direction, and to eliminate the parasitic movement by forming a high-concentration P-type diffusion layer region to wrap the first low-concentration N-type epitaxial layer, and then by forming the second N-type epitaxial layer to wrap the P-type diffusion region, electrically connecting, and making it into an anode. CONSTITUTION:By connecting a P-type diffusion region 16 with an N-type diffusion region 17, a wiring electrode 19 is made. By connecting a N-type diffusion region 18 with a wiring region 20, a cathode electrode is made. The dielectric strength of a diode equals to the dielectric strength of PN junction of an N-type diffusion epitaxial layer 14, a P-type furied diffusion region 11, and the P-type diffusion region 16. When a diode is made to move to the forward direction, most of electrons are injected from the N-type epitaxial layer 14 in the highly concentrated P-type buried diffusion region 11, and in the P-type diffusion region 16. These electrons are re-coupled there, and are eliminated, and then they make anode current. It never occurs that the electric current flowing in a diode generates the parasitic effect of flowing into other portions.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置に用いるダイオードに関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a diode used in a semiconductor device.

従来の技術 半導体装置に従来より用いられてきたダイオードの断面
図を第2図に示す。
BACKGROUND OF THE INVENTION FIG. 2 shows a cross-sectional view of a diode conventionally used in semiconductor devices.

第2図において1はP型半導体基板、2はP型半導体基
板1上に形成されたN型埋込拡散領域、3はN型埋込拡
散領域2上に形成されたN型エピタキシャル層、4はN
型エピタキシャル層3を貫通しP型半導体基板1に達す
るP型分離拡散領域、5はP型半導体基板1及びP型分
離拡散領域4で囲まれたトランジスタのコレクタとなる
N型エピタキシャル層3中に形成されたトランジスタの
ベースとなるP型拡散領域、6はP型拡散領域5中に形
成されたトランジスタのエミッタとなるN型拡散領域、
7は通常N型拡散領域6と同時に形成されるトランジス
タのコレクタコンタクトを接続するN型拡散領域、8は
シリコン酸化膜、9と10は配線電極であり、配線電極
10はN型拡散領域6に、配線電極9はP型拡計領域5
とN型拡散領域7とに接続している。トランジスタのへ
−スとなるP型拡散領域5とコレクタとなるN型埋込拡
散領域2及びN型エピタキシャル層3がダイオードのア
ノードを形成し、トランジスタのエミッタとなるN型拡
散領域6がダイオードのカソードとなる。配線電極9及
び10はそれぞれダイオードのアノードとカソードの配
線電極となる。
In FIG. 2, 1 is a P-type semiconductor substrate, 2 is an N-type buried diffusion region formed on the P-type semiconductor substrate 1, 3 is an N-type epitaxial layer formed on the N-type buried diffusion region 2, and 4 is an N-type buried diffusion region formed on the N-type buried diffusion region 2. is N
A P-type isolation diffusion region 5 penetrates the type epitaxial layer 3 and reaches the P-type semiconductor substrate 1; 6 is a P-type diffusion region which becomes the base of the formed transistor; 6 is an N-type diffusion region which becomes the emitter of the transistor formed in the P-type diffusion region 5;
7 is an N-type diffusion region that connects the collector contact of the transistor, which is usually formed at the same time as the N-type diffusion region 6; 8 is a silicon oxide film; 9 and 10 are wiring electrodes; the wiring electrode 10 is connected to the N-type diffusion region 6; , the wiring electrode 9 is a P-type expanded area 5
and the N-type diffusion region 7. The P-type diffusion region 5, which becomes the base of the transistor, the N-type buried diffusion region 2, which becomes the collector, and the N-type epitaxial layer 3 form the anode of the diode, and the N-type diffusion region 6, which becomes the emitter of the transistor, forms the diode's anode. It becomes a cathode. The wiring electrodes 9 and 10 serve as the anode and cathode wiring electrodes of the diode, respectively.

この種の集積回路用ダイオードの耐圧は、トランジスタ
のベース・エミッタ間耐圧と同じであり、通常の半導体
集積回路ではプロセスにも依存するが6〜8v程度であ
った。
The breakdown voltage of this type of integrated circuit diode is the same as the base-emitter breakdown voltage of a transistor, and in a normal semiconductor integrated circuit, it is about 6 to 8V, although it depends on the process.

発明が解決しようとする課題 回路設計上、従来用いてきたダイオードで得られる耐圧
以上の耐圧を有するダイオードが要望されることがある
。ところでPN接合があればダイオードは一応構成可能
であるが、耐圧の大きなダイオードを構成しようとして
例えば第2図中のP型拡散領域5をアノードとし、N型
エピタキシャル層3をカソードとして用いたとする。
Problems to be Solved by the Invention In terms of circuit design, a diode having a withstand voltage higher than that obtained with conventionally used diodes is sometimes required. By the way, it is possible to construct a diode if there is a PN junction, but suppose that in an attempt to construct a diode with a high breakdown voltage, for example, the P-type diffusion region 5 in FIG. 2 is used as an anode and the N-type epitaxial layer 3 is used as a cathode.

この接合の耐圧はトランジスタのベース・コレクタ間耐
圧きなるため、通常30 V以上は容易に確保できる。
Since the withstand voltage of this junction is determined by the withstand voltage between the base and collector of the transistor, a voltage of 30 V or more can usually be easily secured.

しかるにこの種のダイオードには、順方向動作をさせた
とき、P型拡散領域5がらN型エピタキシャル層3に注
入されたホールは接地されているP型半導体基板1に流
れるという、いわゆる寄生動作か存在する。このことは
カソード電流がアノード電流より少ないという不都合を
もたらす。
However, in this type of diode, when operated in the forward direction, holes injected into the N-type epitaxial layer 3 from the P-type diffusion region 5 flow into the grounded P-type semiconductor substrate 1, which is a so-called parasitic operation. exist. This has the disadvantage that the cathode current is less than the anode current.

課題を解決するための手段 この課題を解決するため、本発明のダイオードはカソー
ドとなる第1の濃度の低いN型エピタキシャル層を包み
込む関係に高濃度P型拡散領域を形成し、さらにこのP
型拡散領域を包み込む第2のN型エピタキシャル層を形
成し、前記P型拡散領域と第2のN型エピタキシャル層
を電気的に接続し、アノードとする構成である。
Means for Solving the Problem In order to solve this problem, the diode of the present invention is provided by forming a highly doped P-type diffusion region surrounding a first low-concentration N-type epitaxial layer serving as a cathode;
A second N-type epitaxial layer is formed to surround the type diffusion region, and the P-type diffusion region and the second N-type epitaxial layer are electrically connected to form an anode.

作用 この構成をとることにより、カソードとなるN型領域か
らP型頭域に注入された電子は、濃度の高いP型頭域で
消滅するか、仮に第2のN型領域に到達してもアノード
電流となるため、不都合な寄生動作をすることはなく、
ダイオードのPN接合となる第1のN型拡散領域とP型
拡散領域の耐圧を高くすることが可能となる。
Effect By adopting this configuration, electrons injected from the N-type region that becomes the cathode into the P-type head region will either disappear in the P-type head region with high concentration, or even if they reach the second N-type region. Since it is an anode current, there is no undesirable parasitic operation.
It becomes possible to increase the withstand voltage of the first N-type diffusion region and the P-type diffusion region that form the PN junction of the diode.

実施例 第1図は本発明にかかる半導体装置に用いるダイオード
の一実施例である。第1図において、■はP型半導体基
板、2はP型半導体基板1上に形成されたN型埋込拡散
領域、11はN型埋込拡散領域2上に形成されたP型埋
込拡散領域、12はP型半導体基板1上に形成されたP
型埋込拡散領域11に類似したP型埋込分離拡散領域で
ある。
Embodiment FIG. 1 shows an embodiment of a diode used in a semiconductor device according to the present invention. In FIG. 1, ■ is a P-type semiconductor substrate, 2 is an N-type buried diffusion region formed on the P-type semiconductor substrate 1, and 11 is a P-type buried diffusion region formed on the N-type buried diffusion region 2. A region 12 is a P-type semiconductor substrate 1 formed on the P-type semiconductor substrate 1.
This is a P-type buried isolation diffusion region similar to type buried diffusion region 11.

以上の領域が形成された後、N型エピタキシャル層13
.14が成長される。表面から形成されたP型分離拡散
領域15はP型埋込分離拡散領域12と接し、N型埋込
拡散領域2、N型エピタキシャル層13.14はP型半
導体基板1.P型分離拡散領域15.P型埋込分離拡散
領域12により島状に分離される。P型拡散領域16は
N型エピタキシャル層13の表面からP型埋込拡散領域
11に至る深い拡散領域であり、N型エピタキシャル領
域14をとり囲む関係で形成されたものであるが、この
領域はP型分離拡散領域15と同時形成可能である。N
型拡散領域17.18はそれぞれN型エピタキシャル層
13.14からオーミックに抵抗をとり出すための拡散
層である。
After the above regions are formed, the N-type epitaxial layer 13
.. 14 will be grown. The P type isolation diffusion region 15 formed from the surface is in contact with the P type buried isolation diffusion region 12, and the N type buried diffusion region 2 and the N type epitaxial layer 13.14 are in contact with the P type semiconductor substrate 1. P-type isolation diffusion region 15. They are separated into islands by P-type buried isolation and diffusion regions 12. The P-type diffusion region 16 is a deep diffusion region extending from the surface of the N-type epitaxial layer 13 to the P-type buried diffusion region 11, and is formed to surround the N-type epitaxial region 14. It can be formed simultaneously with the P-type isolation diffusion region 15. N
Type diffusion regions 17 and 18 are diffusion layers for ohmically extracting resistance from N type epitaxial layers 13 and 14, respectively.

本実施例におけるダイオードは、P型拡散領域16とN
型拡散領域17を配線電極19にて接続し、アノード電
極とし、N型拡散領域18に配線電極20をつけてカソ
ード電極としたものである。
The diode in this embodiment has a P type diffusion region 16 and an N
The type diffusion region 17 is connected with a wiring electrode 19 to serve as an anode electrode, and the N type diffusion region 18 is connected with a wiring electrode 20 to serve as a cathode electrode.

このような構成においては、ダイオードの耐圧はN型エ
ピタキシャル層14とP型埋込拡散領域11.P型拡散
領域16のなすPN接合の耐圧となる。N型エピタキシ
ャル層14の不純物濃度は通常トランジスタのコレクタ
を形成することの要請から、5×1014cm−3〜5
×10150ITl−3程度が用いられているので、5
0〜100vの耐圧は容易に得ることが可能である。又
ダイオードを順方向に動作させたとき、N型エピタキシ
ャル層14から高濃度のP型埋込拡散領域11.P型拡
散領域16に注入された電子の多くは、ここで再結合し
て消滅し、アノード電流となる。N型埋込拡散領域2お
よびN型エピタキシャル層13まで生き延びた電子もこ
の領域がアノード電極である配線電極19に接続されて
いるため、アノード電流となる。
In such a configuration, the breakdown voltage of the diode is determined by the N-type epitaxial layer 14 and the P-type buried diffusion region 11. This is the breakdown voltage of the PN junction formed by the P-type diffusion region 16. The impurity concentration of the N-type epitaxial layer 14 is usually 5×10 14 cm −3 to 5 due to the requirement of forming the collector of a transistor.
Since approximately ×10150ITl-3 is used, 5
A breakdown voltage of 0 to 100V can be easily obtained. Further, when the diode is operated in the forward direction, the highly doped P-type buried diffusion region 11 . Most of the electrons injected into the P-type diffusion region 16 recombine and disappear, becoming an anode current. Electrons that have survived to the N-type buried diffusion region 2 and the N-type epitaxial layer 13 also become an anode current because these regions are connected to the wiring electrode 19 which is an anode electrode.

一方当然のことながら、P型埋込拡散領域11゜P型拡
散領域16よりN型エピタキシャル層14に注入された
ホールは、全てカソード電流となる。かくしてダイオー
ドを流れる電流が、他の部分に逃げるという寄生効果を
生じるということはない。
On the other hand, as a matter of course, all the holes injected into the N-type epitaxial layer 14 from the P-type buried diffusion region 11° and the P-type diffusion region 16 become cathode current. In this way, the current flowing through the diode does not have the parasitic effect of escaping to other parts.

発明の効果 本発明によれば、逆方向耐圧が高く、がっ寄生動作のな
い良好な特性を有するダイオードを複雑な製造工程を使
用することなく提供できる。
Effects of the Invention According to the present invention, a diode having a high reverse breakdown voltage and good characteristics without parasitic operation can be provided without using a complicated manufacturing process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例にががるダイオードの斜視断
面図、第2図は従来のダイオードの断面図である。 1・・・・・・P型半導体基板、2・・・・・・N型埋
込拡散領域、11・・・・・・P型埋込拡散領域、12
・・・・・・P型埋込分離拡散領域、13.14・・・
・・・N型エピタキシャル層、15・・・・・・P型分
離拡散領域、16・・・・・・P型拡散領域、17.1
8・・・・・・N型拡散領域、19.20・・・・・・
配線電極。
FIG. 1 is a perspective sectional view of a diode according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional diode. 1... P-type semiconductor substrate, 2... N-type buried diffusion region, 11... P-type buried diffusion region, 12
...P-type buried isolation diffusion region, 13.14...
...N type epitaxial layer, 15...P type isolation diffusion region, 16...P type diffusion region, 17.1
8...N-type diffusion region, 19.20...
Wiring electrode.

Claims (1)

【特許請求の範囲】[Claims]  P型半導体基板と、前記P型半導体基板上に形成され
たN型埋込拡散領域と、前記N型埋込拡散領域に接する
ことなく、かつ前記N型埋込拡散領域を囲むように形成
されたP型埋込分離拡散領域と、前記N型埋込拡散領域
の上でかつ前記N型埋込拡散領域内に形成されたP型埋
込拡散領域とを備えた基板と、前記基板上に成長された
N型エピタキシャル層と、前記N型エピタキシャル層を
貫通し、前記P型埋込拡散領域に達し、かつ前記N型エ
ピタキシャル層の一部を包囲して形成されたアノードと
なるP型拡散領域と、前記N型エピタキシャル層を貫通
し前記P型埋込分離拡散領域に達し、かつ前記N型エピ
タキシャル層を包囲して形成されたP型分離拡散領域と
を備え、前記N型エピタキシャル層が前記P型拡散領域
で区切られた第1のエピタキシャル領域と、前記P型分
離拡散領域と前記P型拡散領域によりはさまれた第2の
N型エピタキシャル領域とで構成され、前記P型拡散領
域と前記第2のN型エピタキシャル領域を電気的に接続
してアノードとし、前記第1のN型エピタキシャル領域
をカソードとするダイオード。
a P-type semiconductor substrate; an N-type buried diffusion region formed on the P-type semiconductor substrate; a P-type buried isolation diffusion region formed on the N-type buried diffusion region and in the N-type buried diffusion region; The grown N-type epitaxial layer and the P-type diffusion that penetrates the N-type epitaxial layer, reaches the P-type buried diffusion region, and becomes an anode formed by surrounding a part of the N-type epitaxial layer. a P-type isolation diffusion region penetrating the N-type epitaxial layer to reach the P-type buried isolation diffusion region and surrounding the N-type epitaxial layer; A first epitaxial region separated by the P-type diffusion region, and a second N-type epitaxial region sandwiched between the P-type isolation diffusion region and the P-type diffusion region, and the P-type diffusion region and the second N-type epitaxial region are electrically connected to each other to serve as an anode, and the first N-type epitaxial region is used as a cathode.
JP18911190A 1990-07-16 1990-07-16 Diode Pending JPH0474478A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18911190A JPH0474478A (en) 1990-07-16 1990-07-16 Diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18911190A JPH0474478A (en) 1990-07-16 1990-07-16 Diode

Publications (1)

Publication Number Publication Date
JPH0474478A true JPH0474478A (en) 1992-03-09

Family

ID=16235559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18911190A Pending JPH0474478A (en) 1990-07-16 1990-07-16 Diode

Country Status (1)

Country Link
JP (1) JPH0474478A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299477A (en) * 1999-04-12 2000-10-24 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
KR100431189B1 (en) * 2002-06-07 2004-05-12 삼성전기주식회사 Semiconductor device package and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59158568A (en) * 1983-02-24 1984-09-08 テレフオンアクチ−ボラゲツト・エル・エムエリクソン Monolithic integrated circuit diode
JPS6267855A (en) * 1985-09-20 1987-03-27 Sanyo Electric Co Ltd Semiconductor integrated injection logic circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59158568A (en) * 1983-02-24 1984-09-08 テレフオンアクチ−ボラゲツト・エル・エムエリクソン Monolithic integrated circuit diode
JPS6267855A (en) * 1985-09-20 1987-03-27 Sanyo Electric Co Ltd Semiconductor integrated injection logic circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299477A (en) * 1999-04-12 2000-10-24 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
KR100431189B1 (en) * 2002-06-07 2004-05-12 삼성전기주식회사 Semiconductor device package and method of manufacturing the same

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