JP2502696B2 - Semiconductor integrated circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a breakdown voltage of a semiconductor integrated circuit device.

2. Description of the Related Art As a device configuration of a conventional lateral PNPN thyristor of a semiconductor integrated circuit device, there is a configuration as shown in FIG. 1 is a P type silicon substrate, 2 is an N type high concentration buried layer, 3 is a P type high concentration isolation layer, 4 is an N type low concentration epitaxial layer, 5 is a P type gate layer, 6 is an N type cathode layer, 7 Is a P-type anode layer.

The breakdown voltage between the anode and the gate of the lateral PNPN thyristor configured as described above is mainly determined by the diffusion depth of the gate layer 5 when the concentration of the N-type low concentration epitaxial layer 4 is constant. This is because the degree of curvature of the depletion layer extending from the end portion changes depending on the depth of the gate diffusion, and the strength of the electric field per unit area concentrated on the curved portion changes. That is, if the gate diffusion is shallow, the curvature becomes steeper, the electric field concentrates faster, and the breakdown voltage decreases. On the other hand, the switching speed was fairly fast because the N-type high-concentration burying layer 2 was on the entire surface of the device.

DISCLOSURE OF INVENTION Problems to be Solved by the Invention However, if an attempt is made to deepen the diffusion layer to improve the breakdown voltage based on the above-described conventional configuration, the area occupied by the element formed thereby increases, and the integrated circuit device This has been a hindrance, and there is a problem that the time required for the diffusion process becomes long.

The present invention solves the above problems, and an object of the present invention is to provide a semiconductor integrated circuit device capable of increasing the breakdown voltage while maintaining a high switching speed.

Means for Solving the Problems To achieve this object, a semiconductor integrated circuit according to the present invention comprises a semiconductor substrate (11) of one conductivity type and a first conductive type semiconductor substrate (11) of a low conductivity type formed on the semiconductor substrate. Semiconductor layers (14)
A reverse-conductivity-type high-concentration buried layer (12) selectively formed between the semiconductor substrate and the first semiconductor layer, and the first semiconductor immediately above the buried layer. A second semiconductor layer (17) of one conductivity type formed on the surface of the layer, and a third semiconductor layer of one conductivity type formed on the surface of the first semiconductor layer separated from the second semiconductor layer ( 15) and a fourth semiconductor layer (16) of the opposite conductivity type formed in the third semiconductor layer, the semiconductor substrate (11) and the fourth semiconductor layer (16)
It has a configuration of connecting and.

Operation With this configuration, the lateral thyristor is configured and serves as the base region of the lateral transistor formed between the second semiconductor layer 17 and the third semiconductor layer 15 when the switching operation is performed from the turn-on state to the turn-off state. Carriers running through the first semiconductor layer 14 are absorbed by the high-concentration buried layer 12, and the operation of turning off at high speed can be maintained.

In addition, when a high voltage is applied between the fourth semiconductor layer 16 and the second semiconductor layer, the depletion layer 18 at the PN junction between the third semiconductor layer 15 and the first semiconductor layer 14 becomes the third The semiconductor layer 15
Of the semiconductor substrate 11 and the first substrate
The depletion layer 18 in the PN junction with the semiconductor layer 14 extends vertically above and below the PN junction. Even if the applied voltage rises and the upper and lower depletion layers come into contact with each other, since the potentials are almost the same, breakdown breakdown does not occur. Therefore, a high breakdown voltage is maintained while maintaining a high switching speed. Can be secured.

Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of a lateral PNPN thyristor according to an embodiment of the present invention. In FIG. 1, 11 is a P-type silicon substrate, 12 is an N-type high-concentration buried layer, 13 is a P-type high-concentration separation layer,
14 is an N type low concentration epitaxial layer, 15 is a P type gate layer,
16 is an N-type cathode layer and 17 is a P-type anode layer. The details will be described below with reference to the drawings.

Regarding electrical connection, it is common to connect the gate electrode and the cathode electrode through a resistor in the actual use condition to take measures against malfunction.In comparison with the voltage applied to the anode electrode, where breakdown voltage is a problem, Since the voltage between the cathodes (forward diode voltage) is close to zero, as shown in FIG. 2, P-type gate layer (hereinafter referred to as gate) 15, N-type cathode layer (hereinafter referred to as cathode) 16, P-type Silicon substrate (hereinafter referred to as substrate) 11, P-type high concentration separation layer (hereinafter referred to as separation) 13
Are all at the same potential on the low voltage side, and the P-type anode layer (hereinafter referred to as the anode) 17 is on the high voltage side.

First, in FIG. 2, when the potential of the anode 17 rises a little,
In the junction region, the depletion layer 18 rises slightly above the substrate 11 and extends slightly from the isolation 13 and from the gate 15. Then the anode 17
When the electric potential of is further increased, the depletion layer 18 rising from the substrate 11 contacts the depletion layer 18 extending from the gate 15, as shown in FIG. The depletion layer 18 extending from the isolation 13 also contacts the depletion layer 18 extending from the gate. At this time, since the gate 15, the substrate 11, and the isolation 13 are all at the same potential, no breakdown current flows.

When the potential of the anode 17 further rises, as shown in FIG. 4, the depletion layer 18 rising from the substrate 11 relaxes the curved portion of the depletion layer 18 extending from the gate 15, and breakdown breakdown does not occur. Here, if the N-type high-concentration buried layer 12 is immediately below the gate, the depletion layer 18 does not rise from the substrate 11,
The curvature of the depletion layer 18 of 15 is not relaxed, and breakdown breakdown occurs. The breakdown voltage breakdown in this structure is that the potential of the anode 17 rises further and the depletion layer 18 extending from the gate 15 or the isolation 13 is extended.
Is applied to the anode 17 and a current flows, breakdown voltage breakdown occurs between the N-type high-concentration buried layer 12 and the substrate 11, or the depletion layer 18 extending from the separation 13 hits the N-type high-concentration buried layer 12 to generate an electric field. It's either when I concentrated. Further, since the switching speed includes the N-type high-concentration buried layer 12 having a concentration of 10,000 times or more that of the N-type low-concentration epitaxial layer 14, it does not decrease.

As described above, according to this embodiment, by inserting the N-type high-concentration buried layer 12 just below the anode, the breakdown voltage with respect to the anode 17 can be increased without reducing the switching speed.

EFFECTS OF THE INVENTION According to the present invention, by inserting a high-concentration buried layer only in a specific region, the breakdown voltage can be increased without lowering the switching speed, the breakdown voltage is high in a small element area, and the normal process is easy. It is possible to realize an excellent semiconductor integrated circuit device that can be built into.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIGS. 2 to 4 are sectional views showing the expansion of a depletion layer in the embodiment of the present invention, and FIG. 5 is a conventional semiconductor. It is sectional drawing of an integrated circuit device. 1 ... P-type silicon substrate, 2 ... N-type high concentration buried layer, 3
... P-type high-concentration separation layer, 4 ... N-type low-concentration epitaxial layer, 5 ... P-type gate layer, 6 ... N-type cathode layer, 7
... N-type anode layer, 11 ... P-type silicon substrate, 12 ...
N-type high-concentration buried layer, 13 ... P-type high-concentration separation layer, 14 ... N
-Type low-concentration epitaxial layer, 15 ... P-type gate layer, 16 ...
... N-type cathode layer, 17 ... N-type anode layer, 18 ... depletion layer.

Claims (1)

(57) [Claims] 1. A semiconductor substrate of one conductivity type, a low-concentration first semiconductor layer of the opposite conductivity type formed on the semiconductor substrate, and a selection between the semiconductor substrate and the first semiconductor layer. Of a reverse-conductivity-type high-concentration buried layer, a second-type semiconductor layer of one conductivity type formed on the surface of the first semiconductor layer directly above the buried layer, and the second layer A third semiconductor layer of one conductivity type formed on the surface of the first semiconductor layer separated from the second semiconductor layer, and a fourth semiconductor layer of the opposite conductivity type formed in the third semiconductor layer. A semiconductor integrated circuit device, comprising: the semiconductor substrate and the fourth semiconductor layer connected to each other.