JP2518880B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a lateral bipolar transistor.
The present invention relates to a semiconductor integrated circuit including a transistor.

[Conventional technology]

 An example of a conventional semiconductor device is shown in FIGS.

In the figure, 1, 2, 3, and 6 are an emitter region, a collector region, a base contact region, and an isolation region between elements, respectively. When this lateral PNP transistor is used in a saturated state in terms of circuit configuration, the collector region 2, the N-type epitaxial layer 4, and the P ⁺ -type isolation region 6 are respectively used as an emitter, a base, and
The parasitic PNP transistor used as a collector becomes active and current leaks to the substrate.

Conventionally, in order to reduce the influence of the parasitic PNP transistor, the base concentration of the parasitic PNP transistor is increased and h _FE is lowered by surrounding the emitter region 1 and the collector region 2 with the N ⁺ type semiconductor region 9.

[Problems to be solved by the invention]

In the conventional semiconductor device described above, there is a drawback that the concentration of the N ⁺ type semiconductor region 9 is not uniform and becomes lower near the N ⁺ type buried layer 5 than the surface, and h _{FE of} the parasitic transistor is not sufficiently small. . Further, there is a drawback that the number of steps is large because a step for forming the N ⁺ type semiconductor region is required.

[Means for solving problems]

A semiconductor device of the present invention is partitioned by a first conductivity type isolation region selectively provided from the epitaxial layer surface of a chip including a first conductivity type semiconductor substrate and a second conductivity type epitaxial layer to the semiconductor substrate. A lateral type in which an emitter region, a collector region and a base contact region are formed in an element formation region having a second-conductivity-type high-concentration buried layer selectively provided near the interface between the semiconductor substrate and the epitaxial layer In a semiconductor device having a bipolar transistor, a first conductivity type semiconductor region selectively provided between the emitter region, the collector region, the base contact region and the isolation region from the surface of the epitaxial layer to the buried layer is provided. A base electrode having both a base contact region and a first conductivity type semiconductor region. Is that is equipped with a.
In this case, the base contact region and the first conductivity type semiconductor region may be arranged to be in contact with each other.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a pattern layout view showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor chip taken along a portion corresponding to the line AA 'in FIG.

In this embodiment, the semiconductor is partitioned by P ⁺ -type isolation regions 6 selectively provided from the surface of the epitaxial layer 4 of the chip including the P-type semiconductor substrate 8 made of silicon and the N-type epitaxial layer 4 to the semiconductor substrate 8. N ⁺ selectively provided near the interface between the substrate 8 and the epitaxial layer 4
In a semiconductor device having a lateral bipolar transistor in which an emitter region 1, a collector region 2 and a base contact region 3 are formed in an element forming region having a type buried layer 5, an emitter region 1, a collector region 2 and a base region are formed.
The P-type semiconductor region 7 is selectively provided between the surface of the epitaxial layer 4 and the buried layer 5 between the contact region 3 and the isolation region 6.

By adding the P-type semiconductor region 7, a high-concentration buried N ⁺ region, that is, the buried layer 5 is always present in the current furnace of the parasitic PNP transistor, so that h _{FE of the} parasitic PNP transistor can be surely lowered. it can. In this case, since the base contact region 3 is connected to the base electrode B of the lateral PNP transistor, it needs to be inside the P-type semiconductor region 7.

FIG. 3 is a sectional view of a semiconductor chip showing a modified example of this embodiment. When the epitaxial layer 4 is thick, it is composed of two regions, that is, a buried P ⁺ region 6b and an isolation region 6a in the element isolation region. . In this case, the P-type semiconductor region may be composed of two regions 7a and 7b formed in the same step as 6a and 6b.

Since the P-type semiconductor region can be formed in the same process as the isolation region, it is not necessary to add a special process to reduce the h _FE of the parasitic transistor.

〔The invention's effect〕

As described above, according to the present invention, by surrounding the emitter region and the collector region of the lateral bipolar transistor with the semiconductor region having the same conductivity type as the isolation region, the h _FE of the parasitic transistor can be lowered and its influence can be reduced. Further, since this semiconductor region can be formed in the same step as the isolation region, it can be manufactured in a smaller number of steps as compared with the conventional example, and there is also an effect of improving yield and performance.

[Brief description of drawings]

FIG. 1 is a pattern layout diagram showing an embodiment of the present invention, and FIG.
1 is a sectional view of a semiconductor chip taken along the line AA 'in FIG. 1, FIG. 3 is a sectional view of a semiconductor chip showing a modified example of one embodiment, and FIG. 4 is a pattern arrangement showing a conventional example. 5 and 5 are cross-sectional views of the semiconductor chip taken along the line AA 'portion of FIG. 1 ... Emitter region, 2 ... Collector region, 3 ... Base contact region, 4 ... N-type epitaxial layer, 5
... N ⁺ type buried layer, 6 ... P ⁺ type isolation region, 7 ... P type semiconductor region, 8 ... P type semiconductor substrate, B ... base electrode,
C: collector electrode, E: emitter electrode.

Claims (2)

(57) [Claims] 1. A semiconductor comprising a semiconductor substrate of a first conductivity type and an epitaxial layer of a second conductivity type, the semiconductor being partitioned by a first conductivity type isolation region selectively provided from the surface of the epitaxial layer to the semiconductor substrate. A lateral bipolar transistor formed by forming an emitter region, a collector region, and a base contact region in an element formation region having a substrate, the interface between the epitaxial layer, and a second-conductivity-type high-concentration buried layer selectively provided near the interface. A semiconductor device having a transistor has a first conductivity type semiconductor region selectively provided between the emitter region, the collector region, the base contact region and the isolation region from the surface of the epitaxial layer to the buried layer. A base electrode connected to both the base contact region and the first conductivity type semiconductor region Wherein a Rukoto. 2. The semiconductor device according to claim 1, wherein the base contact region and the first conductivity type semiconductor region are in contact with each other.