JP2518929B2 - Bipolar semiconductor integrated circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a bipolar semiconductor integrated circuit, and in particular,
The present invention relates to a bipolar semiconductor integrated circuit having means for connecting a semiconductor substrate to the lowest potential.

[Prior Art] Conventionally, this type of bipolar semiconductor integrated circuit has been used in a circuit that requires high breakdown voltage, such as a subscriber circuit for an electronic exchange. Separated from each other.

FIG. 3 is a schematic diagram showing a planar arrangement of a conventional bipolar semiconductor integrated circuit, and FIG. 4 is a vertical sectional view taken along the line BB of FIG.

As shown in FIGS. 3 and 4, a buried region 2 is formed in the element formation region on the surface of the P-type semiconductor substrate 1 by selectively introducing antimony, for example. Then, the N type epitaxial layer 3 (lower layer) is formed by epitaxially growing on the surface of the P type semiconductor substrate 1. The buried region 7 is arranged in the epitaxial layer 3 so as to surround the element forming region in a strip shape. The buried region 7 is formed by selectively diffusing boron, which is a P-type impurity. After that, the epitaxial layer 3 (upper layer) is formed over the entire surface of the semiconductor substrate by epitaxial growth again. Insulation area 8
Is formed by diffusing boron on the surface of the epitaxial layer 3 excluding the element formation region. Since the insulating region 8 is formed to a depth reaching the boron burying region 7, the element forming regions arranged in the upper and lower epitaxial layers 3 are insulated from each other by the insulating region 8 and the burying region 7. To be separated.

On the other hand, the P type diffusion region 5 and the N ⁺ type diffusion region 4 are selectively formed on the surface of the epitaxial region 3 immediately above the buried region 2, and the P type diffusion region 5 and the N ⁺ type diffusion region 4 are They are the base region and the collector region of the transistor, respectively.
The N ⁺ type diffusion region 6 is selectively formed on the substrate surface in the P type diffusion region 5 and serves as an emitter region of the transistor.

The insulating film 12 is formed by being deposited on the entire surface of the P-type semiconductor substrate 1. The sub-contact portion 10 is provided by selectively opening the insulating film 12 on the substantially central portion of the insulating region 8. The wiring 9 is formed by being deposited on the substrate so as to fill the opening portion. There is. Further, predetermined electrodes are respectively formed in the base region (P type diffusion region 5), collector region (N ⁺ type diffusion region 4) and emitter region (N ⁺ type diffusion region 6) of the plurality of NPN transistors thus formed. A bipolar semiconductor integrated circuit is completed by connecting.

In the conventional bipolar semiconductor integrated circuit having such a structure, by applying a predetermined minimum potential to the sub-contact portion 10, the P-type semiconductor substrate is formed through the insulating region 8 and the buried region 7 into which boron is introduced. 1 is not held at the lowest potential.

[Problems to be Solved by the Invention] However, in the above-described conventional bipolar semiconductor integrated circuit, as shown in FIG. 4, the epitaxial layer 3 is formed immediately below the insulating region 8 connected to the sub-contact portion 10. Since the sub-contact portion 10 is formed, the potential applied to the sub-contact portion 10 is a P-type semiconductor in the insulating region 8 from the edge of the insulating region 8 via the embedded region 7 with the potential application path in a direction parallel to the substrate surface. It is applied to the substrate 1. For this reason,
A voltage drop occurs in the insulating region 8 between the sub-contact portion 10 and the P-type semiconductor substrate 1 due to the resistance of the insulating region 8. As a result, the bipolar semiconductor integrated circuit is easily affected by noise, which may cause latch-up. Particularly, when latch-up occurs in the bipolar semiconductor integrated circuit, there is a problem that the device is destroyed.

In addition, in order to prevent the above voltage drop, the insulating region 8
It is conceivable that boron may be diffused into the epitaxial layer 3 immediately below to reduce the resistance between the sub-contact portion 10 and the P-type semiconductor substrate 1. However, in this case, since the buried region 7 in the wafer is enlarged, boron is doped in the element region in the epitaxial growth process. Then, the resistivity of the epitaxial layer 3 fluctuates, and P-type boron is diffused in the N-type buried region 2, so that the collector saturation resistance (RCS) increases and good transistor characteristics are obtained. There is a problem that you cannot do it.

The present invention has been made in view of the above problems, and is capable of suppressing voltage drop between the sub-contact portion and the semiconductor substrate, preventing noise and latch-up, and maintaining excellent characteristics. Type semiconductor integrated circuit.

[Means for Solving the Problems] In a bipolar semiconductor integrated circuit according to the present invention, a plurality of element regions formed on the surface of a semiconductor substrate and an element formed on the surface of the semiconductor substrate and separating the element regions from each other are separated. An isolation region and a sub-contact portion locally formed on the semiconductor substrate surface of the element isolation region, the element isolation region is an insulating region on the semiconductor substrate surface side and below the insulating region. Contacting the insulating region and the semiconductor substrate at a position sandwiched by a plurality of element isolation embedded regions surrounding the element formation region and the element isolation embedded region immediately below the sub-contact portion. And a buried region for deriving the substrate potential.

[Operation] In the present invention, the sub-contact portion and the semiconductor substrate are electrically connected to each other at the shortest distance by the insulating region and the embedded region for deriving the substrate potential. Therefore, when a predetermined potential is applied to the sub contact portion to fix the semiconductor substrate to the minimum potential, a voltage drop is suppressed between the sub contact portion and the semiconductor substrate. As a result, the bipolar semiconductor integrated circuit can be suppressed from being affected by noise, and latch-up can be prevented.

Further, since the substrate potential deriving buried region is selectively formed immediately below the sub-contact, impurities in the substrate potential deriving buried region must be diffused into the element region during the wafer manufacturing process. There is no. Therefore, even if the buried region for deriving the substrate potential is formed in the semiconductor substrate, the semiconductor characteristics are not deteriorated.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a schematic view showing the planar arrangement of a bipolar semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is its A- line.
It is a longitudinal cross-sectional view in the A line. 1 and 2, the same components as those in Figs. 3 and 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 1, in the epitaxial layer 3 sandwiched between the insulating region 8 immediately below the contact portion 10 and the P-type semiconductor substrate 1, boron is locally formed at the same time when the buried region 7 is formed. The embedded region 11 is formed by the introduction. The buried region 11 is the insulating region 8 and the P-type semiconductor substrate 1.
And is electrically connected to both of them, and is a buried region for deriving the substrate potential. Further, as shown in FIG. 1, the buried region 11 is formed in parallel with the contact portion 10 and in the region directly below the contact portion 10 along the longitudinal direction thereof.

In the bipolar semiconductor integrated circuit of the present embodiment having such a configuration, when a voltage is applied to the contact portion 10 to fix the P-type semiconductor substrate 1 to the minimum voltage, the contact portion 10 and the P-type semiconductor substrate 1 are Since and are connected by the shortest path through the insulating region 8 and the substrate potential deriving embedded region 11, the series resistance between them is reduced. Therefore, since no voltage drop occurs between the sub-contact portion 10 and the P-type semiconductor substrate 1, the bipolar semiconductor integrated circuit functions stably without causing latch-up.

As described above, according to the present invention, since the embedded region for deriving the substrate potential is formed immediately below the sub-contact portion,
The sub-contact portion for fixing the potential of the semiconductor substrate and the semiconductor substrate can be connected at the shortest distance by the embedded region for deriving the substrate potential. Therefore, since the series resistance between the sub-contact portion and the semiconductor substrate can be reduced, it is possible to prevent a voltage drop between them. As a result, the present invention has an effect that the influence of noise of the bipolar semiconductor integrated circuit can be reduced and the occurrence of latch-up can be prevented.

[Brief description of drawings]

FIG. 1 is a schematic view showing a planar arrangement of a bipolar semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a line A- in FIG.
FIG. 3 is a schematic cross-sectional view taken along line A, FIG. 3 is a schematic view showing a planar arrangement of a conventional bipolar semiconductor integrated circuit, and FIG.
It is a longitudinal cross-sectional view in the BB line of a figure. 1; P-type semiconductor substrate, 2, 7, 11; buried region, 3; epitaxial layer, 4, 6; N ⁺ type diffusion region, 5; P-type diffusion region, 8; insulating region,
9: Wiring, 10: Sub-contact part, 12: Insulating film

Claims (1)

(57) [Claims] 1. A plurality of element regions formed on the surface of a semiconductor substrate, element isolation regions formed on the surface of the semiconductor substrate to isolate the element regions from each other, and the element isolation regions are locally formed on the surface of the semiconductor substrate. And a plurality of element-embedding burieds surrounding the element-forming region under the insulating region. A region, and a buried region for deriving a substrate potential, which is formed in contact with the insulating region and the semiconductor substrate at a position sandwiched by the buried region for element isolation immediately below the sub-contact portion. A bipolar semiconductor integrated circuit characterized by the following.