JPH02285655A - Junction isolated structure of integrated circuit device - Google Patents

Abstract

PURPOSE:To restrict the conduction of a parasitic transistor formed between adjacent semiconductor regions as well as between the mutual isolation layers thereby enabling the interference between circuit elements formed in both semiconductor regions to be effectively prevented by a method wherein the diffusion layer of a buried isolation layer is expanded toward the lower side of at least one semiconductor region. CONSTITUTION:The other conductivity type epitaxial layer 4 deposited on one conductivity type substrate 1 is junction-isolated from the substrate 1 into multiple semiconductor regions 4t, 4d to form circuit elements for respective integrated circuit by one conductivity type isolation layers 3, 5. In such a constitution, the isolation layers 3, 5 are composed of a buried isolation layer 3 diffused in lower side of the epitaxial layer 4 and a surface isolation layer 5 diffused from the surface of the epitaxial layer 4 so that the diffusion width of the buried isolation layer 3 between the adjacent semiconductor regions 4t, 4d may be expanded toward the lower side of at least one semiconductor region from the diffusion width of the surface isolation layer 5. For example, the buried isolation layer 3 in the lower side of the semiconductor region 4d for substrate diode D is diffused wider than the surface isolation layer 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a junction isolation structure for preventing interference between circuit elements of an integrated circuit device, and in particular a junction isolation structure for preventing interference between circuit elements of an integrated circuit device. The present invention relates to a junction separation structure suitable for driving.

[Conventional technology]

As is well known, in an integrated circuit device, in order to prevent operational interference between the circuit elements that make up the device, the epitaxial layer is separated into a plurality of semiconductor regions that are electrically floating above the substrate. Generally, element groups are divided into these semiconductor regions and manufactured.

This potential separation has the drawback that although the insulation isolation structure is the most perfect, it tends to be expensive.
A junction isolation structure using a junction, that is, an epitaxial layer of one conductivity type, e.g., P type, grown on a substrate of the other conductivity type, e.g., N type, by a separation layer of one conductivity type, e.g. A structure is adopted in which circuit elements or circuit element groups are separated into a plurality of semiconductor regions in which they are to be fabricated. Although the present invention relates to such a junction separation structure, which is well known, the prior art will be briefly explained below with reference to the example shown in FIG.

In FIG. 2, the substrate 1 is of the p-type, on which an n-type epitaxial layer 4 is grown, with a p-type separation layer forming a semiconductor region 4 for a bipolar transistor T in the illustrated example.
t and a semiconductor region 4d for diode D. As usual, a strong n layer is formed under the semiconductor region @41 for the transistor prior to the growth of the epitaxial layer 4.
A buried layer 2 of the shape is prediffused into the substrate l. Also,
In this example, the separation layer has a composite structure consisting of a strong p-type buried separation layer 3 and a surface separation layer 5, of which the buried separation layer 3 is diffused before the growth of the epitaxial layer 4. The surface isolation layer 5 is then diffused from its surface after epitaxial growth.

The transistor T is of the npn type in this example, and is built within an n-type semiconductor region 4 using it as a collector region, and is formed with an n-type collector all layer 6. p-type base layer7. It has an n-type emitter layer 9 and a strong n-type collector connection layer 10, and is connected to them to form a collector C,
Terminals for base B and emitter E are led out as shown.

In this example, the diode D has a p-type substrate 1. Buried isolation layer 3, surface isolation layer 5, and n-type semiconductor region 4d
This is a so-called substrate diode that utilizes a pn junction between the two, and its negative terminal N is led out from a strong n-type diode connection layer 11. P-type surface separation layer 5 in the center of the figure
A ground connection layer 8 is diffused in strong p-type and a ground terminal G is derived from it. Note that this ground terminal G also serves as the substrate diode DOP side terminal.

In the integrated circuit device having the above structure, both the p-type surface isolation layer 5 and the buried isolation layer 3 are connected via the ground terminal G as usual.
and substrate 1 are placed at ground potential, and a positive voltage is applied to n-type semiconductor regions 4t and 4d. Semiconductor regions can also operate under mutually independent potentials while floating in potential from the substrate.
Therefore, interference between circuit elements built therein can be avoided. As is well known, this is the principle of the junction isolation structure.

Note that the buried isolation layer 3 with a large area shown on the right side of FIG.
The surface separation layer 5 is a region for a so-called scribe line when a chip of a micro-integrated circuit device is isolated from a wafer, and normally this region is used for connecting pads P for connecting the chip to the outside. are provided as shown in the figure.

Further, the remaining structure in FIG. 2 will be explained later with reference to FIG. 1.

[Problem to be solved by the invention]

In the junction isolation structure described above, mutual interference does not occur between the semiconductor regions separated into multiple parts by the isolation layer under normal conditions, but under certain conditions the semiconductor regions become electrically conductive and the role of interference prevention is You may not be able to fulfill your goals.

This is because a separation layer of the opposite conductivity type is interposed between adjacent semiconductor regions, so as shown in FIG. This is because an npn type parasitic transistor t is formed in the transistor t, which may become conductive for some reason.

For example, if the transistor T in Figure 2 is driving an external load and the substrate diode D is used for freewheeling to discharge the capacitance or inductance of this load, there will be a considerable amount of free wheeling during operation. Since the wheeling current flows through the diode D in the forward direction, from the ground terminal G to the negative terminal N of the diode in Figure 2, the current flows from the base to the emitter of the parasitic transistor t in the figure. is injected, and the parasitic transistor t becomes easily conductive due to such forced and injected base current from the outside.

In order to prevent the parasitic transistor t from becoming conductive, it is necessary to lower its current amplification factor, and a conventionally known means for this purpose is to lower its base resistance. The base resistance in this case is the substrate 1.0 that forms the base of the parasitic transistor. Since it is almost determined by the resistance within the substrate 1, which has the highest specific resistance among the buried separation layer 3 and the surface separation layer 5, the resistance of the substrate 1
The most effective method is to increase the impurity concentration.

However, with this solution, the breakdown voltage value of the transistor T inevitably decreases due to the integrated circuit device. In other words, as can be seen from FIG. Since it is almost determined by the pn junction between the p-type substrate 1 and the p-type substrate 1, if the impurity concentration is increased to the level of the substrate in which the depletion layer tends to extend from this junction, the withstand voltage value of the transistor T will decrease.

The present invention solves these problems and suppresses the conduction of parasitic transistors formed between two adjacent semiconductor heads and the separation layer between them, and is formed in an asymmetric conductor region. An object of the present invention is to obtain a junction separation structure for an integrated circuit device that can effectively prevent interference between integrated circuit elements.

[Means for Solving the Problems] The object of the present invention is to make the separation layer have a composite structure, and to make the diffusion width of the buried separation layer between two adjacent semiconductor regions smaller than the diffusion width of the surface separation layer. This is also achieved by expanding downwards in at least one of the semiconductor regions.

Note that when one of the two semiconductor regions in the above structure is for a substrate transistor, it is advantageous to widen the diffusion width of the buried isolation layer toward this region, and the space above the semiconductor region for the substrate transistor is It is particularly advantageous to arrange the connection pads to the outside of the integrated circuit by means of .

[Effect]

Conventionally, the base resistance of the parasitic transistor was reduced in order to reduce its effect, but the present invention focuses on the fact that the current amplification factor of the transistor is inversely proportional to the square of its base width. The base width of the parasitic transistor is increased by making the diffusion width of the buried isolation layer between two adjacent semiconductor regions wider than the diffusion width of the surface isolation layer toward the bottom of at least one of the semiconductor regions. This reduces the current amplification factor. As a result, even if a large base current is injected, the parasitic transistor does not easily become conductive, and the possibility of mutual interference between circuit elements built in the bidirectional conductor region can be significantly reduced.

〔Example〕

FIG. 1 shows an embodiment of a junction separation structure according to the present invention. This figure shows an example in which the structure of the present invention is applied to an integrated circuit device portion in which a transistor T and a substrate diode D are formed, as in the conventional example shown in FIG. Connection pads P are arranged using the space. Note that portions in FIG. 1 that correspond to those in FIG. 2 are given the same reference numerals.

The p-type substrate 1 has an impurity concentration of 1015 atoms/afl
A strong n-type buried layer 2 and a strong p-type buried isolation layer 3 are first diffused into a predetermined range of the surface. It is best to use arsenic, which has a low diffusion rate, as the impurity for the buried layer 2, and boron, which has a high diffusion rate, for the buried isolation layer 3, and their concentration is 10'8 atoms in the case of buried N2. /ci, for example, 1019 atoms/cJ in the buried isolation layer 3. Semiconductor region 4 for substrate diode D
According to the invention, the buried isolation layer 3 lying below d is diffused much wider than the surface isolation layer 5, as shown in the figure.

In this example, since the integrated circuit device is for high breakdown voltage, an n-type epitaxial layer 4 is grown on this substrate 1 to a thickness of about 15 Ω or more with a relatively high resistivity of, for example, about 5 Ωcm, and from its surface, a strong p-type The surface separation layer 5 of 10'8 atoms/C
In this example, the epitaxial layer 4 is junction-separated from the substrate 1 by deeply diffusing with an impurity concentration of about 11 and conductively fusing with the buried isolation layer 3 rising from below as shown in the figure. It is separated into semiconductor regions 4t and 4d.

Semiconductor region 4t for bipolar transistor T among these
As is customary, the strong n-type collector all layer 6 is deeply diffused from the surface using impurities such as phosphorus with a high diffusion rate so as to fuse with the buried layer 2 at a concentration of about 1018 atoms/ctA. Ru.

The transistor T in this example is of the npn type, and the p-type base layer 7 from the surface of the n-type semiconductor region 4t serving as the collector region has a relatively high impurity concentration of about 10I11 atoms/C-, for example about 3- Using this process, an n-type ground connection layer 8 is formed on the surface of the surface isolation layer 5.
are simultaneously diffused.

Similarly, the emitter layer 9 and collector connection layer 10 for the transistor T and the diode connection layer 11 for the substrate diode D are all simultaneously diffused with strong n-type, and their impurity concentration is, for example, 1020 atoms/cJ and the depth is 2IIfn. It is considered to be a degree.

The surface of the wafer on which each of the above diffusion layers is formed is covered with an oxide film 21 as usual, but in this example, the surface isolation layer 5 and the semiconductor regions 4t and 4d are used to increase the breakdown voltage of the integrated circuit device. A so-called field plate 30 is formed of polycrystalline silicon or the like on the oxide film 21 on the bonding surface between the two to prevent a drop in breakdown voltage at the bonding surface. After depositing an oxide film 22, which is a so-called glabellar insulating film, on the field plate 30, a connecting film 40 made of aluminum or the like is brought into conductive contact with a predetermined semiconductor layer through a window opened in the oxide film 22, and the collector C of the transistor T is , terminals for base B and emitter E, etc. Note that the field plate 30 is connected as shown to a connection film 40 for the ground terminal G that is in conductive contact with the ground connection layer 8, and is placed at the ground potential as usual.

As can be seen from a comparison with FIG. 2, the semiconductor region 4d for the substrate diode D in this example is formed to be considerably wider than the conventional one, and since the connection pad P is formed using the top of the semiconductor region 4d, the above-mentioned A connecting film 40 is formed to a desired size and brought into conductive contact with the underlying diode connecting layer 11 to form a second connection film 40.
It is shared with the negative terminal N of the diode T in the figure. Next, as usual, the connection film 40 is covered with a protective film 2 such as silicon nitride.
A connection pad P is formed as shown in the figure by the connection film 40 exposed through the window 23a, which is normally used as a load terminal.

Even in the junction isolation structure of this embodiment configured as described above, the n-type amphibic conductor regions 4t and 4d and the p-type substrate 1
．． A parasitic transistor t is formed between the buried isolation layer 3 and the surface isolation layer 5 as shown in the figure, but the width of the buried isolation layer 3 is wider toward the semiconductor region 4d than the surface isolation layer 5. Therefore, the length of the substrate 1 in the left-right direction in the figure, which substantially increases the base width, becomes larger than that in FIG. 2, and therefore the current amplification factor is significantly reduced compared to the conventional one.

To explain this using a numerical example, in the conventional structure shown in FIG. ! It will be about m wide. On the other hand, the first
In the example structure shown in the figure, the width of the surface isolation layer 5 is the same as the conventional one, but the width of the buried isolation layer 3 can be easily increased by about 100 pa using the space below the connection pad P. obtain.

Therefore, the base width of the parasitic transistor was conventionally about 30 mm, and its current amplification factor was usually about 0.2, but in this embodiment, the base width is about 130 Im, or 4 to 5 times that of the conventional one. As mentioned above, the current amplification factor is approximately inversely proportional to the square of the base width, so it is approximately 0.01
In other words, it is reduced to about one-twentieth of the conventional level. As a result, with respect to the conduction of the parasitic transistor due to the above-mentioned freewheeling current injected from the ground terminal G toward the connection pad P in the example of FIG. It can be made resistant to

In addition, in this embodiment, only the width of the buried isolation layer 3 can be increased while keeping the width of the surface isolation layer 5 exactly the same as in the conventional one, so that the above-mentioned forced isolation layer 3 can be increased without increasing the chi/knob size of the integrated circuit device. This has the advantage that the injection current withstand capacity can be improved.

Furthermore, as can be seen from the above description, the structure of the present invention does not require increasing the impurity concentration of the substrate 1, which is advantageous in increasing the withstand voltage of the integrated circuit device. For example, the structure of the embodiment shown in FIG. 1 can easily provide a breakdown voltage of 100 V or more.

The present invention is not limited to the above embodiments, and the present invention can be implemented in various embodiments. In the embodiments, the explanation has been limited to preventing interference between the semiconductor region for a transistor and the semiconductor region for a substrate diode, but the present invention can also be practiced between semiconductor regions for other circuit elements as appropriate within the scope of the invention. The above-mentioned effects can be obtained. At this time, it is necessary to increase the mutual distance between the semiconductor regions to widen the width of the buried isolation layer, but the forced injection current withstand capability can be improved by about one order of magnitude without particularly increasing the chip size.

〔Effect of the invention〕

As described above, in the junction separation structure of the integrated circuit device according to the present invention, the epitaxial layer of one conductivity type grown on the substrate of the other conductivity type is separated by the separation layer of one conductivity type to form circuit elements for the integrated circuit. When separating junctions from the substrate into multiple semiconductor regions to be fabricated, the separation layer is composed of a buried separation layer diffused under the epitaxial layer and a surface separation layer diffused from the surface of the epitaxial layer. , by widening the diffusion width of the buried isolation layer between the two adjacent semiconductor regions toward the bottom of at least one of the semiconductor regions than the diffusion width of the surface isolation layer. By increasing the effective base width of the parasitic transistor formed by the isolation layer interposed therebetween, the current amplification factor thereof is significantly reduced, and the withstand capability against the forced injection current caused by this parasitic transistor to conduct is improved by more than one order of magnitude. Interference between circuit elements or circuit element groups of an integrated circuit device built in the bidirectional conductor region can be effectively prevented.

Further, even if such interference does not occur, the present invention can reduce the possibility that unnecessary current consumption will occur within the chip of the integrated circuit device due to conduction of the parasitic transistor.

Furthermore, according to an advantageous embodiment of the invention, the buried isolation layer extends below the semiconductor area for the substrate diode, and the connection pads to the outside of the integrated circuit are arranged on this semiconductor area. (It is possible to improve the effects of preventing interference and reducing current consumption without increasing the current consumption at all.

The present invention is particularly advantageous in application to high-voltage integrated circuit devices and BiMO3 integrated circuit devices that directly drive capacitive or inductive loads, and has the remarkable effect of significantly improving the operational reliability thereof. can.

[Brief explanation of drawings]

FIG. 1 is an enlarged cross-sectional view of a main part of an integrated circuit device chip illustrating a junction isolation structure according to the present invention. FIG. 2 is an enlarged sectional view of a main part of an integrated circuit device chip corresponding to FIG. 1 showing an example of a conventional junction isolation structure. In the figure, 1: substrate, 2: buried layer, 3: buried isolation layer, 4: epitaxial layer, 4d: semiconductor region for substrate diode, 4t
: semiconductor region for transistor, 5: surface isolation layer, 6:
Collector all layer, 7: base layer, 8: ground connection layer,
9: Emitter layer, 10: Collector connection layer, 11: Diode connection layer, 21: Oxide film, 22 Dioxide film or glabellar insulating film, 23: Protective film, 23a: Window for connection pad in protective film, 30: Field plate, 40: Connection film, B: Base terminal, C: Collector terminal, D: Diode or substrate diode, E: Emitter terminal, G: Ground terminal, N: Negative side terminal of diode, P: Connection pad, T: Transistor, t : A parasitic transistor.

Claims (1)

[Claims] A structure in which an epitaxial layer of one conductivity type grown on a substrate of one conductivity type is bonded and separated from the substrate by a separation layer of one conductivity type into a plurality of semiconductor regions in which circuit elements for an integrated circuit are to be fabricated, respectively. The isolation layer is composed of a buried isolation layer diffused under the epitaxial layer and a surface isolation layer diffused from the surface of the epitaxial layer, and the buried isolation layer is formed between two adjacent semiconductor regions. A junction isolation structure for an integrated circuit device, characterized in that the diffusion width of the surface isolation layer is made wider toward the lower side of at least one semiconductor region than the diffusion width of the surface isolation layer.