JPS6118344B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device including a capacitive element.

In semiconductor integrated circuits, especially linear integrated circuits, it is often necessary to incorporate capacitors as circuit elements.

By the way, as capacitors built into semiconductor integrated circuits, MOS capacitors using a silicon oxide film or junction capacitors of PN junctions have been known.

Figure 1 shows a conventional semiconductor integrated circuit device.
1 is a cross-sectional view showing the structure of a PN junction capacitive element, in which 1 is a P-type silicon substrate, 2 is a P ⁺ type isolation diffusion region 3 epitaxially grown on this substrate;
An N-type island region 4 formed into an island shape by is selectively embedded between the substrate 1 and the epitaxial region 2.
It is an N ⁺ type buried diffusion region. 5 is a P-type diffusion region that is formed in the N-type island region 2 at the same time as the base diffusion of the transistor, and 6 is a P-type diffusion region that is formed in the P-type diffusion region 55 at the same time as the emitter of the transistor.
The N ⁺ type diffusion region 7 is also a contact area formed in the N type island region 2 at the same time as the emitter diffusion.
N ⁺ type diffusion region, and 8 a silicon oxide film,
Reference numerals 9, 10, and 11 designate conductors that are in ohmic contact with the N-type island region 2, P-type diffusion region 5, and N ⁺ type diffusion region 6, and serve as electrodes of the junction capacitance element.

In such a structure, if the electrodes 9 and 10 are used, the bonding surface 12 will act as a capacitor, if the electrodes 10 and 11 are used, the bonding surface 13 will act as a capacitor, and if the electrode 9 and the silicon substrate 1 are used, the bonding surface 13 will act as a capacitor, and if the electrode 9 and the silicon substrate 1 are used, the bonding surface 12 will act as a capacitor. The junction surface 14 between the N ⁺ type buried diffusion region 4 mainly serves as a capacitor. Usually, one or more of these junction surfaces are used as a capacitor.

Figure 2 shows a conventional semiconductor integrated circuit device.
This is a cross-sectional view showing another example of a PN junction capacitive element.
This is a diagram showing the structure of a known example of improving the structure shown in the figure (Japanese Patent Application No. 44416/1986). The difference from FIG. 1 is that a P + type diffusion region 15 is formed at the same time as the P ⁺ type isolation diffusion region 3 at the position of the P ^type diffusion region 5 which is formed at the same time as the base diffusion of the transistor. . In this case P ⁺ type diffusion region 15
A junction surface 16 formed by the N ⁺ type buried diffusion region 4 serves as a capacitor similar to the junction surface 12 in FIG. The junction surface 16 forms the junction surface 12 in FIG. 1 with the impurity concentration of the P ⁺ type diffusion region 15 and the N ⁺ type buried diffusion region 4 on both sides thereof being about 3×10 ¹⁶ 1/cm ³ . P-type diffusion region 5 and N-type island region 2
Because it is higher than the impurity concentration (=5×10 ¹⁵ ),
The capacitance per unit area is approximately twice that of the bonding surface 12. However, in the structures of FIGS. 1 and 2, when the capacitance of the bonding surfaces 13 and 12 or the bonding surfaces 16 and 17 is used for parallel connection, most of the capacitance depends on the bonding surfaces 13 and 17, respectively. Therefore, the structure in Figure 2 is 10% to 20% lower than the structure in Figure 1.
It can only provide a relatively large capacity.

Conventionally, capacitance has been built into semiconductor integrated circuits using these structures, but with such structures, the capacitance per unit area is small and the number of
Even when creating a capacitance comparable to that of a PF, it occupies a considerable amount of area on a semiconductor chip.

The present invention has been made in view of the problem with the conventional structure, that is, the small capacity per unit area, and it is an object of the present invention to provide a structure that can increase the capacity per unit area.

The present invention will be described below based on the structures of FIGS. 3, 4, and 5 according to embodiments of the present invention.

FIG. 3 is a diagram showing an embodiment of the present invention, and 1, 2, and 4 are the same structural parts as the conventional one, but the following structure differs from the conventional one. That is, a P-type buried diffusion region 18 is formed between the N ⁺ type buried diffusion region 4 and the epitaxial region 2 as shown in the figure, and a P-type diffusion region 18 is formed from the surface of the epitaxial layer to the P-type buried diffusion region 18. A first diffusion region 19 is formed. Next, a P-type second diffusion region 20 is formed in the epitaxial region 2 at the same time as the base diffusion of the transistor, and the P-type second diffusion region 20 is further spread over three regions: the P-type first diffusion region 19, the P-type second diffusion region 20, and the epitaxial region 2. N ⁺
A mold diffusion region 21 is formed.

In this structure, the N ⁺ type buried diffusion region 4 epitaxial region 2 and the N ⁺ diffusion region 21 which are adjacent to each other correspond to one plate (positive side) of the PN junction capacitive element. On the other hand, the P-type buried diffusion region 18 and the epitaxial region 2 sandwiched between the N ⁺ type buried diffusion region 4 and the epitaxial region 2
The P-type second diffusion region 20 sandwiched between the N ⁺ type diffusion regions 21 corresponds to the other plate (minus side), and these are connected to each other by the P-type first diffusion region. The conductors 22 and 23 are in ohmic contact with the P type first diffusion region 19 and the N ⁺ type diffusion region 21, respectively.

According to this structure, the bonding surfaces 24, 25, 26 and 27 serve as capacitors. Moreover, the joint surface 24 is
Similar to the junction surface 13 and the junction surface 17 in the conventional structure shown in FIGS. 1 and 2, this is a junction surface between N-type and P-type with a high impurity concentration (=10 ¹⁷ 1/cm ³ ). In addition, the impurity concentration on the P-type side of the junction surface 27 is approximately 8×10 ¹⁷ 1/cm ³ , which is the same as the impurity concentration of 3×10 ¹⁶ 1/cm ³ in the case of the conventional junction surface 16 in FIG. Since it is higher than that, the capacity per unit area is
This is approximately 1.2×10 ⁵ PF/cm ³ , which is approximately twice as large as that of the conventional structure.

In this example, the breakdown voltage is the lowest, approximately
Since the 7V junction surface 24 is used as a capacitor, it cannot be used at a higher voltage.

FIG. 4 shows another embodiment of the present invention, which can also be used when a voltage of about 7V or more is applied between the terminals. In this case, the N ⁺ type diffusion region 28 is located only within the N type island region 2 and is used only as a contact.

Even in the conventional structure shown in FIGS. 1 and 2, if the voltage between the terminals exceeds 7V, the junction surface 13 and the junction surface 17 can no longer be used, and the capacitance of such a structure is 6×10 ^3PF / ^cm3 , 1.2×
It will be about 10 ⁴ PF/cm ³ . On the other hand, the capacity in this example is about 5×10 ⁴ PF/cm ³ , which is 4
or an increase of 8 times.

FIG. 5 is still another embodiment of the present invention, which is an application example where one electrode of the capacitive element has the lowest potential of the integrated circuit. Alternatively, the P-type buried diffusion region 18 and the P-type isolation buried diffusion region 30 may be directly connected.

In this embodiment, the bonding surface 31 also contributes to the capacitance, and the capacitance per unit area increases rapidly.

As explained above, according to the present invention, it is possible to obtain a semiconductor integrated circuit device having a PN junction capacitive element with a much larger capacitance per unit area than that of the conventional one, and therefore a semiconductor integrated circuit device with a much larger capacitance per unit area than the conventional one. Not only does this make it possible to increase the integration density of semiconductor integrated circuit devices, but it also has the effect of increasing the degree of integration of semiconductor integrated circuit devices, since the occupancy rate of the semiconductor chip by the capacitor part decreases when building the same capacitance as before. play.

[Brief explanation of the drawing]

Figure 1 shows a conventional semiconductor integrated circuit device.
FIG. 2 is a sectional view showing the structure of a PN junction capacitive element, FIG. 2 is a sectional view showing another example of a PN junction capacitive element in a conventional semiconductor integrated circuit, and FIG. FIG. 4 is a cross-sectional view showing another example, and FIG. 5 is a cross-sectional view showing still another example. 1...P type silicon substrate, 2...Epitaxially grown N type island region, 3...P ⁺ type isolation diffusion region,
4...N ⁺ type buried diffusion region, 5... P type diffusion region, 6
... N ⁺ type diffusion region, 7 ... N ⁺ type diffusion region, 8 ... silicon oxide film, 9, 10, 11 ... conductor, 12, 1
3, 14...Joint surface, 15...P ⁺ type diffusion region, 1
6, 17... Junction surface, 18... P-type buried diffusion region, 1
9... P type first diffusion region, 20... P type second diffusion region, 21... N ⁺ type diffusion region, 22, 23... conductor, 24, 25, 26, 27... bonding surface, 28...
N ⁺ type diffusion region, 29...P type isolation diffusion region, 30
...P-type isolated buried diffusion region, 31...junction surface.

Claims (1)

[Claims] 1 A second semiconductor substrate formed on a first conductivity type semiconductor substrate.
a conductive type epitaxial region; and the second epitaxial region embedded between the epitaxial region and the substrate.
a first buried region of a conductive type; a second buried region of the first conductive type buried between the first buried region and the epitaxial region; and a second buried region opposite to the second buried region. the first region of the first conductivity type formed on the surface portion of the epitaxial layer; 1. A semiconductor integrated circuit device comprising: a PN junction capacitive element configured to include a plurality of second regions of the first conductivity type connecting two buried regions and the first region.