TW454332B - Semiconductor device - Google Patents

Abstract

A kind of semiconductor device has the followings: a semiconductor layer 30, which has the first conduction type; the first unit module 10 with the first semiconductor region 12 and the contact region 14, in which both the first semiconductor region 12 and the contact region 14 have the first conduction type and are formed inside semiconductor layer 30; and the second unit module 20 with the second semiconductor region 22 and the contact region 24, in which both the second semiconductor region 22 and the contact region 24 have the second conduction type and are formed inside semiconductor layer 30. The first unit module 10 acts in coordination with the second unit module 20 so as to function as the diode device 100.

Description

454332 V. Description of the invention (!) [Technical field to which the invention belongs] The present invention relates to a listening room with a small occupation area = body device. In particular, the present invention relates to a semiconductor device including a polarizing element. Difficulty [Background Technology] In recent years, with the development of 翱 a CMOS circuits (system complementary LSIs with single-chip solutions, the analog CMOS circuit is used to manufacture analog electrical LSi). CM〇fj rose. The performance of the design circuit of the analog circuit using the ability of the CU08 process determines the performance of the 1 ^ 1, and the situation of the high-pole circuit is important in order to report as much as possible. In the design of high-performance analogues, such as changes in electric dust, remove noise or electrical circuits from digital circuit blocks. In addition, in order to reduce tf, a reference voltage circuit or a circuit affected by noise of the reference current unit is required to consume power, or in order to protect the internal circuit from external and corresponding voltages between the internal circuits. Voltage conversion circuit and so on. ~ π Fan, Changhu · Dan > " "η-« aphenetaη I The problem of noise. Therefore, inside l s i, a reference voltage circuit using a Zener diode is used instead of a reference voltage circuit using a band gap reference circuit. In the case of a CMOS LSI, from the viewpoint of manufacturing cost and the viewpoint that it can be manufactured using the same process as a digital circuit block, a band gap reference circuit including a diode using a PN junction of a MOS transistor is used. In order to make use of Zener diodes to construct a quasi-voltage circuit designed for high-performance analog circuits, the power supply voltage becomes high and there is a problem that noise occurs in the circuit. Therefore, within l $ I, instead of using Zener diodes, it is necessary to improve the accuracy of using analog diodes with excellent diode characteristics to become system LSIs. The accuracy of band-gap reference circuits is therefore 454332. 2. Description of the invention (2) Indispensable.

And 'requires the reduction of the area of the LSI's crystal chip, ^ requires the system to reduce the area of the si's crystal element to perform analog / digital miniaturization of LSI, but' is different from the digital circuit part which is easier to reduce, the analog circuit It is difficult to reduce the area of the analog circuit part because of the variation or temperature dependence. In order to reduce the die area of analog / digital mixed LSI, it is important to reduce the area of the analog circuit. Therefore, it is important to reduce the occupation area of the diode element provided in the analog circuit section.

The inventor in this case reviewed the structure of the diode element 1000 shown in FIG. 15. Fig. 15 (a) schematically shows the diode element 1 above 1000, and Fig. 15 (b) schematically shows the diode element 1 along the line b-b 'of Fig. 15 (a). 0 0 0 section. 〇 Diode element 1000 has a structure that can be easily manufactured using a CMOS process. 'Includes the p + diffusion region 122 formed in the center of the N-well region (NW) 130, and the oxidation of the device isolation region on the periphery of the p + diffusion region 122. A film (an oxide film for element separation) 132 and a diffusion region 112 surrounding the outer periphery of the oxide film 132 for the element separation region. In addition, a P-well region (PW) 136 is formed around the N-well region (ND0130), and a p + -diffusion is formed in the P 丼 region (PWM36 as the element separation region surrounding the N + -diffusion region 112 oxidizes the pancreas 132) Region 134. The P + diffusion region 12 2 and the diffusion region 112 form a 'M junction at the junction between the P + diffusion region 122 and the N-well region (Nff) 13 ′ in the N-well region 130. The p + -diffusion region 122 is formed. As the anode and the N + diffusion region 112 as the cathode, a diode can be formed. In the diode element 1000,

454332 V. Description of the invention (3) A pair of PN junctions constitute a diode. The larger the area of the pn junction (ie, the area of the bottom surface of the p + diffusion region 122), the larger the current capacity of the diode element 1000. Bigger. Unlike the N + diffusion region 112 or P + diffusion region 122, which has a relatively low resistance, the N well region 130 has a relatively high resistance, and a parasitic resistance 140 exists in the N well region 130. The parasitic resistance 140 is connected in series with a diode formed by the bottom surface of the P + diffusion region 122 and the PN junction of the N well region 130. Therefore, the parasitic resistance 140 of the N well region 130 causes a voltage drop in the diode. As a result, , So that the current capacity of the diode element 1 000 is reduced. Therefore, in order to design the diode element 1000 in order to obtain the required current capacity, it is decided to define the distance between the P + diffusion region size 122 of the P + diffusion region 122 and the size of the well region 130 (P + diffusion region). 122 and the distance between the N + diffusion region 112) 114, the layout design is performed. However, when it is designed to increase the current capacity of the diode element 1000, it is necessary to increase the size of the P + diffusion region 122 located at the center of the N-well region 130 from the center of the P + diffusion region 122 to The distance up to the N + diffusion region 112 becomes larger. As a result, the parasitic resistance 140 of the N-well region 130 becomes large. Since the parasitic resistance 140 reduces the current capacity of the diode element 1000, in order to obtain the required current capacity, it is necessary to further increase the size of the P + diffusion region 122, which as a result prevents the reduction of the area of the wafer. The larger the diode current (ID), the more significant the parasitic resistance 140 reduces the current capacity of the diode element 1000. Therefore, this phenomenon is particularly problematic in the case where a relatively large amount of current flows through the diode element 1000 whose P + diffusion region size 124 is fixed. The present invention was conceived in view of the above problems, and its main object is to provide a semiconductor including a diode device with high performance and a small occupied area.

454332 V. Description of the Invention (4) Device [Summary of Invention] The semiconductor device of the present invention has a semiconductor layer of the first conductivity type; and a conductor SC: a dagger unit: has a semi-electrical connection to the-conductivity type No. J: The semiconductor region and the contact region used to connect the semiconductor conductor & field and wiring. 3 of the "two" :::: single :: element 'has the first conductivity type in the It is electrically connected to the second semiconductor region of the first conductivity type and the contact region using the first unit single region and the wiring; it is used as m pieces. The 'first unit cell cooperative action' is functional and has less ΐf : The first unit unit is a plurality of -unit units- and the second unit unit of the two units defines a plurality of second units, and the first semiconductor region and the second semiconductor are defined: zone :: better. = The size and size of the design of the device are substantially the same. The minimum size allowed in m is 0. The first semiconductor region and the shape of each region are approximately square when viewed from the normal direction. OK. * First semiconductor, the first unit cell and the second unit It is better to arrange the checkered pattern in the semiconductor layer ^ ~ conductive type In one embodiment: the first unit cell and the second unit are already in the ~ 'conductive type

Page 7 454332 5. Description of the invention (5) The semiconductor layers are arranged at a predetermined distance from each other; the inter-cell area between the first unit cell and the second unit cell within the semiconductor layer of the first conductivity type A gate structure having at least an insulating layer formed on the cell region and a conductive layer formed on the insulating layer is formed thereon. In one embodiment, a gate wiring electrically connected to the gate structure is further included. In one embodiment, a plurality of the second unit cells are formed in the first semiconductor region of the first unit cell. In one embodiment, a semiconductor layer of the second conductivity type is further included, and the semiconductor layer of the first conductivity type is formed on the semiconductor layer of the second conductivity type. In one embodiment: the first unit cell formed in the semiconductor layer of the first conductivity type serves as a base, the second unit cell serves as an emitter, and the semiconductor layer of the second conductivity type serves as a collector. In one embodiment: the semiconductor layer of the second conductivity type is a semiconductor substrate; the semiconductor layer of the first conductivity type is a well region formed in the semiconductor substrate β. In an embodiment, the semiconductor layer is formed on an insulating layer. The first conductive type rich conductor layer. In one embodiment, the analog circuit portion and the digital circuit portion are further included. The diode element is formed in the analog circuit portion, and is manufactured by a CMOS process.

454332 V. Description of the invention (6) The analog circuit section and the digital circuit section. : The present invention is provided with a first unit cell and a second unit cell, and a lean element and a second unit cell are used to form a diode element. Therefore, since the first semiconductor region of the first conductivity type and the second semiconductor region of the second conductivity type of the second early unit are arranged close to each other, the distance between the anode and the cathode can be reduced. As a result, since the parasitic resistance of the semiconductor layer of the first conductivity type can be reduced, it is possible to provide a diode, a device, and an f-conductor device having high performance and a small occupied area. In the case where a plurality of first unit units and a plurality of first unit units are provided, increasing the PN junction area can increase the current capacity of the diode. In addition, in the case where the size of each of the first semiconductor region and the second semiconductor region is substantially the same as the minimum size allowed by the design rule, 'the distance between the anode and the cathode can be shortened more effectively, which is effective. Cut the parasitic resistance. It is also possible to minimize the size of the diode element, and as a result, it is possible to reduce the wafer area of the semiconductor device. When the shape of each of the first semiconductor region and the second semiconductor region is approximately square, the first and second unit cells can be arranged with the highest efficiency according to a predetermined design rule. In addition, when the first unit cell and the second soap position unit are arranged in a checkered pattern, the parasitic resistance of the semiconductor layer of the first conductivity type can be more effectively reduced. When a gate structure is formed on an inter-cell region between a first unit cell and a second unit cell 'Since it is not necessary to provide an element separation region oxide film between the first unit cell and the second unit cell, the second unit cell The periphery can also be used as a PN interface. Therefore, 'the PN junction area can be further increased without increasing the element area of the diode element. In the formation and gate structure

454332 V. Description of the invention (7) The voltage of the gate wiring connected randomly can change the structure of the diode element. In the case of the structure of a two-unit unit of a first unit, the first conductivity type can be reduced. In the case of the half-type semiconductor layer, for example, in the case of this second structure, if the first unit is used as the emitter, and the second unit is used as the first unit unit and the second unit. In this structure, it is also possible to increase the current capacity by reducing the resistance. The semiconductor layer can be used as a semiconductor or an insulating layer (or an insulating substrate). The structure using the first unit cell and element 'is, for example, formed in an analog circuit section. By applying and independent of the gate wiring. The first half is due to the shrinkable conductor, the conductive type potential unit, the electrical type potential unit, a conductive conductor area, and the short anode and cathode parasitic resistance. The semiconductor layer serves as a base, and the second semiconductor layer serves as a ferroelectric layer constituting a bipolar electric transistor. The second well of the first conductivity type is formed on the well formed in the bipolar substrate.

The bit cell is formed by using CMOS to form a plurality of first conductive spaces. At an early stage, the single-collector 'crystallizable element's parasitic electrical first conductive region. Semiconductor layer Diode element manufacturing process [Best embodiment of the invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following drawings, for the sake of simplicity, the same reference numerals are used to denote constituent elements having substantially the same function. ^

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS. The semiconductor device of this embodiment includes a semiconductor integrated circuit device, for example,

^ 454332 V. Description of the invention (8) —— * · Analog / digital mixed LSI produced by CMOS process. In the semiconductor device of this embodiment, a semiconductor integrated circuit includes a diode element 100 shown in Fig. 1. Fig. 1 (a) schematically shows the upper surface of the diode element 100, and Fig. 1 (a) schematically shows the cross section of the diode element 100 along line b_b of Fig. 1 (a). .

The diode element 100 includes a semiconductor layer 30 of a first conductivity type and first and second unit cells 10 and 20 formed in the semiconductor layer 30 of the first conductivity type. For example, it is an n-well region (NW) 30 formed in the p-type semiconductor substrate 60. In addition, the semiconductor layer 30 of the first conductivity type is not limited to the well region of the first conductivity type. The semiconductor substrate of the first conductivity type may also be a semiconductor of the first conductivity type formed on the semiconductor substrate of the second conductivity type. Layers are also available. In this embodiment, the N-well region 30 is used on the semiconductor layer of the first conductivity type, but a p-well region may be used instead.

The first unit cell 10 includes a first semiconducting region 12 of a first conductivity type formed in the N-well region 30 and a contact region 14 for electrically connecting the first semiconducting region 12 and the wiring 50. In this embodiment, the first semiconducting region 12 is an N + diffusion region 'and the N + diffusion region 12 is electrically connected to the wiring 50 via a contact portion 52 joined to a contact region 14 provided on a surface thereof. Further, the second unit cell 20 has a second semiconducting region 22 of a second conductivity type formed in the NZ region 30 and a contact region 24 for electrically connecting the first semiconducting region 12 and the wiring. In this embodiment, the “second semiconducting region 22 of the second conductivity type is a P + diffusion region” and the P + diffusion region 22 is electrically connected to the wiring 50 through a contact portion 52 joined to a contact region 24 provided on the surface thereof. In addition, in

Page 11 454332 V. Description of the invention (9) In the case of forming a P-well region on the semiconductor layer of the first isoelectric type, as long as the first semiconducting region 12 of the first conductivity type is used as the p + diffusion region, the second conductive type The second semiconducting region 22 of the type can be β as the N + diffusion region. In this embodiment, the first unit cell 10 and the second unit cell 20 are arranged at a predetermined interval (for example, about 2 m). In order to separate the first unit Cuiyuan 10 (N + diffusion region 12) and the second unit cell 20 (p + diffusion region), between the first unit cell 10 and the second unit unit 20 in the N-well region 30 The inter-cell region (element isolation region) forms an element isolation region oxide film (field oxide film) 32. Also, a p-well region (pff) 36 is formed around the N-well region 30. In the P-well region 36, for example, the periphery of the element separation region separating the first unit cell ι and the second unit cell 20 from the oxygen fc membrane 32 is surrounded. The p + diffusion region 34 is formed in general »N + of the first unit cell 10. The diffusion region 12 of the first unit cell 10 and the P + diffusion region 22 of the second unit cell 20 are formed in the N well region 30 using the p + diffusion region 22 and the N well. The region 30 forms a PN junction. Therefore, by setting the second unit cell 20 (p + diffusion region 22) as the anode and the first unit cell 10 (N + diffusion region 12) as the cathode, the diode can be functionally used as a diode. The diode element 100 of this embodiment is different from the above-mentioned diode element 10Q0 'because the first unit cell 10 and the second unit cell 20 are used to form a diode, compared with the diode element 1,000' The distance between the anode and the cathode is shortened. Therefore, the parasitic resistance 40 existing in the well region 30 can be reduced more than the structure of the diode element 1000. That is, since the first unit cell 10 and the second unit cell 20 can be arranged close to the N-well region 30, the distance that the current flows in the N-well region 30 having the parasitic resistance 40 can be shortened. As a result, the parasitic resistance 4 is reduced. .

Page 12 454332 V. Description of the invention (10) After reducing the parasitic resistance 40, increasing the diode current (ID) can also prevent the current capacity of the diode element 100 from being greatly reduced. A high performance diode device 100 with a large current capacity. In addition, the diode element 100 has a larger current capacity per unit area than that of the diode element 1000, and can be reduced in structure by 1 area. In this embodiment, a plurality of first unit cells 10 and a plurality of second unit cells 20 are formed in the N-well region 30. Therefore, the pn junction area can be increased, and the current capacity of the diode element can be increased. In the example shown in FIG. 1, four first unit units 10 and five second unit units 20 are arranged in a two-first (array) manner, but this is not limited. More first unit units 10 and 10 may also be provided. Second unit cell 20. In addition, the plurality of first unit cells 10 and the plurality of second unit cells 20 may not be all connected to the wiring 50. According to the characteristics of the required diode element, 'the number of unit cells (10 or 2) Connect the wiring 50. Therefore, since any number of unit cells can be used to set the desired diode characteristics, the advantage that the design of the diode element becomes easy can also be obtained. When the N + diffusion region 1 2 of the first unit cell 10 and the p + diffusion region 22 of the second unit cell 20 are formed with the smallest possible size, the distance between the anode and the cathode can be further shortened. As a result, the parasitic resistance can be effectively reduced. 40%. In addition, the size of the diode element 100 can also be reduced, which can also reduce the area of the wafer of the semiconductor device. Therefore, the N + diffusion region 12 and? The respective size of the + diffusion region 22 = size (for example, the length of the side of a square) is substantially the same as the minimum size allowed in the design rules. In this embodiment, ^ + diffusion region 12 and? + Diffusion area, the minimum size allowed in design rules is about 1.4 from m, so that 4 5 4 3 3 ^] Jade, invention description (11) ~ · ~ ---- stipulate N + diffusion area 12 and The size of each of the P + diffusion regions 22 is substantially the same as that of the P + diffusion regions 22, for example, about 2 μm. That is, it is considered to be set to the optimal (minimum) size after the rough process. The shapes seen from the substrate normal direction of the N + diffusion region 12 of the first unit cell 10 and the P + diffusion region 22 of the second unit cell 20 are, for example, squares. Because the shape of the N + diffusion region 12 and {^ diffusion region 22 is square ”, the first unit cell 10 and the second unit cell 20 can be arranged with the highest efficiency within a predetermined design rule. However, the shapes of the N + diffusion region ^ and the Bu diffusion region 22 need not be geometrically exact squares, as long as they have a substantially square shape. For example, the corners may be rounded or the lengths of the sides may not be exactly equal. The shape is not limited to a square. For example, the shape of each of the diffusion region 12 and the p + diffusion region 22 may be a regular hexagon like a honeycomb structure. In addition, the radon diffusion region 12 and? The shape of the + diffusion region 22 is circular or oval. 〇 'In this embodiment, the first unit unit 10 and the second unit unit 20 are arranged to interact with each other', for example, arranged in a checkered pattern (or, for example, chess pattern). When the unit cells 20 are arranged in a checkered pattern, since the distance between each of the first unit cells 10 and each of the second unit cells 20 can be shortened, a plurality of first unit cells 10 and a plurality of second unit cells are provided. In the case of the unit cell 2f, there is also an advantage that the parasitic resistance 40 can be made small. The right use of the structure of the diode element 100 can reduce the voltage drop caused by the parasitic resistance 40, which can greatly increase the current capacity per unit area. In addition, since the elbow diffusion region and the p + diffusion region, which are diodes, are each composed of the first unit cell 7010 and the second unit cell 20, the unit cell design can be used.

Page 14 454332 V. Description of the invention (12) --- Design circuit. Therefore, it is also possible to obtain the advantage of improving the simplicity when designing a diode having a desired characteristic (a desired characteristic). Therefore, the diode element 100 can be suitably used as an element of a band gap reference circuit in an analog circuit section, for example. Next, referring to Figs. 2 (a) to (e), a description will be given of a method of manufacturing a polar body το member 100 in this embodiment. The diode device 100 can be manufactured, for example, using a typical CMOS process, and using the same process as the digital circuit portion of a semiconductor integrated circuit. First, as shown in FIG. 2 (a), for example, after a p-type semiconductor substrate (such as a P-type silicon substrate) 60 is prepared, as shown in FIG. 2 (b), a part of the substrate 60 is selectively moved from the surface to a predetermined one. An oxide film 32 of the element isolation region is formed up to the depth »Next, as shown in FIG. 2 (c), an N-well region is formed on the semiconductor layer of the first conductivity type by, for example, an ion implantation method. At this stage, an N-well region is also formed. The p-well region 36 around 30 β is next. As shown in FIG. 2 (d), an N + diffusion region 12 (first unit cell 10) and a ρ + diffusion region are selectively formed in one of the N well regions 30. 22 (second unit unit 20). The diffusion region 12 and the ρ + diffusion region 22 may be formed by, for example, an ion implantation method. Next, as shown in FIG. 2 (e), after the insulating film 54 is deposited on the substrate 60, a contact hole is selectively formed in the insulating film 54. Next, wiring 50 (including the contact portion 52) is formed. The contact portion 52 of the wiring 50 is respectively connected to the contact area 12 of the first unit unit 2 and the contact area 22 of the second unit unit 20, and the first unit unit tgIO and the second unit unit 20 are each connected to the wiring unit 5. Electrically connected '45433i V. Description of the invention (13) Connected. In this way, a diode element 1 can be obtained. In the diode element 100, an element separation region oxide film 32 is formed in the region between the first unit cell 10 and the second unit cell 20, but the element separation region is not formed. As shown in FIGS. 3 (a) and 3 (b), the oxide film 32 may be a bipolar element 200 in which a gate structure 70 is formed on the inter-cell region. The gate structure 70 is composed of an insulating film (for example, a gate oxide film) 2 and a conductive layer (for example, a polysilicon layer) 74 formed thereon, and has a structure that can be manufactured using a typical CMOS process. ^ In the diode element 200 shown in FIG. 3, since the free-electrode structure 70 is provided on the inter-cell region, the element separation region oxide film 32 is not formed, and a structure in which the n + diffusion region 12 and the P + diffusion region 22 are separated can be adopted. . So. In addition to this? + In addition to the area of the bottom surface of the diffusion region 22 ', the area of the peripheral surface of the p + diffusion region 22 also contributes to the area of the PN junction, which can increase the area of the pn junction. In addition, since the gate structure 70 can be formed using a CMOS process, the gate structure 70 of the diode element 200 can be formed by using the same process as the analog circuit portion. In addition, a gate wiring (not shown in the figure) and a gate structure 70 located in the N-well region 30 may be electrically connected to the diode element 200 '. After the gate wiring is provided in the gate structure 70, if a high potential voltage (Vdd) is applied to the 配线 wiring with an independent potential, the reverse bias during the operation of the diode is difficult to function. Therefore, formation of a depleted layer can be prevented, and as a result, a reduction in the area of the PN junction can be suppressed. The diode device 200 can be fabricated using, for example, a typical CMOS process as shown in Figs. 4 (a) to (f). Further, in this example, a diode element 200 having a structure in which a gate wiring 56 is formed on the gate structure 70 is fabricated.

Page 16 454-332 V. Description of the invention (14) First, as shown in FIG. 4 (a), for example, after preparing a P-type semiconductor substrate (such as a P-shaped substrate) 60, as shown in FIG. 4 (b), A part of the substrate 60 selectively forms the element isolation region oxide film 32 from the surface to a predetermined depth. In addition, unlike the example shown in FIG. 2, since the gate structure 70 is formed in a later process (refer to FIG. 4 (d)), the oxide film 32 of the element separation region may not be formed in a portion that becomes the N-well region (Nff) 30. Next, as shown in FIG. 4 (c), an N 丼 region (NW) 30 is formed on the semiconductor layer of the first conductivity type by, for example, an ion implantation method. At this stage, a P-well region 36 located around the N-well region 30 is also formed. Next, as shown in FIG. 4 (d), a gate structure 7 is formed in a portion between the first unit cell 10 and the second unit cell 20 that becomes an inter-cell region. The gate structure 70 may be formed as follows, for example. First, an oxide film (e.g., silicon oxide (SiO2)) is deposited on the substrate 60, and then, for example, polysilicon is deposited thereon. Next, the two are selectively etched to form an interlayer oxide film (thickness: several nanometers) 72 and a conductive layer (multi-silicon gate, thickness: one hundred nanometers) 74. In this way, a gate structure 7 is formed in the inter-cell region. Secondly, as shown in FIG. 4 (e), the gate structure 70 is used as a part of the mask. 'N + diffusion is selectively formed in a part of the N-well region 30. Region 12 (first unit cell 10) and P + diffusion region 22 (first unit cell 20). Since the gate structure 70 is provided in the inter-cell region, the element isolation region oxide film 32 is not formed in the N-well region 30, and the N + diffusion region 12 and the P + diffusion region 22 are formed without damaging the diode characteristics. Next, as shown in FIG. 4 (), after the insulating film 54 is deposited on the substrate 60, a contact hole is selectively formed in the insulating film 54, and then a wiring 50 (including

Page 17 454332 V. Description of the invention (15) Contact portion 52) and gate wiring 56. The contact portion 52 of the wiring 50 is connected to the contact area 14 of the first unit cell 10 and the contact area 24 of the second unit cell, respectively. Further, the gate wiring 56 and the conductive layer 74 of the gate structure 70 are electrically connected to each other, and a diode element 200 can be obtained in this manner. Fig. 5 is a circuit for obtaining a voltage-current characteristic of the diode, and Fig. 6 shows a result of measuring the voltage-current characteristic of the diode using the circuit shown in Fig. 5. The vertical axis in FIG. 6 represents the current per unit area (logarithmic scale), and the horizontal axis represents the applied voltage. In addition, the solid winter line in FIG. 6 shows the result when the diode element 200 of this embodiment is used. In this case, no voltage is applied to the gate structure 70 of the diode 2 * 00. The dotted line in FIG. 6 indicates the result when the diode element 1000 (comparative example) shown in FIG. 15 is used. "'It is known from Fig. 6' that the applied voltage Vd is within any one of the operating ranges of the diode. In both cases, the characteristics of the diode element 2000 of this embodiment are superior to those of the diode element 1000. 1, 7 will be shown after the part of the graph in Figure 6 with an applied voltage of 0-7V or more. As shown in FIG. 7, when the applied voltage is 071, the diode element 200 of this embodiment is 2.3 times larger than the diode element 10000 (comparative example) per unit of electricity. That is, it can be understood that the diode element 200 of this embodiment has excellent characteristics. t ^ is a graph in which the vertical axis on the decimal scale is represented in the graph of FIG. 6 = pressure 0.6VM.0V. It can be cured by Figure 8; 2: the influence of the parasitic resistance in the well area, the current valley of the second body 70 and the current capacity of the diode element 1 000 (comparative example) 454332

The difference & more stomach. From this result, it can be understood that suppressing the influence of the parasitic resistance 40 of the N-well region 30 in the amount of the diode element in this embodiment can increase the current per diode = area (diode current Iβ). In addition, the "EX" in the vertical axis in Fig. 7 and Fig. 8 means ι〇 ~ χ, for example, 10E〇5 means j 〇χ 1〇 (Example 2), while referring to Fig. 9 and Fig. 10 Description of Winter Embodiment 2 of the present invention ^ FIG. 9 (a) schematically shows a diode element 300 included in the semiconductor device of Embodiment 3

FIG. 9 (b) schematically shows a cross section of the diode 300 along the line 2 (b) -b in FIG. 9 (a).

The diode element 300 of this embodiment picks a point formed in a semiconductor region of a soi (silicon on insulator) substrate and the diode element 100 of Example 1 formed in a N-well region 30. Or 200 different. That is, in this embodiment, a semiconductor layer (semiconductor region) 30 of a first conductivity type formed on an insulating film (or an insulating substrate) 62 is used as the semiconductor layer of the first conductivity type. The semiconductor layer 30 of the first conductivity type may be an N-type semiconductor layer or a P-type semiconductor layer. In order to make the description of this embodiment simple and clear, in the following (also including the embodiments described later), 'the main differences from the first embodiment' and the same points as the first embodiment are omitted or simplified. The diode element 300 has a first unit cell of a first conductivity type semiconductor layer 30 (thickness: for example, about 5 Onm) formed on an insulating film (eg, a buried oxide film, thickness: for example, about 100 nm) 62. 10 and second unit unit 20. Inter-unit area between the first unit unit 10 and the second unit unit 20

Page 19 454332 V. Description of the invention (17) The domain is formed by gate fabrication 70. The gate structure 70 may be provided with a gate wiring (not shown). In this embodiment, yttrium oxide 64 for element separation is formed around the semiconductor layer 30, and the P-type semiconductor substrate 60 is located under the insulating film (buried oxide film) 62. The first and second unit cells 10 and 20 are arranged in a checkered pattern in the semiconductor layer 30 as in the case of the first embodiment. In the diode element 300, an N + diffusion region 12 of a first unit cell 10 and a second unit cell 2 are formed in a semiconductor region (semiconductor layer 30) of a so substrate having no ν well region or ρ well region. Of p + diffusion region 22. Therefore, the area of the outer peripheral surface of each of the N + diffusion region 12 and the P + diffusion region 22 contributes to the PN junction area, which can increase the pN junction area. As a result, the current capacity of the diode device can be increased. In addition, the structure of the diode element 30 () is also the same as that of the above-mentioned embodiment. Since the first unit cell 10 and the second unit cell 20 can be arranged close to each other, the parasitic resistance of the semiconductor layer 30 can be reduced. 40%. The diode element 300 can be fabricated as shown in FIGS. 10 (3) to (6). In addition, in this example, a bipolar element 300 having a structure in which a gate wiring 56 is formed on the gate structure 70 is fabricated. First, as shown in FIG. 10 (a), for example, a buried oxide layer (^ 02 film) 62 and a semiconductor region (semiconductor layer) formed thereon are formed on a p-type semiconductor substrate (p-type rare substrate) 60. 30% of the SOI substrate. Next, as shown in FIG. 10 (b), an oxide film 64 for element separation is selectively formed on a part of the semiconductor region 30 of the SOI substrate. Next, as shown in FIG. 10 (c), the first unit cell 1 is formed. A part of the inter-cell area between 0 and the second unit cell 20 forms a gate structure. 454332. Description of the invention (18) Next, as shown in FIG. 10 (d), the gate structure 70 is used as a part of the cover. The N + diffusion region 12 is selectively formed in a part of the semiconductor layer 30 (the first unit cell 1). ) And p + diffusion region 22 (second unit cell). In addition, in the case where an SO substrate is used as in this embodiment, and the element separation region oxide film 32 is formed as in the diode element 100 of the above-mentioned embodiment 1. Compared with the method, the method of forming the gate structure 70 without forming an oxide film in the element separation region is better in the manufacturing process. / Second, as shown in FIG. 10 (e), after the insulating film 54 is deposited on the SOI substrate. Selectively forming a contact hole in the insulating film 54 and then forming a wiring

50 (including the contact portion 52) and the gate wiring 56. In this way, a diode element 300 can be obtained. (Embodiment 3) A third embodiment of the present invention will be described with reference to Figs. 11 to 13. In the above-mentioned embodiment, the first unit cell 10 and the second unit cell 20 are used to form a 7L diode ', but a bipolar transistor element can also be formed using this structure. FIG. 11 (a) schematically shows the upper surface of the bipolar transistor element 400 included in the semiconductor device of Example 3, and FIG. 11 (b) schematically shows the double electrode along the line b-b 'in FIG. H (a). Cross section of a polar transistor element 400. As shown in FIGS. 11 (a) and (b), if the first unit cell 10 is the base, the second unit cell 20 is the emitter, and A P-type semiconductor substrate (a second-conductivity-rich conductor layer) 60 is used as a collector to form a bipolar transistor element 40 (). In order to make the base (B), the emitter (E), and the collector (c The relationship between) is more clear.

454332 5. Description of the invention Step (19) shows the structure of the bipolar transistor element 400 in the mode.

In the bipolar transistor element 400 shown in FIG. Π, the wiring 50a for the emitter and the contact area 24 of the second unit cell 20 are electrically connected, and the wiring 50b for the base is in contact with the first unit cell 10. The area 14 is electrically connected. The collector wiring 50c and the p + diffusion region 34 formed in the P-well region 36 adjacent to the N-well region 30 are electrically connected. Therefore, the collector wiring 50c and the P-type semiconductor substrate 60 are connected to each other. Connect electrically.

In the bipolar transistor element 400, one of the first dry level cell 10 and the second dry position cell 20 is set as a base (B) or an emitter. As shown in the description of the above embodiment, since the first unit cell 10 and the second unit cell 20 can be disposed close to each other, the parasitic resistance 40 of the N-well region 30 can be reduced, and as a result, excellent current characteristics can be provided. Bipolar transistor element. In addition, in the structure shown in FIG. 1 ', an element separation region oxide film 32' is provided between the first unit cell 10 and the second unit cell 20, but the element separation region oxide film 32 'is not provided, and the inter-cell region is provided. Structure with gate structure 70 installed

However, as shown in FIG. 13, the bipolar transistor element 450 can also be formed using a dual-well structure. That is, in the p-type conductor substrate 60, N is formed as a semiconductor layer of the second conductivity type. After the pluton region 31, a p-well region 30 is formed in the N-well region 31 as a semiconductor layer of the first conductivity type. In this dual-well structure, a first unit cell (base unit Η 0 and a second unit unit (emitter) 20) are provided in a p-well region 30 which is a semiconductor layer of a first conductivity type. 31 as a collector can constitute a bipolar transistor element. In the case of this structure, it is also the same as the bipolar transistor element 400, because it can make the ρ well area

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It is possible to provide a bipolar electric field 30 with excellent current characteristics, which has reduced parasitic resistance and a crystal element. (Embodiment 4) Referring to FIG. 14, the embodiment 4 of the present invention ^, τ. ^ ^ ^ ΛI | month. In the above-mentioned embodiment, the first unit cell and the second unit cell 20 are arranged alternately in the semiconductor layer 30 of the electrical type, and a structure in which the first unit cell 10 and the second are in a checkered pattern (for example, refer to Round!), But in the present embodiment, the first conductive layer + conductive layer 30 of the conductive type 30 is formed at a relatively large 70, and a first conductive layer 30 is formed in the first unit 10 Structure of the unit cell 20. 14 (a) schematically shows the top of the diode element 500 included in the semiconductor device of this embodiment, and FIG. 14 (b) schematically shows b-b 'along FIG. 14 (^). A cross-section of a line diode device 500. The diode element 500 has a first unit cell 10 in a semiconductor layer (N-well region) 30 of a first conductivity type and a plurality of second unit cells 2 formed in the first unit cell 10. . In this embodiment, the shape of the first unit cell 10 seen from the direction of the substrate normal is, for example, a square (side length: about 5 inches), and the shape of the second unit cell 20 is also a square (side length: about 25 / £ m). The second unit cell 20 is formed, for example, in the first unit cell 10. The interval 15 between the first unit cell 10 and the second unit cell 20 is, for example, about 2 m. In the structure of the diode element 500, the distance from the center portion of the N + diffusion region 12 which becomes the cathode to the P + diffusion region 22 which becomes the anode can be shortened compared to the case of the structure of the diode element 1000 shown in FIG. Inco

V. Description of the invention (21) Reducing the parasitic resistance of the semiconductor layer (N-well region) 30 of the first conductivity type can provide a diode element that can increase the current capacity per unit area. [Industrial Applicability] According to the present invention, a semiconductor device including a diode device with high performance and a small occupied area is provided. A diode device with high performance and a small occupied area, for example, can be used as one of the analog / digital analog LSI analog circuit parts realized by CMOS process. It can provide a diode device with higher performance and smaller die area. . 〇

d54332 Brief description of the diagram FIG. 1 (a) schematically shows the top of the semiconductor device body 100 of the second embodiment, and FIG. 1 (b) schematically shows the diagram along FIG. 1 (a-pole b-b ' The cross section of the diode device 100 is shown in the figure. Figures 2 (a) to (e) are cross-sectional views illustrating the manufacturing process of the diode device 100: Figure 3 (a) of the method Example! Above the two-body element 200 included in the semiconductor device, FIG. 3 (b) schematically shows a cross-section of the diode element 200 along the line of FIG. 3 (a-b '. FIG. 4 (a) to (F) is a cross-sectional view for explaining the manufacturing process of the diode device 2000. ^ Figure 5 is a circuit diagram for obtaining the voltage-current characteristics of the diode. Figure 6 shows the measurement using the circuit shown in Figure 5 The graph of the results of the voltage-current characteristics of the diode. Figure 7 is an enlarged view of a part in which the applied voltage of the figure of FIG. 6 is about 0 7v. Figure 8 shows the applied voltage of the figure of FIG. 6. A graph of the range. 'Fig. 9 (a) schematically shows the upper surface of the diode element 300 included in the semiconductor device of Example 3, and Fig. 9 (b) schematically shows along & Cross section of the diode element 300 of the b-b 'line. Figs. 10 (a) to (e) are cross-sectional views illustrating the manufacturing process of the diode element 3qq. Fig. 11 (a) is in the mode Shows the upper surface of the bipolar transistor element 400 included in the semiconductor device of Example 3. 囷 11 (b) shows the mode along 囷

Page 25 454332 A brief description of the drawing of 11 (8) 1) ′. The cross section of the bipolar transistor element 400. FIG. 12 shows the bipolar transistor element 40 at a step. The sectional view. Circle 13 is a cross-sectional view of a bipolar transistor element 400 in a pattern. Fig. 14 (a) schematically shows the upper surface of the diode element 500 included in the semiconductor device of the fourth embodiment, and Fig. 14 (b) schematically shows the diode element along the bb line of Fig. 14 (&). Section of 500. FIG. 15 (a) schematically shows the top of the diode element 1000, and FIG. 15 (b) schematically shows the cross section of the diode element 1000 along the line ib_b of FIG. 15 (a).

Claims (1)

454332 VI. Application for patent Fanyuan 1. A semiconductor device with a semiconducting layer of the first conductivity type; at least one first unit unit having a semiconductor layer formed in the semiconducting layer of the first conductivity type A first semiconductor region of the first conductive plastic and a contact region for electrically connecting the first semiconductor region and the wiring; and at least one second unit cell having a semiconductor layer formed in the first conductivity type semiconductor layer A second semiconductor region of a second conductive pad and a contact region for electrically connecting the second semiconductor region and wiring; the first unit cell and the second unit cell cooperate to generate a diode element Functions. 2. For the semiconductor device according to item 1 of the patent application, wherein the at least one first unit cell is a plurality of first unit cells, and the at least one second unit cell is a plurality of second unit cells. 3. For the semiconductor device in the first or second scope of the application for a patent, wherein the size stipulating the respective sizes of the first semiconductor region and the second semiconductor region is in accordance with the design rules of the semiconductor device The minimum dimensions are substantially the same. 4. The semiconductor device according to item 1 or item 2 of the scope of patent application, wherein the shape of each of the first semiconductor region and the second semiconductor region seen from the normal direction is approximately square. 5. In the semiconductor device of claim 1 or 2, the first unit cell and the second unit cell are arranged in a grid pattern in the first type semiconductor layer. If you apply for a patent, please refer to 6 for the patent application. ° The semiconductor device of item 1 or item 2, which 454332 6. In the scope of patent application * f The first unit unit and the second unit unit are arranged at a predetermined distance from each other in the semiconductor layer of the first conductivity type; A gate structure having at least an insulating layer formed on the unit region and a conductive layer formed on the insulating layer is formed on an inter-unit region between the first unit unit and the second unit unit. The semiconducting chirp device of the scope of patent application No. 6 further includes a gate wiring electrically connected to the gate structure. 8. If a semiconductor device according to item 1 of the patent application is filed, a plurality of the second unit cells are formed in the first half-conductor area of the first unit cells. 9. If the semiconductor device in the scope of the patent application item 1 or item 2 further includes a semiconductor layer of the second conductivity type, a semiconductor layer of the first conductivity type is formed on the semiconductor layer of the second conductivity type. 10. The semiconductor device according to item 9 of the scope of patent application, wherein the first unit cell formed in the semiconductor layer of the first conductivity type is used as a base, and the second unit cell is used as an emitter. F The second The conductive type semiconductor layer functions as a collector. 11. The semiconductor device according to item 9 of the patent application scope, wherein * «the semiconductor layer of the second conductivity type is a semiconductor substrate; the semiconductor layer of the first conductivity type is a well region formed in the semiconductor substrate 0 12. For example, for a semiconductor device with the scope of the first or second patent application, its MU Page 28 d6A332 6. In the scope of the patent application, the semiconductor layer of the first conductivity type is formed on the insulating layer. 13. The semiconductor device according to item 1 or item 2 of the patent application scope, further comprising an analog circuit portion and a digital circuit portion, forming the diode element in the analog circuit portion, and manufacturing the analog circuit portion and This digital circuit section. Page 29