JP2007281259A - Electrostatic protective element and electrostatic protective circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase electrostatic resistance and improve the protective characteristics of an electrostatic protective element and an electrostatic protective circuit, in relation to the electrostatic protective element for protecting an internal circuit from static and the electrostatic protective circuit. <P>SOLUTION: There is provided an electrostatic protective element 12 comprising an n-type buried diffusion layer 22 provided in a semiconductor substrate 21, an n-type epitaxial growth layer 23, a p-type isolation layer 24, an n-type cathode contact layer 27, and a p-type anode contact layer 26. A groove 28 surrounding the n-type buried diffusion layer 22 is provided between the n-type cathode contact layer 27 and the p-type isolation layer 24. The bottom face 28A of the groove 28 and the bottom face 22A of the n-type buried diffusion layer 22 form one substantially flat surface. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electrostatic protection element and an electrostatic protection circuit, and more particularly to an electrostatic protection element and an electrostatic protection circuit that protect internal circuits from static electricity.

  FIG. 24 is a cross-sectional view of a conventional protection circuit. In FIG. 24, P is a PN junction portion (hereinafter referred to as “region P”) through which a surge current passes when a negative surge is applied, Q and S are directions in which the surge current flows, and R is a positive surge. PN junction portions (hereinafter referred to as “region R”) through which a surge current passes when applied are shown.

  Referring to FIG. 24, an electrostatic protection circuit 100 includes a semiconductor substrate 101, a first diode-type electrostatic protection element 102 formed on the semiconductor substrate 101, and a second diode-type electrostatic protection element 103. Have The electrostatic protection circuit 100 is a circuit for protecting an internal circuit (not shown) from static electricity.

  The first diode type electrostatic protection element 102 is an element for protecting an internal circuit (not shown) from a negative surge. The first diode type electrostatic protection element 102 is connected to a wiring connecting a ground terminal (not shown) and an input / output terminal (not shown). The first diode type electrostatic protection element 102 is electrically connected to an internal circuit.

  The first diode-type electrostatic protection element 102 includes an N-type buried diffusion layer 105 formed on the semiconductor substrate 101, an N-type epitaxial growth layer 106 formed on the semiconductor substrate 101 and the N-type buried diffusion layer 105, An N-type epitaxial growth layer 106, a P-type isolation layer 107 formed on the semiconductor substrate 101, an anode contact layer 108, and a cathode contact layer 109 are included.

  The P-type isolation layer 107 is disposed so as to surround the N-type epitaxial growth layer 106 provided with the cathode contact layer 109. The anode contact layer 108 is formed by diffusing P-type impurities in the P-type isolation layer 107. The cathode contact layer 109 is formed by diffusing N-type impurities in the N-type epitaxial growth layer 106.

  In the first diode type electrostatic protection element 102 having such a configuration, when a negative surge is applied to an input / output terminal (not shown), a surge current is applied from the anode contact layer 108 to the cathode contact layer 109. To protect the internal circuit. At this time, the surge current passes through the PN junction corresponding to the region P.

  The second diode type electrostatic protection element 103 is an element for protecting an internal circuit (not shown) from a positive surge. The second diode-type electrostatic protection element 103 is connected to a wiring connecting a power supply terminal (not shown) and an input / output terminal (not shown). The second diode type electrostatic protection element 103 is electrically connected to the internal circuit.

  The second diode-type electrostatic protection element 103 includes an N-type buried diffusion layer 111 formed on the semiconductor substrate 101, an N-type epitaxial growth layer 106 formed on the semiconductor substrate 101 and the N-type buried diffusion layer 111, It has an N-type epitaxial growth layer 106 and a P-type isolation layer 112 formed on the semiconductor substrate 101, a cathode contact layer 113, and an anode contact layer 114. The P-type isolation layer 112 is disposed so as to surround the N-type epitaxial growth layer 106 provided with the cathode contact layer 113 and the anode contact layer 114. The cathode contact layer 113 is formed by diffusing N-type impurities in the N-type epitaxial growth layer 106. The anode contact layer 114 is formed by diffusing P-type impurities in the N-type epitaxial growth layer 106.

The second diode-type electrostatic protection element 103 configured as described above generates a surge current from the anode contact layer 114 to the cathode contact layer 113 when a positive surge is applied to an input / output terminal (not shown). To protect internal circuitry (not shown). At this time, the surge current passes through the PN junction portion corresponding to the region R (see, for example, Patent Document 1).
JP-A-9-116100

  By the way, the magnitude of the electrostatic resistance of the diode-type electrostatic protection element depends on the area of the PN junction portion through which the surge current passes. Specifically, the larger the area of the PN junction through which surge current passes, the greater the electrostatic resistance, and the protection characteristic of the diode-type electrostatic protection element (characteristic for protecting the internal circuit (not shown) from surge) is improves.

  However, in the conventional electrostatic protection circuit 100, since it is difficult to increase the area of the PN junction portion through which the surge current passes, sufficient electrostatic resistance cannot be obtained, and the first and second diode types There has been a problem that the protection characteristics of the electrostatic protection elements 102 and 103 cannot be improved.

  Therefore, the present invention has been made in view of the above points, and an object of the present invention is to provide an electrostatic protection element and an electrostatic protection circuit capable of increasing the electrostatic resistance and improving the protection characteristics. .

  According to one aspect of the present invention, an N-type buried diffusion layer (22) provided in a semiconductor substrate (21) and the semiconductor substrate (21) and the N-type buried diffusion layer (22) are formed. An N-type epitaxial growth layer (23), a P-type isolation layer (24) formed on the N-type epitaxial growth layer (23), and an N-type cathode contact layer (27) formed on the N-type epitaxial growth layer (23) ) And a P-type anode contact layer (26) formed on the P-type isolation layer (24), wherein the N-type cathode contact layer (27) A groove (28) surrounding the N-type buried diffusion layer (22) is provided between the P-type isolation layer (24), and the bottom surface (28A) of the groove (28) and the N-type buried diffusion layer are provided. The bottom surface (22A) of the layer (22) is substantially flush with the bottom surface (28A) of the groove (28) or lower than the bottom surface (22A) of the N-type buried diffusion layer (22). An electrostatic protection element (12) characterized in that it is arranged is provided.

  According to the present invention, the groove (28) surrounding the N-type buried diffusion layer (22) is provided between the N-type cathode contact layer (27) and the P-type isolation layer (24). The bottom surface (28A) and the bottom surface (22A) of the N-type buried diffusion layer (22) are substantially flush, or the position of the bottom surface (28A) of the groove (28) is the bottom surface of the N-type buried diffusion layer (22). By arranging it below (22A), when a negative surge is applied, the surge current passes through the bottom surface (22A) of the N-type buried diffusion layer (22) having a large area, so that the surge current passes. The area of the PN junction increases. Thereby, since an electrostatic withstand amount becomes large, the protection characteristic of an electrostatic protection element (12) can be improved.

  According to another aspect of the present invention, an N-type buried diffusion layer (41) provided in a semiconductor substrate (21) and the semiconductor substrate (21) and the N-type buried diffusion layer (41) are formed. An N-type epitaxial growth layer (23); a P-type anode contact layer (43) formed on the N-type epitaxial growth layer (23); and a P-type anode contact layer formed on the N-type epitaxial growth layer (23). An N-type cathode contact layer (44) surrounding (43), and comprising an electrostatic protection element (13) comprising the P-type anode contact layer (43) and the N-type cathode contact layer (44). A groove (45) surrounding the P-type anode contact layer (43) is provided therebetween, and the depth (I) of the groove (45) is set to the depth (K) of the P-type anode contact layer (43). Or the depth (I) of the groove (45) is deeper than the depth (K) of the P-type anode contact layer (43) and does not reach the semiconductor substrate (21). An electrostatic protection element (13) is provided.

  According to the present invention, the groove (45) surrounding the P-type anode contact layer (43) is provided between the P-type anode contact layer (43) and the N-type cathode contact layer (44). The depth (I) is substantially equal to the depth (K) of the P-type anode contact layer (43), or the depth (I) of the groove (45) is set to the depth of the P-type anode contact layer (43) ( K) is deeper than K and does not reach the semiconductor substrate (21). When a positive surge is applied, the surge current passes through the bottom surface (43A) of the P-type anode contact layer (43) having a large area. Therefore, the area of the PN junction portion through which the surge current passes increases. Thereby, since an electrostatic withstand amount becomes large, the protection characteristic of an electrostatic protection element (13) can be improved.

  In addition, the said reference code is a reference to the last, and this invention is not limited to the aspect of illustration by this.

  The present invention can increase the electrostatic resistance of the electrostatic protection element and improve the protection characteristics of the electrostatic protection element.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing an equivalent circuit of a semiconductor device provided with an electrostatic protection circuit according to an embodiment of the present invention.

  Referring to FIG. 1, the electrostatic protection circuit 10 according to the present embodiment includes a first electrostatic protection element 12 and a second electrostatic protection element 13. The electrostatic protection circuit 10 is for protecting the internal circuit 11 from static electricity. The first and second electrostatic protection elements 12 and 13 are diode-type electrostatic protection elements.

  The first electrostatic protection element 12 is provided on a wiring connecting the input / output terminal 15 and the ground terminal 16 and is electrically connected to the internal circuit 11. The first electrostatic protection element 12 is an element for protecting the internal circuit 11 when a negative surge is applied to the input / output terminal 15.

  The second electrostatic protection element 13 is provided on a wiring connecting the input / output terminal 15 and the power supply terminal 17 and is electrically connected to the internal circuit 11. The second electrostatic protection element 13 is an element for protecting the internal circuit 11 when a positive surge is applied to the input / output terminal 15.

  FIG. 2 is a cross-sectional view of the electrostatic protection circuit according to the embodiment of the present invention. In FIG. 2, A is a region of the semiconductor substrate 21 where the first electrostatic protection element 12 is formed (hereinafter referred to as “first electrostatic protection element formation region A”), and B is a second electrostatic protection. A region of the semiconductor substrate 21 in which the element 13 is formed (hereinafter referred to as “second electrostatic protection element formation region B”) is shown.

  In FIG. 2, C is a path of surge current flowing through the first electrostatic protection element 12, D is a PN junction portion through which the surge current flowing through the first electrostatic protection element 12 passes, and E is the second A path of surge current flowing through the electrostatic protection element 13, F indicates a PN junction portion through which the surge current flowing through the second electrostatic protection element 13 passes.

  With reference to FIG. 2, the specific structure of the 1st and 2nd electrostatic protection elements 12 and 13 is demonstrated.

  The first electrostatic protection element 12 is formed in the first electrostatic protection element formation region A of the semiconductor substrate 21. As the semiconductor substrate 21, for example, a P-type semiconductor substrate made of silicon can be used.

  The first electrostatic protection element 12 includes an N-type buried diffusion layer 22, an N-type epitaxial growth layer 23, a P-type isolation layer 24, a P-type anode contact layer 26, an N-type cathode contact layer 27, a groove 28, an oxide film 30, insulating films 31 and 32, an anode electrode 36, and a cathode electrode 37.

  The N-type buried diffusion layer 22 is provided on the semiconductor substrate 21 corresponding to the first electrostatic protection element formation region A. The thickness M1 of the N-type buried diffusion layer 22 can be set to 4 μm, for example.

  The N type epitaxial growth layer 23 is provided so as to cover the semiconductor substrate 21 and the N type buried diffusion layer 22. The thickness M2 of the N-type epitaxial growth layer 23 can be set to 2 μm, for example.

  The P-type isolation layer 24 is provided on the semiconductor substrate 21 and the N-type epitaxial growth layer 23. The P-type isolation layer 24 is disposed so as to surround the N-type epitaxial growth layer 23 on which the N-type cathode contact layer 27 is formed.

  The P-type anode contact layer 26 is provided on the P-type isolation layer 24. The P-type anode contact layer 26 is in contact with the anode electrode 36. The P-type anode contact layer 26 is formed by diffusing P-type impurities in the P-type isolation layer 24.

  The N-type cathode contact layer 27 is provided on the N-type epitaxial growth layer 23 located on the N-type buried diffusion layer 22. The N-type cathode contact layer 27 is in contact with the cathode electrode 37. The N-type cathode contact layer 27 is formed by diffusing N-type impurities in the N-type epitaxial growth layer 23.

  The groove 28 is formed so as to penetrate the N-type epitaxial growth layer 23 located between the P-type anode contact layer 26 and the N-type cathode contact layer 27 and to penetrate a part of the semiconductor substrate 21. The groove 28 is disposed so as to continuously surround the N-type buried diffusion layer 22. The shape of the groove 28 is a frame shape. The bottom surface 28A of the groove 28 is formed so as to be substantially flush with the bottom surface 22A of the N-type buried diffusion layer 22. When the thickness M1 of the N-type buried diffusion layer 22 is 4 μm and the thickness M2 of the N-type epitaxial growth layer 23 is 2 μm, the depth H of the groove 28 can be 6 μm, for example. In this case, the width G of the groove 28 can be set to 3 μm, for example.

  As described above, the groove 28 continuously surrounding the N-type buried diffusion layer 22 is provided between the P-type anode contact layer 26 and the N-type cathode contact layer 27, and the bottom surface 28 A of the groove 28 and the N-type buried diffusion layer 22 are formed. By making the bottom surface 22A substantially flush with each other, when a negative surge is applied to the input / output terminal 15, the surge current passes through the bottom surface 22A of the N-type buried diffusion layer 22 having a large area and becomes a P-type anode contact layer. 26 flows to the N-type cathode contact layer 27.

  As a result, the area of the PN junction through which surge current passes can be increased as compared with the prior art, and the electrostatic resistance of the first electrostatic protection element 12 can be increased. 12 protection characteristics (characteristics of the first electrostatic protection element 12 that protects the internal circuit 11 from a negative surge) can be improved.

  The oxide film 30 is provided so as to cover the N-type epitaxial growth layer 23, the P-type isolation layer 24, the P-type anode contact layer 26, and a part of the N-type cathode contact layer 27.

  The insulating film 31 is provided so as to fill the groove 28. The upper surface 31A of the insulating film 31 is substantially flush with the upper surface of the oxide film 30. As the insulating film 31, for example, an oxide film can be used.

  The insulating film 32 is provided on the oxide film 30 and the insulating film 31. The insulating film 32 has openings 33 and 34. The opening 33 is formed so as to expose the upper surface of the P-type anode contact layer 26. The opening 34 is formed so as to expose the upper surface of the N-type cathode contact layer 27. As the insulating film 32, for example, an oxide film can be used.

  The anode electrode 36 is provided in the opening 33. The anode electrode 36 is in contact with the P-type anode contact layer 26. The cathode electrode 37 is provided in the opening 34. The cathode electrode 37 is in contact with the N-type cathode contact layer 27.

  According to the first electrostatic protection element 12 of the present embodiment, the groove 28 that continuously surrounds the N-type buried diffusion layer 22 is provided between the P-type anode contact layer 26 and the N-type cathode contact layer 27. By making the bottom surface 28A of the groove 28 and the bottom surface 22A of the N-type buried diffusion layer 22 substantially flush with each other, when a negative surge is applied to the input / output terminal 15, a PN through which a surge current passes than before. Since the area of the joint portion increases, the electrostatic resistance can be increased, and thus the protection characteristics of the first electrostatic protection element 12 can be improved.

  In the first electrostatic protection element 12 of the present embodiment, the case where the bottom surface 28A of the groove 28 and the bottom surface 22A of the N-type buried diffusion layer 22 are substantially flush has been described as an example. Even when the position of the bottom surface 28A of 28 is disposed below (deep position) below the bottom surface 22A of the N-type buried diffusion layer 22, the protection characteristics of the first electrostatic protection element 12 can be improved.

  The second electrostatic protection element 13 is formed in the second electrostatic protection element formation region B of the semiconductor substrate 21. The second electrostatic protection element 13 includes an N-type buried diffusion layer 41, an N-type epitaxial growth layer 23, a P-type isolation layer 42, a P-type anode contact layer 43, an N-type cathode contact layer 44, a groove 45, an oxide film 30, insulating films 32 and 46, an anode electrode 47, and a cathode electrode 48.

  The N-type buried diffusion layer 41 is provided on the semiconductor substrate 21 corresponding to the second electrostatic protection element formation region B. The N type epitaxial growth layer 23 is provided so as to cover the semiconductor substrate 21 and the N type buried diffusion layer 41.

  The P-type isolation layer 42 is provided on the semiconductor substrate 21 and the N-type epitaxial growth layer 23. The P-type isolation layer 42 is disposed so as to surround the N-type epitaxial growth layer 23 in which the P-type anode contact layer 43 and the N-type cathode contact layer 44 are formed.

  The P-type anode contact layer 43 is provided in the N-type epitaxial growth layer 23 located on the N-type buried diffusion layer 41. The P-type anode contact layer 43 is in contact with the anode electrode 47. The P-type anode contact layer 43 is formed by diffusing P-type impurities in the N-type epitaxial growth layer 23. The depth K of the P-type anode contact layer 43 can be set to 0.4 μm, for example.

  The N-type cathode contact layer 44 is provided in the N-type epitaxial growth layer 23 located on the N-type buried diffusion layer 41. The N-type cathode contact layer 44 is disposed so as to continuously surround the P-type anode contact layer 43. The N-type cathode contact layer 44 is in contact with the cathode electrode 48. The N-type cathode contact layer 44 is formed by diffusing N-type impurities in the N-type epitaxial growth layer 23.

  The trench 45 is formed in the N-type epitaxial growth layer 23 located between the P-type anode contact layer 43 and the N-type cathode contact layer 44. The groove 45 is disposed so as to continuously surround the P-type anode contact layer 43. The shape of the groove 45 is a frame shape. The bottom surface 45 </ b> A of the groove 45 is formed to be substantially flush with the bottom surface 43 </ b> A of the P-type anode contact layer 43. That is, the depth I of the groove 45 is substantially equal to the depth K of the P-type anode contact layer 43. When the depth K of the P-type anode contact layer 43 is 0.4 μm, the depth I of the groove 45 can be set to 0.4 μm, for example. In this case, the width J of the groove 45 can be set to 1 μm, for example.

  As described above, the groove 45 that continuously surrounds the P-type anode contact layer 43 is provided in the N-type epitaxial growth layer 23 located between the P-type anode contact layer 43 and the N-type cathode contact layer 44, and the bottom surface 45 </ b> A of the groove 45. And the bottom surface 43A of the P-type anode contact layer 43 are substantially flush with each other, so that when a positive surge is applied to the input / output terminal 15, the surge current is applied to the bottom surface 43A of the P-type anode contact layer 43 having a large area. Passes from the P-type anode contact layer 43 to the N-type cathode contact layer 44.

  Thereby, since the area of the PN junction portion through which surge current passes is increased as compared with the conventional case, the electrostatic resistance of the second electrostatic protection element 13 can be increased. 13 protection characteristics (characteristics of the second electrostatic protection element 13 that protects the internal circuit 11 from a positive surge) can be improved.

  The oxide film 30 is provided so as to cover the N-type epitaxial growth layer 23 and the P-type isolation layer 42 and part of the P-type anode contact layer 43 and the N-type cathode contact layer 44.

  The insulating film 46 is provided so as to fill the groove 45. The upper surface 46A of the insulating film 46 is substantially flush with the upper surface of the oxide film 30. As the insulating film 46, for example, an oxide film can be used.

  The insulating film 32 is provided on the oxide film 30 and the insulating film 46. The insulating film 32 has openings 51 and 52. The opening 51 is formed so as to expose the upper surface of the P-type anode contact layer 43. The opening 52 is formed so as to expose the upper surface of the N-type cathode contact layer 44.

  The anode electrode 47 is provided in the opening 51. The anode electrode 47 is in contact with the P-type anode contact layer 43. The cathode electrode 48 is provided in the opening 52. The cathode electrode 48 is in contact with the N-type cathode contact layer 44.

  According to the second electrostatic protection element 13 of the present embodiment, the P-type anode contact layer 43 is continuous with the N-type epitaxial growth layer 23 located between the P-type anode contact layer 43 and the N-type cathode contact layer 44. When the negative surge is applied to the input / output terminal 15 by making the bottom surface 45A of the groove 45 and the bottom surface 43A of the P-type anode contact layer 43 substantially flush with each other, However, since the area of the PN junction portion through which the surge current passes increases, the electrostatic withstand capability can be increased, so that the protection characteristics of the second electrostatic protection element 13 can be improved.

  In the second electrostatic protection element 13 of the present embodiment, the case where the depth I of the groove 45 is substantially equal to the depth K of the P-type anode contact layer 43 has been described as an example. Even when the depth I is deeper than the depth K of the P-type anode contact layer 43 and does not reach the semiconductor substrate 21, the protection characteristics of the second electrostatic protection element 13 can be improved.

  According to the electrostatic protection circuit 10 of the present embodiment, the first and second electrostatic protection elements 12 and 13 having larger electrostatic resistance than the conventional electrostatic protection elements 102 and 103 (see FIG. 24) are provided. As a result, the internal circuit 11 can be accurately protected from negative surges and positive surges.

  3-23 is a figure which shows the manufacturing process of the electrostatic protection circuit based on Embodiment of this invention. 3 to 23, the same components as those of the electrostatic protection circuit 10 according to the embodiment of the present invention are denoted by the same reference numerals.

  First, in the process shown in FIG. 3, the N-type buried diffusion layer 22 and the P-type impurity layer 24A are formed on the semiconductor substrate 21 corresponding to the first electrostatic protection element formation region A by a well-known method. An N-type buried diffusion layer 41 and a P-type impurity layer 42A are formed in the semiconductor substrate 21 corresponding to the electrostatic protection element formation region B. The P-type impurity layer 24 </ b> A is formed so as to continuously surround the N-type buried diffusion layer 22. The P-type impurity layer 42A is formed so as to continuously surround the N-type buried diffusion layer 41. Next, an N-type epitaxial growth layer 23 is formed so as to cover the semiconductor substrate 21, the N-type buried diffusion layers 22 and 41, and the P-type impurity layers 24A and 42A. The thickness M1 of the N-type buried diffusion layer 22 can be set to 4 μm, for example. The thickness M2 of the N-type epitaxial growth layer 23 on the semiconductor substrate 21 can be set to 2 μm, for example.

  Next, in a step shown in FIG. 4, an oxide film 30 that protects the N-type epitaxial growth layer 23, a polysilicon film 57, and a resist film 58 having a groove 58A are sequentially formed on the N-type epitaxial growth layer 23. The groove 58A corresponds to the position where the groove 28 is formed. The thickness of the oxide film 30 can be set to 10 nm, for example. The thickness of the polysilicon film 57 can be set to 100 nm to 200 nm, for example.

  Next, in the process shown in FIG. 5, the polysilicon film 57 and the oxide film 30 are etched by dry etching using the resist film 58 as a mask, and the upper surface of the N-type epitaxial growth layer 23 is formed on the polysilicon film 57 and the oxide film 30. A groove 61 is formed to expose the.

  Next, in the process shown in FIG. 6, the N-type epitaxial growth layer 23 and the semiconductor substrate 21 are etched by dry etching using the resist film 58 as a mask to form the grooves 28. At this time, the depth H of the groove 28 is preferably set such that the bottom surface 28A of the groove 28 is substantially flush with the bottom surface 22A of the N-type buried diffusion layer 22. When the thickness M1 of the N-type buried diffusion layer 22 is 4 μm and the thickness M2 of the N-type epitaxial growth layer 23 is 2 μm, the depth H of the groove 28 can be 6 μm, for example. In this case, the width G of the groove 28 can be set to 3 μm, for example.

  Next, in the step shown in FIG. 7, the resist film 58 is removed. Next, in the process shown in FIG. 8, the insulating film 31 is formed so as to fill the groove 28 and the groove part 61. At this time, the insulating film 31 is also formed on the polysilicon film 57. As the insulating film 31, for example, an oxide film can be used.

  Next, in the step shown in FIG. 9, the insulating film 31 formed on the polysilicon film 57 is removed by the entire surface etch back. At this time, the upper surface 31 A of the insulating film 31 filling the trench 28 is made to be substantially flush with the upper surface of the oxide film 30. Next, in the step shown in FIG. 10, the polysilicon film 57 is removed.

  Next, in the step shown in FIG. 11, a polysilicon film 63 and a resist film 64 having a groove 64A are sequentially formed on the structure shown in FIG. The groove portion 64 </ b> A corresponds to the formation position of the groove 45. The thickness of the polysilicon film 63 can be set to 100 nm to 200 nm, for example.

  Next, in the process shown in FIG. 12, a groove 66 exposing the N-type epitaxial growth layer 23 is formed in the polysilicon film 63 and the oxide film 30 by the same method as the process shown in FIGS. Next, a groove 45 is formed in the N type epitaxial growth layer 23. At this time, the depth I of the groove 45 is preferably formed so that the bottom surface 45A of the groove 45 is substantially flush with the bottom surface 43A of the P-type anode contact layer 43. When the depth K of the P-type anode contact layer 43 is 0.4 μm, the depth I of the groove 45 can be set to 0.4 μm, for example. In this case, the width J of the groove 45 can be set to 1 μm, for example.

  Next, in the step shown in FIG. 13, the insulating film 46 is formed so as to fill the groove 45 by the same method as the steps shown in FIGS. 7 to 10 described above. At this time, the upper surface 46 A of the insulating film 46 is made to be substantially flush with the upper surface of the oxide film 30.

  Next, in the process shown in FIG. 14, a resist film 68 having groove portions 68A and 68B is formed on the structure shown in FIG. 13, and then N oxide is formed through the oxide film 30 exposed in the groove portions 68A and 68B. The type epitaxial growth layer 23 is doped with a P-type impurity. Subsequently, the resist film 68 is removed, and then the doped P-type impurities are diffused to form P-type impurity layers 24B and 42B. Thereby, the P-type isolation layer 24 composed of the P-type impurity layers 24A and 24B and the P-type isolation layer 42 composed of the P-type impurity layers 42A and 42B are formed. In FIG. 14, the resist film 68 is shown for convenience of explanation.

  Next, in the step shown in FIG. 15, a resist film 71 having an opening 71A and a groove 71B is formed on the oxide film 30 and the insulating films 31 and 46, and the oxide film 30 exposed to the opening 71A and the groove 71B. Then, the N-type epitaxial growth layer 23 is doped with N-type impurities. As a result, an N-type impurity region 72 is formed in the N-type epitaxial growth layer 23 located below the opening 71A, and an N-type impurity region 73 surrounding the groove 45 is formed in the N-type epitaxial growth layer 23 located below the groove 71B. Is done. The opening 71A corresponds to the position where the N-type cathode contact layer 27 is formed. The groove 71B corresponds to the position where the N-type cathode contact layer 44 is formed. Next, in the step shown in FIG. 16, the resist film 71 is removed.

  Next, in the process shown in FIG. 17, a resist film 75 having openings 75A and 75B is formed on the structure shown in FIG. 16, and then the oxide film 30 exposed through the openings 75A and 75B is interposed. The P type isolation layer 24 and the N type epitaxial growth layer 23 are doped with a P type impurity. As a result, a P-type impurity region 76 is formed in the P-type isolation layer 24, and a P-type impurity region 78 is formed in the N-type epitaxial growth layer 23. Next, in the step shown in FIG. 18, the resist film 75 is removed.

  Next, in the process shown in FIG. 19, the structure shown in FIG. 18 is heat-treated to diffuse the N-type impurity regions 72 and 73 and the P-type impurity regions 76 and 78, and thereby the P-type anode contact layers 26, 43 and N Type cathode contact layers 27 and 44 are formed. At this time, the depth K of the P-type anode contact layer 43 is preferably such that the bottom surface 43A of the P-type anode contact layer 43 is substantially flush with the bottom surface 45A of the groove 45.

  Next, in the step shown in FIG. 20, an insulating film 32 and a resist film 81 having openings 81A to 81D are sequentially formed on the structure shown in FIG. The opening 81 </ b> A is located above the P-type anode contact layer 26, and the opening 81 </ b> B is located above the N-type cathode contact layer 27. The opening 81C is located above the N-type cathode contact layer 44, and the opening 81D is located above the P-type anode contact layer 43.

  Next, in the step shown in FIG. 21, the insulating film 32 and the oxide film 30 are etched by dry etching using the resist film 81 as a mask until the insulating film 32 and the oxide film 30 penetrate, and the P-type anode contact layer 26 is formed. An exposed opening 33, an opening 34 exposing the N-type cathode contact layer 27, an opening 52 exposing the N-type cathode contact layer 44, and an opening 51 exposing the P-type anode contact layer 43 are formed. To do. Next, in the step shown in FIG. 22, the resist film 81 is removed.

  Next, in the step shown in FIG. 23, the anode electrode 36 is formed in the opening 33, the cathode electrode 37 is formed in the opening 34, the anode electrode 47 is formed in the opening 51, and the cathode electrode 48 is formed in the opening 52 by a known method. Form at the same time. Specifically, for example, a barrier metal (for example, a TiN film) is formed so as to cover the upper surface side of the structure shown in FIG. 22, and then a W film is formed on the barrier metal, and then on the insulating film 32 By removing the unnecessary barrier metal and W film formed in (1), anode electrodes (36, 47) and cathode electrodes (37, 48) are formed.

  Thereby, the first electrostatic protection element 12 is formed in the first electrostatic protection element formation region A, the second electrostatic protection element 13 is formed in the second electrostatic protection element formation region B, The electrostatic protection circuit 10 having the first and second electrostatic protection elements 12 and 13 is manufactured.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

  The present invention is applicable to electrostatic protection elements and electrostatic protection circuits that protect internal circuits from static electricity.

It is the figure which showed the equivalent circuit of the semiconductor device provided with the electrostatic protection circuit which concerns on embodiment of this invention. It is sectional drawing of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (1) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (3) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (4) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (5) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (The 8) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (10) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (11) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (12) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (13) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (14) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (15) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (16) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (17) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (18) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (19) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (20) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is FIG. (The 21) which shows the manufacturing process of the electrostatic protection circuit which concerns on embodiment of this invention. It is sectional drawing of the conventional protection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Electrostatic protection circuit 11 Internal circuit 12 1st electrostatic protection element 13 2nd electrostatic protection element 15 Input / output terminal 16 Ground terminal 17 Power supply terminal 21 Semiconductor substrate 22, 41 N-type buried diffusion layer 22A, 28A, 43A, 45A Bottom 23 N type epitaxial growth layer 24, 42 P type isolation layer 24A, 24B, 42A, 42B P type impurity layer 26, 43 P type anode contact layer 27, 44 N type cathode contact layer 28, 45 groove 30 Oxide film 31, 32, 46 Insulating film 31A, 46A Upper surface 33, 34, 51, 52, 71A, 75A, 75B, 81A-81D Opening 36, 47 Anode electrode 37, 48 Cathode electrode 57, 63 Polysilicon Film 58, 64, 68, 71, 75, 81 Resist film 58A, 61, 64A 66, 68A, 68B, 71B Groove 72, 73 N-type impurity region 76, 78 P-type impurity region A First electrostatic protection element formation region B Second electrostatic protection element formation region H, K, I depth G , J width M1, M2 thickness

Claims (3)

An N-type buried diffusion layer provided on a semiconductor substrate; an N-type epitaxial growth layer formed so as to cover the semiconductor substrate and the N-type buried diffusion layer; and a P-type isolation layer formed on the N-type epitaxial growth layer; An electrostatic protection element comprising: an N-type cathode contact layer formed on the N-type epitaxial growth layer; and a P-type anode contact layer formed on the P-type isolation layer,
Providing a groove surrounding the N-type buried diffusion layer between the N-type cathode contact layer and the P-type isolation layer;
The bottom surface of the groove is substantially flush with the bottom surface of the N-type buried diffusion layer, or the bottom surface of the groove is disposed below the bottom surface of the N-type buried diffusion layer. Electric protection element. An N-type buried diffusion layer provided on a semiconductor substrate; an N-type epitaxial growth layer formed so as to cover the semiconductor substrate and the N-type buried diffusion layer; and a P-type anode contact layer formed on the N-type epitaxial growth layer; An N-type cathode contact layer formed on the N-type epitaxial growth layer and surrounding the P-type anode contact layer,
A groove surrounding the P-type anode contact layer is provided between the P-type anode contact layer and the N-type cathode contact layer,
The depth of the groove is substantially equal to the depth of the P-type anode contact layer, or the depth of the groove is deeper than the depth of the P-type anode contact layer and does not reach the semiconductor substrate. An electrostatic protection element. The electrostatic protection element according to claim 1;
An electrostatic protection circuit comprising the electrostatic protection element according to claim 2.

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