JPS5637622A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5637622A
JPS5637622A JP11288979A JP11288979A JPS5637622A JP S5637622 A JPS5637622 A JP S5637622A JP 11288979 A JP11288979 A JP 11288979A JP 11288979 A JP11288979 A JP 11288979A JP S5637622 A JPS5637622 A JP S5637622A
Authority
JP
Japan
Prior art keywords
groove
layers
semiconductor
regions
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11288979A
Other languages
Japanese (ja)
Inventor
Akira Muramatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11288979A priority Critical patent/JPS5637622A/en
Publication of JPS5637622A publication Critical patent/JPS5637622A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To try the improvement of junction characteristics by forming a groove on the surface of a semiconductor layer by spatter etching wherein a conductive type semiconductor or a semiconductor region having different impurity density is formed in the groove. CONSTITUTION:After N<-> silicon layers 12A, 12B are unitedly and epitaxially grown with predetermined thickness on the surface of a substrate 10 through N<+> buried layers 11A, 11B, P type regions 13, 14 are simultaneously formed on the layers 12A, 12B respectively. Furthermore, N<+> type regions 15, 16 and 17 are selectively diffused to the regions 12A, 12B and 14 at the same time and the N<+> type regions 15, 16 and 17 are formed. After forming circuit elements such as diodes, transistors or the like by selective diffusion, a groove 19 is formed on the N<-> type epitaxial growth layers so that the groove 19 may surround the layers 12A, 12B respectively by reactive spatter etching consisting a photoresist arranged on an SiO2 film 18 as a mask and the groove 19 may also reach the substrate 10. The groove 19 is formed with predetermined width and depth. Furthermore, a conductive type semiconductor or a semiconductor having different impurity density is formed in the groove 19.
JP11288979A 1979-09-05 1979-09-05 Manufacture of semiconductor device Pending JPS5637622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11288979A JPS5637622A (en) 1979-09-05 1979-09-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11288979A JPS5637622A (en) 1979-09-05 1979-09-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5637622A true JPS5637622A (en) 1981-04-11

Family

ID=14598045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11288979A Pending JPS5637622A (en) 1979-09-05 1979-09-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5637622A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007281259A (en) * 2006-04-07 2007-10-25 Mitsumi Electric Co Ltd Electrostatic protective element and electrostatic protective circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS499586A (en) * 1972-05-24 1974-01-28

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS499586A (en) * 1972-05-24 1974-01-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007281259A (en) * 2006-04-07 2007-10-25 Mitsumi Electric Co Ltd Electrostatic protective element and electrostatic protective circuit

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