JPS5613761A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5613761A
JPS5613761A JP9052679A JP9052679A JPS5613761A JP S5613761 A JPS5613761 A JP S5613761A JP 9052679 A JP9052679 A JP 9052679A JP 9052679 A JP9052679 A JP 9052679A JP S5613761 A JPS5613761 A JP S5613761A
Authority
JP
Japan
Prior art keywords
type
regions
region
diffusion
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9052679A
Other languages
Japanese (ja)
Inventor
Yoshitaka Tawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP9052679A priority Critical patent/JPS5613761A/en
Publication of JPS5613761A publication Critical patent/JPS5613761A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To reduce the number of processes needed in forming the first and second diffused regions on a substrate by employing a diffusion source containing both P-type and N-type impurities, and utilizing the difference of diffusion coefficient between them. CONSTITUTION:On an N<+>-type Si substrate 1 an N<->-type layer 2 is provided by epitaxial growth, the whole of which is used as a collector region of an NPN-type transistor, and the layer 2 is coated with an oxide film 3, in which two (or an annular) openings are made, and P<+>-type regions 4a and 4b are provided in the exposed portions of the layer 2 by diffusion. Then a P-type base region 6 is provided in the portion of the layer 2 surrounded by the regions 4a and 4b, and in the base region 6 an N-type emitter region 7 is provided by diffusion respectively. At this time, in the region of the film 3 corresponding to the regions 6 and 7 an opening is made, which is coated with a diffusion source 5 containing P-type and N-type impurities. After that, the impurities are diffused on heating to form the regions 6 and 7 respectively by utilizing the diffusion coefficient difference. Then electrodes 8 of Al or the like are provided in each region.
JP9052679A 1979-07-16 1979-07-16 Preparation of semiconductor device Pending JPS5613761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9052679A JPS5613761A (en) 1979-07-16 1979-07-16 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9052679A JPS5613761A (en) 1979-07-16 1979-07-16 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5613761A true JPS5613761A (en) 1981-02-10

Family

ID=14000866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9052679A Pending JPS5613761A (en) 1979-07-16 1979-07-16 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5613761A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57186230A (en) * 1981-05-13 1982-11-16 Matsushita Electric Ind Co Ltd Metallic thin film type magnetic recording medium and its manufacture
JPS589216A (en) * 1981-07-07 1983-01-19 Matsushita Electric Ind Co Ltd Metallic thin film type magnetic recording medium
JPS58153323A (en) * 1982-03-06 1983-09-12 Ulvac Corp Ion plating device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57186230A (en) * 1981-05-13 1982-11-16 Matsushita Electric Ind Co Ltd Metallic thin film type magnetic recording medium and its manufacture
JPH0325848B2 (en) * 1981-05-13 1991-04-09 Matsushita Electric Ind Co Ltd
JPS589216A (en) * 1981-07-07 1983-01-19 Matsushita Electric Ind Co Ltd Metallic thin film type magnetic recording medium
JPH0326454B2 (en) * 1981-07-07 1991-04-10 Matsushita Electric Ind Co Ltd
JPS58153323A (en) * 1982-03-06 1983-09-12 Ulvac Corp Ion plating device

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