JPS5491186A - Insulating gate-type field effect semiconductor device - Google Patents

Insulating gate-type field effect semiconductor device

Info

Publication number
JPS5491186A
JPS5491186A JP16022577A JP16022577A JPS5491186A JP S5491186 A JPS5491186 A JP S5491186A JP 16022577 A JP16022577 A JP 16022577A JP 16022577 A JP16022577 A JP 16022577A JP S5491186 A JPS5491186 A JP S5491186A
Authority
JP
Japan
Prior art keywords
region
type
diffusion
mask
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16022577A
Other languages
Japanese (ja)
Inventor
Kazuo Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16022577A priority Critical patent/JPS5491186A/en
Publication of JPS5491186A publication Critical patent/JPS5491186A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce a source junction capacity to make a high-speed operation possible and eliminate the operation faulty dependent upon punch through by growing single crystal and poly-crystal Si layers on an insulating film which has an aperture and forming a double-diffusion-type IGFET there. CONSTITUTION:Though thick SiO2 film 20 is buried in a prescribed region of P<+>- type si substrate 11 and a N<->-type layer is grown epitaxially throughout the surface, single crystal Si layer 21 and poly-crystal Si layer 22 are grown on exposed substrate 11 and film 20 respectively. Next, these layers are subjected to mesa etching and are made into island-shaped patterns, and these patterns are covered with diffusion mask 23, and P-type region 15, which becomes the channel of the driver-side FET, between layers 21 and 22 is formed by diffusion. After that, mask 23 is updated to mask 23' to form N-type source region 12 and drain region 13 of the driver-side FET and source region 13' and drain region 14 of the load-side FET by diffusion. Next, mask 23' and oxide film 24 generated at this time are removed to cause gate oxide film 26 to adhere to the gate region.
JP16022577A 1977-12-28 1977-12-28 Insulating gate-type field effect semiconductor device Pending JPS5491186A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16022577A JPS5491186A (en) 1977-12-28 1977-12-28 Insulating gate-type field effect semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16022577A JPS5491186A (en) 1977-12-28 1977-12-28 Insulating gate-type field effect semiconductor device

Publications (1)

Publication Number Publication Date
JPS5491186A true JPS5491186A (en) 1979-07-19

Family

ID=15710407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16022577A Pending JPS5491186A (en) 1977-12-28 1977-12-28 Insulating gate-type field effect semiconductor device

Country Status (1)

Country Link
JP (1) JPS5491186A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074664A (en) * 1983-09-30 1985-04-26 Toshiba Corp Manufacture of complementary type mos semiconductor device
JPS6477156A (en) * 1987-09-18 1989-03-23 Toshiba Corp Semiconductor device and manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074664A (en) * 1983-09-30 1985-04-26 Toshiba Corp Manufacture of complementary type mos semiconductor device
JPH0527265B2 (en) * 1983-09-30 1993-04-20 Tokyo Shibaura Electric Co
JPS6477156A (en) * 1987-09-18 1989-03-23 Toshiba Corp Semiconductor device and manufacture thereof

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