JPS6477156A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To decrease a dimensional error of an element isolating region by a method wherein an element isolating insulation film is formed on a surface of a silicon semiconductor substrate, then a silicon layer is laminated on the whole face of the above substrate through an epitaxial growth method, and the silicon layer is divided into element forming regions isolated from each other. CONSTITUTION:An element isolating field oxide film 11 is formed on the surface of a P-type silicon substrate 10 through a selective oxidation. A single crystal silicon layer 12A is deposited on the exposed face of the silicon substrate 10 under such a condition as it grows epitaxially. In this process, the part of a silicon layer 12B on the field oxide film 11 is turned into polycrystalline silicon. Next, the above silicon layers 12A and 12B are patterned through a selective etching method, the silicon layer is left unremoved only on each element forming region, and the other part of the layer is removed. The layer left in this process is made to be regions used for forming elements, a wiring among the elements, resistor, and capacitors of a MOS transistor or the like.