JPS6484659A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6484659A
JPS6484659A JP62240837A JP24083787A JPS6484659A JP S6484659 A JPS6484659 A JP S6484659A JP 62240837 A JP62240837 A JP 62240837A JP 24083787 A JP24083787 A JP 24083787A JP S6484659 A JPS6484659 A JP S6484659A
Authority
JP
Japan
Prior art keywords
mostr
resist
etching
covered
subjected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62240837A
Other languages
Japanese (ja)
Inventor
Akito Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62240837A priority Critical patent/JPS6484659A/en
Publication of JPS6484659A publication Critical patent/JPS6484659A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve a device in yield by a method wherein an insulating film is deposited on the whole face and then one of plural MOS transistor forming regions are covered with a resist film and the other is subjected to etching for the formation of a side wall of a gate electrode, and the former region is processed in the same manner as the latter region. CONSTITUTION:A p-type well 3, an element isolating insulation film 2, a channel doped layer 4, a gate oxide film 5, a gate electrode 6, and a low concentrated n-type layer 8 are formed on an n-type Si substrate 1, and then a resist 7 is removed for the formation of an oxide film 9 on the whole face. Then, a p channel MOS transistor (hereinafter referred to as 'p-MOSTr') side is covered with a photoresist 7a, and only an n-MOSTr side is subjected to etching for forming a side wall 9 and an n-type layer 10 in succession. Next, the resist 7a is removed, an oxide film 9a is deposited on the whole face, then the n- MOSTr side is covered with a photoresist 7b, and only the p-MOSTr side is subjected to etching for the formation of a side wall 9b and a p-type layer 11 in succession. Thereafter, the resist 7b is removed and then an Al wiring or the like is accomplished.
JP62240837A 1987-09-28 1987-09-28 Manufacture of semiconductor device Pending JPS6484659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62240837A JPS6484659A (en) 1987-09-28 1987-09-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62240837A JPS6484659A (en) 1987-09-28 1987-09-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6484659A true JPS6484659A (en) 1989-03-29

Family

ID=17065438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62240837A Pending JPS6484659A (en) 1987-09-28 1987-09-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6484659A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01283956A (en) * 1988-05-11 1989-11-15 Matsushita Electric Ind Co Ltd Semiconductor device and preparation thereof
JPH06268165A (en) * 1991-02-27 1994-09-22 Samsung Electron Co Ltd Preparation of semiconductor transistor and its structure
JPH06342884A (en) * 1991-07-09 1994-12-13 Samsung Electron Co Ltd Mos semiconductor device and its manufacture
US5766991A (en) * 1990-05-11 1998-06-16 U.S. Philips Corporation CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain
JP2003100902A (en) * 2001-09-21 2003-04-04 Mitsubishi Electric Corp Manufacturing method for semiconductor device
KR100398571B1 (en) * 2001-04-24 2003-09-19 주식회사 하이닉스반도체 Method of manufacturing merged memory and logic device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01283956A (en) * 1988-05-11 1989-11-15 Matsushita Electric Ind Co Ltd Semiconductor device and preparation thereof
US5766991A (en) * 1990-05-11 1998-06-16 U.S. Philips Corporation CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain
JPH06268165A (en) * 1991-02-27 1994-09-22 Samsung Electron Co Ltd Preparation of semiconductor transistor and its structure
JPH06342884A (en) * 1991-07-09 1994-12-13 Samsung Electron Co Ltd Mos semiconductor device and its manufacture
KR100398571B1 (en) * 2001-04-24 2003-09-19 주식회사 하이닉스반도체 Method of manufacturing merged memory and logic device
US7998802B2 (en) 2001-09-21 2011-08-16 Renesas Electronics Corporation Method of manufacturing semiconductor device with offset sidewall structure
JP2003100902A (en) * 2001-09-21 2003-04-04 Mitsubishi Electric Corp Manufacturing method for semiconductor device
US8415213B2 (en) 2001-09-21 2013-04-09 Renesas Electronics Corporation Method of manufacturing semiconductor device with offset sidewall structure
US8541272B2 (en) 2001-09-21 2013-09-24 Renesas Electronics Corporation Method of manufacturing semiconductor device with offset sidewall structure
US8642418B2 (en) 2001-09-21 2014-02-04 Renesas Electronics Corporation Method of manufacturing semiconductor device with offset sidewall structure
US8859360B2 (en) 2001-09-21 2014-10-14 Renesas Electronics Corporation Method of manufacturing semiconductor device with offset sidewall structure
US8987081B2 (en) 2001-09-21 2015-03-24 Renesas Electronics Corporation Method of manufacturing semiconductor device with offset sidewall structure
US9214464B2 (en) 2001-09-21 2015-12-15 Renesas Electronics Corporation Method of manufacturing semiconductor device with offset sidewall structure
US9349816B2 (en) 2001-09-21 2016-05-24 Renesas Electronics Corporation Method of manufacturing semiconductor device with offset sidewall structure

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