JPS6410672A - Vertical mosfet - Google Patents
Vertical mosfetInfo
- Publication number
- JPS6410672A JPS6410672A JP16548687A JP16548687A JPS6410672A JP S6410672 A JPS6410672 A JP S6410672A JP 16548687 A JP16548687 A JP 16548687A JP 16548687 A JP16548687 A JP 16548687A JP S6410672 A JPS6410672 A JP S6410672A
- Authority
- JP
- Japan
- Prior art keywords
- well region
- impurity
- region
- introducing
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 abstract 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To enable the miniaturization of a chip without deteriorating the ON resistance and the breakdown voltage characteristics, by forming a source region in a well region by using an impurity introducing mask whose width is narrower than that of a first impurity introducing mask used for forming the well region. CONSTITUTION:On an N<+> substrate 1, an N-type layer 2 operating as a drain is formed. On the surface side of the N-type layer 2, a P-well region 3 is formed, on the central part of which a P<+> well region 4 is formed. The P-well region 3 is formed by introducing and diffusing P-type impurity. In this process, a first impurity introducing mask is used, in which a side wall 15a of SiO2 is arranged on the side part of a gate electrode 8. In a part from the P-well region 3 to the P<+> well region 4, an N<+> source region 5 is formed. On the P-well region 3 between the N<+> source region 5 and the N-type layer 2, a gate electrode 8 to induce a channel 6 is formed, via a gate insulating film 7. The N<+> source region 6 is formed by introducing and diffusing N-type impurity applying the gate electrode 8 to an impurity introducing mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16548687A JPS6410672A (en) | 1987-07-03 | 1987-07-03 | Vertical mosfet |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16548687A JPS6410672A (en) | 1987-07-03 | 1987-07-03 | Vertical mosfet |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6410672A true JPS6410672A (en) | 1989-01-13 |
Family
ID=15813316
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16548687A Pending JPS6410672A (en) | 1987-07-03 | 1987-07-03 | Vertical mosfet |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6410672A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0334376A (en) * | 1989-06-29 | 1991-02-14 | Nec Corp | Manufacture of vertical type field effect transistor |
US5032880A (en) * | 1989-05-23 | 1991-07-16 | Kabushiki Kaisha Toshiba | Semiconductor device having an interposing layer between an electrode and a connection electrode |
JPH06244429A (en) * | 1992-12-24 | 1994-09-02 | Mitsubishi Electric Corp | Insulated-gate semiconductor device and manufacture thereof |
JP4435847B2 (en) * | 2007-01-16 | 2010-03-24 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61156882A (en) * | 1984-12-28 | 1986-07-16 | Toshiba Corp | Double-diffused igfet and manufacture thereof |
JPS61278167A (en) * | 1985-06-04 | 1986-12-09 | Tdk Corp | Vertical semiconductor device and manufacture thereof |
JPS6246568A (en) * | 1985-08-23 | 1987-02-28 | Tdk Corp | Manufacture of vertical type semiconductor device |
-
1987
- 1987-07-03 JP JP16548687A patent/JPS6410672A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61156882A (en) * | 1984-12-28 | 1986-07-16 | Toshiba Corp | Double-diffused igfet and manufacture thereof |
JPS61278167A (en) * | 1985-06-04 | 1986-12-09 | Tdk Corp | Vertical semiconductor device and manufacture thereof |
JPS6246568A (en) * | 1985-08-23 | 1987-02-28 | Tdk Corp | Manufacture of vertical type semiconductor device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5032880A (en) * | 1989-05-23 | 1991-07-16 | Kabushiki Kaisha Toshiba | Semiconductor device having an interposing layer between an electrode and a connection electrode |
JPH0334376A (en) * | 1989-06-29 | 1991-02-14 | Nec Corp | Manufacture of vertical type field effect transistor |
JPH06244429A (en) * | 1992-12-24 | 1994-09-02 | Mitsubishi Electric Corp | Insulated-gate semiconductor device and manufacture thereof |
JP4435847B2 (en) * | 2007-01-16 | 2010-03-24 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
JPWO2008087763A1 (en) * | 2007-01-16 | 2010-05-06 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
US7981817B2 (en) | 2007-01-16 | 2011-07-19 | Panasonic Corporation | Method for manufacturing semiconductor device using multiple ion implantation masks |
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