JPS6451662A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS6451662A
JPS6451662A JP20827487A JP20827487A JPS6451662A JP S6451662 A JPS6451662 A JP S6451662A JP 20827487 A JP20827487 A JP 20827487A JP 20827487 A JP20827487 A JP 20827487A JP S6451662 A JPS6451662 A JP S6451662A
Authority
JP
Japan
Prior art keywords
trench
length
gate
transistor
longer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20827487A
Other languages
Japanese (ja)
Inventor
Kazuhiro Takenaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP20827487A priority Critical patent/JPS6451662A/en
Publication of JPS6451662A publication Critical patent/JPS6451662A/en
Pending legal-status Critical Current

Links

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To constitute a three-dimensional off set, and enable the high density integration and the high breakdown voltage operation, by arranging a trench between the gate region and the drain region on an Si substrate, and making the bottom and a part of the side-wall along the trench as off-set part. CONSTITUTION:An off-set part 6 is constituted of an impurity diffusion layer being an N<-> diffusion layer aII over the side-wall and the bottom part of a trench 7. On an Si substrate 1, an N<+> drain region 2 is arranged on the opposite side of the trench 7 to a gate electrode 5, and a transistor is formed whose off set length is longer than the plane size. Therefore a transistor having an off-set whose effective length is longer than the usual length although a plane off-set length is short, is obtained. As a result, the distance between gate and drain becomes short, so that the high density integration and the high breakdown voltage operation are enabled.
JP20827487A 1987-08-24 1987-08-24 Semiconductor device and its manufacture Pending JPS6451662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20827487A JPS6451662A (en) 1987-08-24 1987-08-24 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20827487A JPS6451662A (en) 1987-08-24 1987-08-24 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS6451662A true JPS6451662A (en) 1989-02-27

Family

ID=16553523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20827487A Pending JPS6451662A (en) 1987-08-24 1987-08-24 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS6451662A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010002670A (en) * 1999-06-16 2001-01-15 김영환 Method for Manufacturing Semiconductor Device the same
JP2003249646A (en) * 2001-12-18 2003-09-05 Fuji Electric Co Ltd Semiconductor device
US6730961B2 (en) 2001-12-18 2004-05-04 Fuji Electric Co., Ltd. Semiconductor device
US6861702B2 (en) 2001-05-11 2005-03-01 Fuji Electric Co., Ltd. Semiconductor device
US7049202B2 (en) 2001-05-18 2006-05-23 Fuji Electric Co., Ltd. Method of manufacturing semiconductor device
JP2007080956A (en) * 2005-09-12 2007-03-29 Seiko Epson Corp Semiconductor device and its manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010002670A (en) * 1999-06-16 2001-01-15 김영환 Method for Manufacturing Semiconductor Device the same
US6861702B2 (en) 2001-05-11 2005-03-01 Fuji Electric Co., Ltd. Semiconductor device
US7049202B2 (en) 2001-05-18 2006-05-23 Fuji Electric Co., Ltd. Method of manufacturing semiconductor device
JP2003249646A (en) * 2001-12-18 2003-09-05 Fuji Electric Co Ltd Semiconductor device
US6730961B2 (en) 2001-12-18 2004-05-04 Fuji Electric Co., Ltd. Semiconductor device
JP2007080956A (en) * 2005-09-12 2007-03-29 Seiko Epson Corp Semiconductor device and its manufacturing method

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